Adder
• An adder is a digital combinational circuit that performs addition of numbers. Are used in
the arithmetic logic units or ALU.
• They are also utilized in other parts of the processor, where they are used to
calculate addresses, table indices, increment and decrement operators, and similar
operations.
• Although adders can be constructed for many number representations, such as binary-coded
decimal or excess-3, the most common adders operate on binary numbers.
• In cases where two's complement or ones' complement is being used to represent negative
numbers, it is trivial to modify an adder into an adder–subtractor.
• Basics of addition: - (A)x+ (B)x = ?
Half adder
• The simplest form of addition is addition of two binary digits, consists of four possible
elementary operations
1 1 0 0
+1 +0 +1 +0
• The first three operations produce a sum of two digits, but when both augend and addend bits
are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is
called a carry.
• It is a combinational circuit, which perform the arithmetic addition of two one-bit binary
numbers is referred to as an half-adder.
• So, in half adder inputs are adds two single binary bits A and B, and two outputs, sum (S) and
carry (C).
INPUTS OUTPUTS
A B Carry Sum
0 0
0 1
1 0
1 1
1. Cost of implementation a half adder is one EX-OR gate and one AND gate.
2. A half adder has only two inputs and there is no provision to add a carry coming from the
lower order bits when multi bit number addition is performed. For this reason, we have
designed a full adder.
Full adder
1. A full adder is a combinational logic circuit that performs the arithmetic sum of three input
bits.
2. Where An, Bn are the nth order bits of the number A and B respectively and Cn is the carry
generated from the addition of (n-1)th order bits.
3. It consists of three input bits, denoted by A (First operand), B (Second operand), C in
(Represents carry from the previous lower significant position).
• Two output bits are same as of half adder, which is Sum and Carryout.
• When the augend and addend number contain more significant digits, the carry obtained
from the addition of two bits is added to the next higher order pair of significant bits.
INPUTS OUTPUTS ab a’b’ a’b ab ab’
A B C in C out Sum cin 00 01 11 10
0 0 0 cin’ 0 0 2 6 4
0 0 1 cin 1 1 3 7 5
0 1 0
0 1 1
ab a’b’ a’b ab ab’
1 0 0
cin 00 01 11 10
1 0 1
cin’ 0 0 2 6 4
1 1 0
cin 1 1 3 7 5
1 1 1
INPUTS OUTPUTS
A B C in Sum C out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Four-bit parallel binary adder / Ripple adder
• As we know that full adder is capable of adding two 1 bit number and 1 previous carry, but in
order to add binary numbers with more than one bits, additional full adders must be
employed. For e.g. a four bit binary adder can be constructed using four full adders.
• Theses four full adders are connected in cascade, carry output of each adder is connected to
the carry input of the next higher-order adder.
• So a n-bit parallel adder is constructed using ‘n’ number of full adders.
• The longest propagation delay time in an adder is the time it takes the carry to propagate through the full adders.
For carry in a 4-bit adder we have 2 gate delays at each adder and for sum we have 1 gate delay.
• For an n -bit adder, there are 2n gate levels for the carry to propagate from input to output. And for Sum we
have 2n-1 Gate delays.
• There are some scope of improvement in adder like
Carry propagation delay Look ahead Carry Generator
• Can adder be modified to work as subtractor
• Adder/subtractor or ripple adder
Q A half adder is implemented with XOR and AND gates. A full adder is implemented with two half
adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The
propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is
implemented by using full adders. The total propagation time of this 4-bit binary adder in
microseconds is (GATE-2015) (2 Marks)