EXPERIMENT – 1

OBJECTIVE - Implementing HALF ADDER, FULL ADDER using basic logic gates.

THEORY –

HALF ADDER - A half adder is a digital circuit that adds two single-bit binary numbers. It
has two inputs, typically labeled A and B, and two outputs: the sum (S) and the carry (C).
 Sum (S): This output is the result of the bitwise addition of the two inputs. It is
obtained using an XOR (exclusive OR) operation:
S=A⊕B
 Carry (C): This output represents any carry-over value, which occurs if both input
bits are 1. It is obtained using an AND operation:
C=A∧B
Truth Table for a Half Adder:
A B Sum (S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
In summary, a half adder is used for adding two single-bit binary numbers, producing a sum
and a carry as outputs.

FULL ADDER - A full adder is a digital circuit that adds three input bits: two significant
bits and a carry bit from a previous addition. It has three inputs and two outputs.
1. Sum (S):
S=A⊕B⊕Cin
(This is the XOR of all three inputs.)
2. Carry-out (C_out):
Cout=(A∧B)∨(Cin∧(A⊕B))
(This is the OR of the AND of A and B, and the AND of the carry-in with the XOR of
A and B.)
Truth Table for Full Adder:
A B C Sum (S) Carry-out (C_out)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
A full adder adds three input bits, producing a sum and a carry-out. It can be used to add
multiple binary numbers in sequence (e.g., in multi-bit binary addition).
 EXPERIMENT – 2
OBJECTIVE – Implementing Binary to Gray, Gray to Binary code conversions.

THEORY –

BINARY TO GRAY CODE CONVERSION:

Binary to Gray code conversion is a method of encoding binary numbers to minimize errors
in digital systems, particularly in hardware like rotary encoders. In Gray code, only one bit
changes at a time between consecutive numbers.

Conversion Process:

1. The most significant bit (MSB) of the Gray code is the same as the MSB of the
binary number.
2. For each subsequent bit of the Gray code, it is obtained by performing an XOR
operation between the corresponding bit in the binary number and the bit just to its
left.

Example:
Convert the binary number 1011 to Gray code:
1. MSB: The Gray code's MSB is the same as the binary's MSB: 1.
2. Next bit: XOR of the 1st and 2nd binary bits: 1⊕0=1
3. Next bit: XOR of the 2nd and 3rd binary bits: 0⊕1=1
4. Next bit: XOR of the 3rd and 4th binary bits: 1⊕1=0

GRAY TO BINARY CODE CONVERSION:

Gray to binary conversion is the process of converting a Gray code number back into its
equivalent binary form. The conversion is done by applying a series of XOR operations.

Conversion Process:

1. The most significant bit (MSB) of the binary number is the same as the MSB of the
Gray code.
2. For each subsequent bit of the binary number, it is obtained by XORing the
corresponding Gray code bit with the previous binary bit.

Example:
Convert the Gray code 1110 to binary:
1. MSB: The binary MSB is the same as the Gray MSB: 1.
2. Next binary bit: XOR of the binary MSB (1) and the 2nd Gray code bit (1): 1⊕1=0
3. Next binary bit: XOR of the 2nd binary bit (0) and the 3rd Gray code bit (1): 0⊕1=1
4. Next binary bit: XOR of the 3rd binary bit (1) and the 4th Gray code bit (0): 1⊕0=1
So, the binary number for Gray code 1110 is 1011.
 EXPERIMENT – 3
OBJECTIVE – Implementing 3 – 8 line DECODER.

THEORY – A 3-to-8 line decoder is a digital circuit that takes a 3-bit binary input and
decodes it into one of eight output lines. It has 3 input bits and 8 output lines, where only one
output is active (high) at a time based on the input combination, and all other outputs are
inactive (low).
Operation:
 The 3 input bits (let’s call them A2, A1, A0) are used to select one of the 8 outputs.
 For each unique combination of the 3 input bits, one specific output line (from O0 to
O7) is set to 1, and all others are 0.
Truth Table:
A2 A1 A0 Outputs
0 0 0 O0=1
0 0 1 O1=1
0 1 0 O2=1
0 1 1 O3=1
1 0 0 O4=1
1 0 1 O5=1
1 1 0 O6=1
1 1 1 O7=1
Key Points:
 Only one output is active at one time based on the input.
 If the input to a 3-to-8 line decoder is 001, only the output corresponding to this input
will be active (high), and all the other outputs will be inactive (low).
 It is used in various applications like memory addressing, data selection, and binary-
to-decimal conversion.

The N×2N formula is typically associated with the number of outputs in a decoder,
particularly in cases where the decoder has N input lines and 2N output lines.

Formula Explanation:
In the context of a decoder:
 N represents the number of input lines.
N
 2 represents the number of possible output lines.
 Example: if N = 3
N×2N
3×23
3×8
 EXPERIMENT – 4
OBJECTIVE – Implementing 4*1 and 8*1 Multiplexer.

THEORY –

A multiplexer (MUX) is a digital device that selects one of many input signals and forwards
the selected input to a single output line. Multiplexers are used in digital circuits to route
signals efficiently based on control lines. Let's look at the 4-to-1 multiplexer (4:1 MUX) and
the 8-to-1 multiplexer (8:1 MUX).

4-to-1 Multiplexer (4:1 MUX)

A 4-to-1 multiplexer has:

 4 input lines: These are the data inputs from which the multiplexer will select one.
 1 output line: Only one of the inputs is sent to the output based on the selection.
2
 2 control (select) lines: Since 2 = 4, two selection lines are needed to choose one of
the four inputs.

8-to-1 Multiplexer (8:1 MUX)

An 8-to-1 multiplexer has:

 8 input lines: These are the data inputs from which the multiplexer will select one.
 1 output line: Only one of the 8 inputs is passed to the output.
3
 3 control (select) lines: Since 2 = 8, three selection lines are required to choose one
of the eight inputs.

Here are the common types of multiplexers:

1. 2-to-1 Multiplexer
2. 4-to-1 Multiplexer
3. 8-to-1 Multiplexer
4. 16-to-1 Multiplexer
5. 32-to-1 Multiplexer
6. 64-to-1 Multiplexer
7. 128-to-1 Multiplexer
8. n-to-1 Multiplexer (general form, where "n" can be any power of 2)

Here are the types of multipliers:

1. Binary Multiplier
2. Serial Multiplier
3. Parallel Multiplier
4. Array Multiplier
5. Booth's Multiplier
6. Modified Booth's Multiplier
7. Signed Multiplier
8. Floating Point Multiplier
 EXPERIMENT – 5
OBJECTIVE – Verify the excitation tables of various flip-flops.

THEORY – Flip-Flops Excitation Tables

Excitation tables describe the required inputs (J, K, D, S, R, etc.) for flip-flops to transition
from one state to another. Here, I'll summarize the excitation tables for the most common
types of flip-flops: SR, JK, D, and T flip-flops.

Flip-flops are bistable devices, meaning they have two stable states. They are used for storing
binary information in digital circuits. Flip-flops form the building blocks of memory units,
registers, and counters. A flip-flop changes its state based on inputs and a clock signal. There
are various types of flip-flops, each with unique properties and characteristics.

1. SR Flip-Flop (Set-Reset Flip-Flop)

The SR flip-flop has two inputs: S (Set) and R (Reset). It has two states: Q (current output)
and Q' (complement of the output).

SR Flip-Flop Excitation Table

Present State (Q) Next State (Q') Set (S) Reset (R)
0 0 0 0
0 1 1 0
1 0 0 1
1 1 0 0

 (S = 1, R = 1) is invalid as it causes an undefined state (both outputs are 1).

2. JK Flip-Flop

The JK flip-flop has inputs J and K, and it avoids the invalid state of the SR flip-flop by
having different behavior when both inputs are 1.

JK Flip-Flop Excitation Table

Present State (Q) Next State (Q') J K

0 0 0 0
0 1 1 0
1 0 0 1
1 1 1 1

 (J = 1, K = 1) causes the output to toggle.

3. D Flip-Flop (Data or Delay Flip-Flop)

The D flip-flop has a single input D and follows a simple rule where the output directly
follows the input on the clock edge.

D Flip-Flop Excitation Table

Present State (Q) Next State (Q') D

0 0 0
0 1 1
1 0 0
1 1 1

 (D = 1) sets the output to 1, and (D = 0) resets the output to 0.

4. T Flip-Flop (Toggle Flip-Flop)

The T flip-flop has a single input T and toggles its output when T = 1. When T = 0, the
output stays the same.

T Flip-Flop Excitation Table

Present State (Q) Next State (Q') T

0 0 0
0 1 1
1 0 1
1 1 0

 (T = 1) causes the output to toggle.

 (T = 0) holds the current state.

Summary of Excitation Tables:

 SR Flip-Flop: Has two inputs (Set and Reset), but (S = 1, R = 1) is invalid.

 JK Flip-Flop: Similar to SR, but the (J = 1, K = 1) state causes toggling.
 D Flip-Flop: The output simply follows the input D.
 T Flip-Flop: The output toggles when T = 1, and holds when T = 0.
Each flip-flop type has different input conditions for transitioning between states, providing
versatility in sequential circuit design.
 EXPERIMENT – 6
OBJECTIVE – Design of an 8 bit input/output system with four 8 bit internal registers.

THEORY – This system is essentially a simple model of an embedded system with input and
output capabilities, as well as a small set of registers for data processing. The system will be
designed with the following components:
1. Input Block (8-bit Input): This is the part of the system where data is received. It could
be from an external source like a sensor, keyboard, or communication interface.
2. Output Block (8-bit Output): This is where processed data is sent out to the external
environment. It could be to display data, activate devices, or send data over
communication channels.
3. Four 8-bit Internal Registers: These are small, fast storage locations inside the system
for holding 8-bit values temporarily. They are used to store intermediate data during
processing.
4. Control Logic: The control logic is responsible for managing the data flow between the
input, registers, and output. It decides which register receives data, and how the data is
processed and transferred.
5. Clock: Since we're dealing with digital electronics, a clock signal is typically used to
synchronize the operations of the system.
Design Explanation
1. Input Section:
 Input Bus: An 8-bit input bus brings data from an external source into the system.
 Multiplexer (MUX): A multiplexer could be used to select which register receives
the input data. The control logic will decide this based on the current operation. For
example, the input could be directed to R1 when the system is initializing, or to R2 if
intermediate processing is required.
2. Internal Registers (R1, R2, R3, R4):
 Each internal register is 8-bits wide. These registers are capable of storing 8-bit
values, and the control unit decides how data is transferred between them.
 The control logic enables one register to be loaded with data at a time. For example,
data can be moved from the input to R1, or the result of an operation from R1 could
be stored in R2.
3. Control Logic:
 Registers Selection: The control logic will include logic gates or a multiplexer to
select which register gets the input data, which register is used for processing, and
which register's content is sent to the output.
 Operations: Depending on the design, arithmetic or logical operations might be
performed using data from one or more registers. For instance, if the system performs
an addition, the control unit will fetch data from two registers, add them, and store the
result in a third register.
 Data Routing: The control logic may also handle the routing of data to the output
block. This is usually done using a multiplexer that selects which register’s content is
sent to the output.
4. Output Section:
 The output block is where the processed data is sent to an external device.
 A multiplexer is used to select which register’s data is output. The selected register’s
8-bit value is placed on the 8-bit output bus, making it available for external systems.
 EXPERIMENT – 7
OBJECTIVE – Design of an 8 bit ARITHMETIC LOGIC UNIT.

THEORY – The ALU is divided into two primary functional units: the Arithmetic Unit (for
mathematical operations like addition, subtraction, multiplication, and division) and the
Logical Unit (for bitwise operations like AND, OR, XOR, NOT).

This allows the ALU to perform a wide range of tasks, from basic calculations to decision-
making operations, which are fundamental for program execution and data manipulation in a
computer system.

An Arithmetic Logic Unit (ALU) is a fundamental component of a computer's central

processing unit (CPU). It is responsible for performing arithmetic and logical operations on
binary data. The ALU is a crucial part of the CPU's data path, allowing it to perform
calculations, decision-making, and data manipulation needed to execute instructions in a
computer program.

An 8-bit Arithmetic Logic Unit (ALU) is a digital circuit used in computer systems to
perform arithmetic and logic operations on 8-bit binary numbers. It is a critical component in
processors (CPUs), performing operations such as addition, subtraction, bitwise logical
operations, and comparison tasks.

The 8-bit ALU operates on two 8-bit inputs and produces an 8-bit output, with additional
control signals to determine which operation to perform.

The ALU typically consists of two main blocks: the Arithmetic Unit and the Logical Unit,
controlled by a Control Unit that selects which operation to perform.

 Arithmetic Unit: Performs arithmetic operations like addition, subtraction,

multiplication, and division.

 Logical Unit: Performs logical operations like AND, OR, XOR, NOT, and others.
 Control Unit: The control unit generates the control signals that tell the ALU which
operation to execute, based on the instruction from the CPU.
 EXPERIMENT – 8
OBJECTIVE – Design the data path of a computer from its register transfer language
description.

THEORY – To design the data path of a computer from its Register Transfer Language
(RTL) description in short, follow these steps:

1. Understand the RTL Description:

The Register Transfer Language describes the movement of data between registers, memory,
and functional units (like the ALU). For example:
 LD R1, M [1000]: Load the value from memory address 1000 into register R1.
 ADD R2, R1, R3: Add the contents of registers R1 and R3 and store the result in
register R2.
 MOV R4, R2: Move the contents of register R2 into register R4.
 ST R4, M[2000]: Store the value of register R4 into memory at address 2000.

2. Identify Key Components:

 Registers: R1, R2, R3, R4, and any other temporary registers (like the Program
Counter).
 ALU: Performs operations like ADD, SUB, etc.
 Memory: Stores instructions and data (e.g., data memory and instruction memory).
 Multiplexers: Used to select between multiple inputs for registers or the ALU.
 Control Unit: Decodes the instruction and generates the necessary control signals.

3. Define the Control Signals:

Control signals determine which operations will occur (e.g., ALU operation, register write
enable, memory read/write enable, etc.).

4. Design the Data Path:

For each instruction in the RTL:
 LD R1, M[1000]: Memory provides data to MUX, which writes it to R1.
 ADD R2, R1, R3: R1 and R3 are selected by MUXes and sent to the ALU. The ALU
result is written to R2.
 MOV R4, R2: The value in R2 is transferred to R4.
 ST R4, M[2000]: R4 is selected and written to memory at address 2000.

Key Steps:
1. Registers: Store values for later use.
2. ALU: Performs the required operation (e.g., ADD).
3. Memory: Provides or stores data.
4. Multiplexers: Select the appropriate data paths.
5. Control Unit: Generates the signals to manage the operations.
This is a high-level design, where specific control signals and more components (like flags,
data buses) would be added based on the exact RTL operations.
 EXPERIMENT – 9
OBJECTIVE – Design the control unit of a computer using either hardwiring or
microprogramming based on its register transfer language description.

THEORY – The Control Unit (CU) of a computer orchestrates the operations of the data
path components, guiding them based on the instructions. The design of the CU can be
approached in two ways: hardwiring or microprogramming. Let's briefly explain both
approaches based on an RTL description.

1. Hardwired Control Unit Design (Direct Control Signals)

In hardwiring, control signals are directly generated using combinational logic circuits (like
AND, OR, NOT gates) based on the opcode of the instruction.

Steps to Design:

1. Understand the RTL Instructions: These describe how data moves between
registers, memory, and functional units. For example:

o LD R1, M[1000]: Load the value from memory address 1000 into register R1.
o ADD R2, R1, R3: Add the contents of registers R1 and R3, store the result in
register R2.

2. Generate Control Signals: For each instruction, the control unit will generate
specific control signals, such as:

o ALU Control: Specifies the operation for the ALU (e.g., ADD, SUB).
o Register Write Enable: Signals when data should be written to a register.
o Memory Read/Write: Enables reading from or writing to memory.

3. Create the Control Logic: Use decoders to decode the instruction opcode and
generate the appropriate control signals. This can be done using:

o Instruction Decoder: Decodes the opcode and produces signals for specific
operations (like ALU operation, memory access).
o Control Signal Generation: For each type of instruction, different signals are
sent to the corresponding components (ALU, registers, memory).

Example:

For an instruction like ADD R2, R1, R3, the control unit needs to:

 Enable the ALU to perform an addition.

 Select R1 and R3 as inputs for the ALU.
 Write the result back into R2.
The control unit hardwires these steps directly.
2. Microprogramming Control Unit Design (Using Micro-Operations)

In microprogramming, the control unit uses a set of microinstructions stored in memory to

generate control signals. This approach is more flexible but slower compared to hardwiring.

Steps to Design:

 Define Micro-Operations: For each instruction, break it down into smaller steps
(micro-operations). For example:

o LD R1, M[1000] can be broken into:

 Fetch instruction from memory.
 Decode instruction.
 Load data from memory to register R1.

 Create a Micro-Program: A micro-program consists of a sequence of

microinstructions, each representing a specific step in the execution of an instruction.

 Use a Control Memory: The microprogram is stored in control memory. Each

microinstruction contains control signals that govern the ALU, registers, and memory
for one micro-operation.

 Generate Control Signals: The microcontroller fetches each microinstruction

sequentially to execute the micro-operations. The control unit provides the necessary
control signals by referring to the appropriate microinstruction in the control memory.

Example:

For ADD R2, R1, R3, the microprogram might consist of:

 Step 1: Load the instruction (LD R1, M[1000]).

 Step 2: Perform the ALU operation (ADD).
 Step 3: Write the result to R2.

Each of these steps is defined in a microinstruction and stored in the control memory.
 EXPERIMENT – 10
OBJECTIVE – Implement a simple instruction set computer with a control unit and a
data path.

THEORY – Implementing a simple Instruction Set Computer (ISC) with a Control Unit
(CU) and Data Path involves designing a system that can execute a set of basic instructions
like loading data, performing arithmetic operations, and storing data. Here's a brief
explanation of how to implement this system:

To design a simple Instruction Set Computer (ISC) with a Control Unit (CU) and a Data
Path:

1. Instruction Set: Define simple instructions like LD (Load), ADD (Add), MOV
(Move), and ST (Store).
2. Data Path: Includes components like:
o Registers (R1, R2, etc.)
o ALU (Arithmetic Logic Unit) for operations like addition
o Memory for data storage
o Multiplexers (MUX) to select data paths
o Program Counter (PC) to track instructions.
3. Control Unit:
o Decodes the instruction and generates control signals for the data path
components (e.g., register write, ALU operation, memory read/write).
4. Execution:
o The PC fetches the next instruction.
o The CU decodes it and activates the correct control signals.
o The Data Path performs the operations (e.g., load data to register, add values
in ALU, store results).

This setup allows the computer to execute basic instructions step by step.

Example:

For the instruction ADD R2, R1, R3:

 The control unit enables the ALU to perform the addition.

 MUXes select R1 and R3 as inputs for the ALU.
 The ALU adds R1 and R3, and the result is stored in R2.

This simple design allows the computer to execute basic instructions by manipulating data
and controlling the flow of information between the registers, ALU, and memory.