Large and Fast:

Exploiting Memory Hierarchy

NTUST ECE Undergraduate

Shanq-Jang Ruan (阮聖彰) Ph. D. @ Low Power System Lab.

Dept. Electronic and Computer Engineering at NTUST

Principle of Locality
• Programs access a small proportion of their address space at
any time
• Temporal locality
• Items accessed recently are likely to be accessed again soon
• e.g., instructions in a loop, induction variables
• Spatial locality
• Items near those accessed recently are likely to be accessed soon
• E.g., sequential instruction access, array data

1
Taking Advantage of Locality
• Memory hierarchy
• Store everything on disk
• Copy recently accessed (and nearby) items from disk to smaller
DRAM memory
• Main memory
• Copy more recently accessed (and nearby) items from DRAM
to smaller SRAM memory
• Cache memory attached to CPU

2
Memory Hierarchy Levels
• Block (aka line): unit of copying
• May be multiple words
• If accessed data is present in
upper level
• Hit: access satisfied by upper level
• Hit ratio: hits/accesses
• If accessed data is absent
• Miss: block copied from lower level
• Time taken: miss penalty
• Miss ratio: misses/accesses
= 1 – hit ratio
• Then accessed data supplied from
upper level

3
Memory Technology
• Static RAM (SRAM)
• 0.5ns – 2.5ns, $2000 – $5000 per GB
• Dynamic RAM (DRAM)
• 50ns – 70ns, $20 – $75 per GB
• Magnetic disk
• 5ms – 20ms, $0.20 – $2 per GB
• Ideal memory
• Access time of SRAM
• Capacity and cost/GB of disk

4
DRAM Technology
• Data stored as a charge in a capacitor
• Single transistor used to access the charge
• Must periodically be refreshed
• Read contents and write back
• Performed on a DRAM “row”

5
DRAM Technology
• 何謂 MT/s？
• MT/s 是每秒百萬 (mega) 次傳輸的縮寫，是一種更準確、用來計算並表
示 DDR SDRAM 記憶體資料傳輸速率 (速度) 的標準。MT/s 是每秒百萬
(mega) 次傳輸的縮寫。
• SDRAM
• 時脈：100MHz
傳輸速率：100MT/s
頻寬：800MB/s
• DDR SDRAM
• 時脈：100MHz
傳輸速率：200MT/s
頻寬：1600MB/s
[Link]
6
Advanced DRAM
Organization
• Bits in a DRAM are organized as
a rectangular array
• DRAM accesses an entire row
• Burst mode: supply successive
words from a row with reduced
latency
• Double data rate (DDR) DRAM
• Transfer on rising and falling clock
edges
• Quad data rate (QDR) DRAM
• Separate DDR inputs and outputs

7
Advanced DRAM Organization
• DDR4

8
DRAM Generations
Year Capacity $/GB
1980 64 Kibibit $6,480,000
1983 256 Kibibit $1,980,000
1985 1 Mebibit $720,000
1989 4 Mebibit $128,000
1992 16 Mebibit $30,000
1996 64 Mebibit $9,000
1998 128 Mebibit $900
2000 256 Mebibit $840
2004 512 Mebibit $150
2007 1 Gibibit $40
2010 2 Gibibit $13
2012 4 Gibibit $5
2015 8 Gibibit $7
2018 16 Gibibit $6

9
DRAM Performance Factors
• Row buffer
• Allows several words to be read and refreshed in parallel
• Synchronous DRAM
• Allows for consecutive accesses in bursts without needing to send
each address
• Improves bandwidth
• DRAM banking
• Allows simultaneous access to multiple DRAMs
• Improves bandwidth

10
Main Memory Supporting Caches
• Use DRAMs for main memory
• Fixed width (e.g., 1 word)
• Connected by fixed-width clocked bus
• Bus clock is typically slower than CPU clock
• Example cache block read
• 1 bus cycle for address transfer
• 15 bus cycles per DRAM access
• 1 bus cycle per data transfer
• For 4-word block, 1-word-wide DRAM
• Miss penalty = 1 + 4×15 + 4×1 = 65 bus cycles
• Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle

11
Increasing Memory Bandwidth
• 4-word wide memory • 4-bank interleaved memory
• Miss penalty = 1 + 15 + 1 = 17 bus • Miss penalty = 1 + 15 + 4×1 = 20 bus
cycles cycles
• Bandwidth = 16 bytes / 17 cycles = • Bandwidth = 16 bytes / 20 cycles =
0.94 B/cycle 0.8 B/cycle

12
Flash Storage
• Nonvolatile semiconductor storage
• 100× – 1000× faster than disk
• Smaller, lower power, more robust
• But more $/GB (between disk and DRAM)

13
Flash Types
• NOR flash: bit cell like a NOR gate
• Random read/write access
• Used for instruction memory in embedded systems (e.g. BIOS)
• NAND flash: bit cell like a NAND gate
• Denser (bits/area), but block-at-a-time access
• Cheaper per GB
• Used for USB keys, media storage, …
• Flash bits wears out after 1000’s of accesses
• Not suitable for direct RAM or disk replacement
• Wear leveling: remap data to less used blocks

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Disk Storage

15
Disk Sectors and Access
• Each sector records
• Sector ID
• Data (512 bytes, 4096 bytes proposed)
• Error correcting code (ECC)
• Used to hide defects and recording errors
• Synchronization fields and gaps
• Access to a sector involves
• Queuing delay if other accesses are pending
• Seek: move the heads
• Rotational latency
• Data transfer
• Controller overhead
16
Disk Access Example
• Given
• 512B sector, 15,000rpm, 4ms average seek time, 100MB/s transfer
rate, 0.2ms controller overhead, idle disk
• Average read time
• 4ms seek time
+ ½ / (15,000/60) = 2ms rotational latency
+ 512 / 100MB/s = 0.005ms transfer time
+ 0.2ms controller delay
= 6.2ms
• If the actual average seek time is 1ms
• Average read time = 3.2ms

17
Disk Performance Issues
• Manufacturers quote average seek time
• Based on all possible seeks
• Locality and OS scheduling lead to smaller actual average seek times
• Smart disk controller allocates physical sectors on disk
• Present logical sector interface to host
• SCSI, ATA, SATA
• Disk drives include caches
• Prefetch sectors in anticipation of access
• Avoid seek and rotational delay

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Cache Memory
• Cache memory
• The level of the memory hierarchy closest to the CPU
• Given accesses X1, …, Xn–1, Xn

• How do we know if the data is

present?
• Where do we look?

19
Direct Mapped Cache
• Location determined by address
• Direct mapped: only one choice
• (Block address) modulo (#Blocks in cache)

• #Blocks is a power
of 2
• Use low-order
address bits
20
Tags and Valid Bits
• How do we know which particular block is stored in a cache
location?
• Store block address as well as the data
• Actually, only need the high-order bits
• Called the tag
• What if there is no data in a location?
• Valid bit: 1 = present, 0 = not present
• Initially 0

21
Cache Example
• 8 blocks, 1 word/block, direct mapped
• Initial state, access addresses 22, 26, 22, 26, 16, 3, 16, 18
Index V Tag Data
000 N
001 N
010 N
011 N
100 N
101 N
110 N
111 N

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Cache Example
Word addr Binary addr Hit/miss Cache block
22 10 110 Miss 110

Index V Tag Data

000 N
001 N
010 N
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N

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Cache Example
Word addr Binary addr Hit/miss Cache block
26 11 010 Miss 010

Index V Tag Data

000 N
001 N
010 Y 11 Mem[11010]
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N

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Cache Example
Word addr Binary addr Hit/miss Cache block
22 10 110 Hit 110
26 11 010 Hit 010

Index V Tag Data

000 N
001 N
010 Y 11 Mem[11010]
011 N
100 N
101 N
110 Y 10 Mem[10110]
111 N
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Cache Example
Word addr Binary addr Hit/miss Cache block
16 10 000 Miss 000
3 00 011 Miss 011
16 10 000 Hit 000

Index V Tag Data

000 Y 10 Mem[10000]
001 N
010 Y 11 Mem[11010]
011 Y 00 Mem[00011]
100 N
101 N
110 Y 10 Mem[10110]
111 N
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Cache Example
Word addr Binary addr Hit/miss Cache block
18 10 010 Miss 010

Index V Tag Data

000 Y 10 Mem[10000]
001 N
010 Y 10 Mem[10010]
011 Y 00 Mem[00011]
100 N
101 N
110 Y 10 Mem[10110]
111 N
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Address Subdivision

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Example: Larger Block Size
• 64 blocks, 16 bytes/block
• To what block number does address 1200 map?
• Block address = 1200/16 = 75
• Block number = 75 modulo 64 = 11

63 10 9 4 3 0
Tag Index Offset
22 bits 6 bits 4 bits

29
Block Size Considerations
• Larger blocks should reduce miss rate
• Due to spatial locality
• But in a fixed-sized cache
• Larger blocks  fewer of them
• More competition  increased the miss rate
• Larger blocks  pollution
• Larger miss penalty
• Can override the benefit of reduced miss rate
• Early restart and critical-word-first can help

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Cache Misses
• On cache hit, CPU proceeds normally
• On cache miss
• Stall the CPU pipeline
• Fetch block from next level of hierarchy
• Instruction cache miss
• Restart instruction fetch
• Data cache miss
• Complete data access

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Write-Through
• On data-write hit, could just update the block in cache
• But then cache and memory would be inconsistent
• Write through: also update memory
• But makes writes take longer
• e.g., if base CPI = 1, 10% of instructions are stores, write to memory
takes 100 cycles
• Effective CPI = 1 + 0.1×100 = 11
• Solution: write buffer
• Holds data waiting to be written to memory
• CPU continues immediately
• Only stalls on write if write buffer is already full
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Write-Back
• Alternative: On data-write hit, just update the block in cache
• Keep track of whether each block is dirty
• When a dirty block is replaced
• Write it back to memory
• Can use a write buffer to allow replacing block to be read first

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Write Allocation
• What should happen on a write miss?
• Alternatives for write-through
• Allocate on miss: fetch the block
• Write around: don’t fetch the block
• Since programs often write a whole block before reading it (e.g., initialization)
• For write-back
• Usually fetch the block

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Example: Intrinsity FastMATH
• Embedded MIPS processor
• 12-stage pipeline
• Instruction and data access on each cycle
• Split cache: separate I-cache and D-cache
• Each 16KB: 256 blocks × 16 words/block
• D-cache: write-through or write-back
• SPEC2000 miss rates
• I-cache: 0.4%
• D-cache: 11.4%
• Weighted average: 3.2%

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Example: Intrinsity FastMATH

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Main Memory Supporting Caches
• Use DRAMs for main memory
• Fixed width (e.g., 1 word)
• Connected by fixed-width clocked bus
• Bus clock is typically slower than CPU clock
• Example cache block read
• 1 bus cycle for address transfer
• 15 bus cycles per DRAM access
• 1 bus cycle per data transfer
• For 4-word block, 1-word-wide DRAM
• Miss penalty = 1 + 4×15 + 4×1 = 65 bus cycles
• Bandwidth = 16 bytes / 65 cycles = 0.25 B/cycle

37
Measuring Cache Performance
• Components of CPU time
• Program execution cycles
• Includes cache hit time
• Memory stall cycles
• Mainly from cache misses
• With simplifying assumptions:
Memory stall cycles
Memory accesses
=  Miss rate  Miss penalty
Program
Instructions Misses
=   Miss penalty
Program Instruction
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Cache Performance Example
• Given
• I-cache miss rate = 2%
• D-cache miss rate = 4%
• Miss penalty = 100 cycles
• Base CPI (ideal cache) = 2
• Load & stores are 36% of instructions
• Miss cycles per instruction
• I-cache: 0.02 × 100 = 2
• D-cache: 0.36 × 0.04 × 100 = 1.44
• Actual CPI = 2 + 2 + 1.44 = 5.44
• Ideal CPU is 5.44/2 =2.72 times faster

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Average Access Time
• Hit time is also important for performance
• Average memory access time (AMAT)
• AMAT = Hit time + Miss rate × Miss penalty
• Example
• CPU with 1ns clock, hit time = 1 cycle, miss penalty = 20 cycles, I-
cache miss rate = 5%
• AMAT = 1 + 0.05 × 20 = 2ns
• 2 cycles per instruction

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Performance Summary
• When CPU performance increased
• Miss penalty becomes more significant
• Decreasing base CPI
• Greater proportion of time spent on memory stalls
• Increasing clock rate
• Memory stalls account for more CPU cycles
• Can’t neglect cache behavior when evaluating system
performance

41
Associative Caches
• Fully associative
• Allow a given block to go in any cache entry
• Requires all entries to be searched at once
• Comparator per entry (expensive)
• n-way set associative
• Each set contains n entries
• Block number determines which set
• (Block number) modulo (#Sets in cache)
• Search all entries in a given set at once
• n comparators (less expensive)

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Associative Cache Example

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Spectrum of Associativity
• For a cache with 8 entries

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Associativity Example
• Compare 4-block caches
• Direct mapped, 2-way set associative,
fully associative
• Block access sequence: 0, 8, 0, 6, 8
• Direct mapped
Block Cache Hit/miss Cache content after access
address index 0 1 2 3
0 0 miss Mem[0]
8 0 miss Mem[8]
0 0 miss Mem[0]
6 2 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]

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Associativity Example
• 2-way set associative
Block Cache Hit/miss Cache content after access
address index Set 0 Set 1
0 0 miss Mem[0]
8 0 miss Mem[0] Mem[8]
0 0 hit Mem[0] Mem[8]
6 0 miss Mem[0] Mem[6]
8 0 miss Mem[8] Mem[6]

• Fully associative
Block Hit/miss Cache content after access
address
0 miss Mem[0]
8 miss Mem[0] Mem[8]
0 hit Mem[0] Mem[8]
6 miss Mem[0] Mem[8] Mem[6]
8 hit Mem[0] Mem[8] Mem[6]
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How Much Associativity
• Increased associativity decreases miss rate
• But with diminishing returns
• Simulation of a system with 64KB
D-cache, 16-word blocks, SPEC2000
• 1-way: 10.3%
• 2-way: 8.6%
• 4-way: 8.3%
• 8-way: 8.1%

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Set Associative Cache Organization

48
Replacement Policy
• Direct mapped: no choice
• Set associative
• Prefer non-valid entry, if there is one
• Otherwise, choose among entries in the set
• Least-recently used (LRU)
• Choose the one unused for the longest time
• Simple for 2-way, manageable for 4-way, too hard beyond that
• Random
• Gives approximately the same performance as LRU for high
associativity

49
Multilevel Caches
• Primary cache attached to CPU
• Small, but fast
• Level-2 cache services misses from primary cache
• Larger, slower, but still faster than main memory
• Main memory services L-2 cache misses
• Some high-end systems include L-3 cache

50
Multilevel Cache Example
• Given
• CPU base CPI = 1, clock rate = 4GHz
• Miss rate/instruction = 2%
• Main memory access time = 100ns
• With just primary cache
• Miss penalty = 100ns/0.25ns = 400 cycles
• Effective CPI = 1 + 0.02 × 400 = 9

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Example (cont.)
• Now add L-2 cache
• Access time = 5ns
• Global miss rate to main memory = 0.5%
• Primary miss with L-2 hit
• Penalty = 5ns/0.25ns = 20 cycles
• Primary miss with L-2 miss
• Extra penalty = 400 cycles
• CPI = 1 + 0.02 × 20 + 0.005 × 400 = 3.4
• Performance ratio = 9/3.4 = 2.6

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Multilevel Cache Considerations
• Primary cache
• Focus on minimal hit time
• L-2 cache
• Focus on low miss rate to avoid main memory access
• Hit time has less overall impact
• Results
• L-1 cache usually smaller than a single cache
• L-1 block size smaller than L-2 block size

53
Interactions with Advanced CPUs
• Out-of-order CPUs can execute instructions during cache
miss
• Pending store stays in load/store unit
• Dependent instructions wait in reservation stations
• Independent instructions continue
• Effect of miss depends on program data flow
• Much harder to analyse
• Use system simulation

54
Interactions with
Software
• Misses depend on
memory access
patterns
• Algorithm behavior
• Compiler optimization
for memory access

55
Software Optimization via Blocking
• Goal: maximize accesses to data before it is replaced
• Consider inner loops of DGEMM:
(Double-precision General Matrix Multiply)

for (int j = 0; j < n; ++j)

{
double cij = C[i+j*n]; /*cij = c[i][j]*/
for( int k = 0; k < n; k++ )
cij += A[i+k*n] * B[k+j*n]; /*cij += A[i][k]*B[k][j]*/
C[i+j*n] = cij;
}

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DGEMM Access Pattern
• C, A, and B arrays (N=6 and i=1)
older accesses
cij += A[i][k]*B[k][j]
new accesses

C A B
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Cache Blocked DGEMM
1 #define BLOCKSIZE 32
2 void do_block (int n, int si, int sj, int sk, double *A, double
3 *B, double *C)
4 {
5 for (int i = si; i < si+BLOCKSIZE; ++i)
6 for (int j = sj; j < sj+BLOCKSIZE; ++j)
7 {
8 double cij = C[i+j*n]; /* cij = C[i][j] */
9 for( int k = sk; k < sk+BLOCKSIZE; k++ )
10 cij += A[i+k*n] * B[k+j*n]; /* cij+=A[i][k]*B[k][j] */
11 C[i+j*n] = cij; /* C[i][j] = cij */
12 }
13 }
14 void dgemm (int n, double* A, double* B, double* C)
15 {
16 for ( int sj = 0; sj < n; sj += BLOCKSIZE )
17 for ( int si = 0; si < n; si += BLOCKSIZE )
18 for ( int sk = 0; sk < n; sk += BLOCKSIZE )
19 do_block(n, si, sj, sk, A, B, C);
20 }

58
Blocked DGEMM Access Pattern

59
Virtual Memory
• Use main memory as a “cache” for secondary (disk) storage
• Managed jointly by CPU hardware and the operating system (OS)
• Programs share main memory
• Each gets a private virtual address space holding its frequently used
code and data
• Protected from other programs
• CPU and OS translate virtual addresses to physical addresses
• VM “block” is called a page
• VM translation “miss” is called a page fault

60
Address Translation
• Fixed-size pages (e.g., 4K)

61
Page Fault Penalty
• On page fault, the page must be fetched from disk
• Takes millions of clock cycles
• Handled by OS code
• Try to minimize page fault rate
• Fully associative placement
• Smart replacement algorithms

62
Page Tables
• Stores placement information
• Array of page table entries, indexed by virtual page number
• Page table register in CPU points to page table in physical memory
• If page is present in memory
• PTE stores the physical page number
• Plus other status bits (referenced, dirty, …)
• If page is not present
• PTE can refer to location in swap space on disk

63
Translation Using a Page Table

64
Mapping Pages to Storage

65
Replacement and Writes
• To reduce page fault rate, prefer least-recently-used (LRU)
replacement
• Reference bit (aka use bit) in PTE set to 1 on access to the page
• Periodically cleared to 0 by OS
• A page with reference bit = 0 has not been used recently
• Disk writes take millions of cycles
• Block at once, not individual locations
• Write-through is impractical
• Use write-back
• Dirty bit in PTE set when page is written

66
Fast Translation Using a TLB
• Address translation would appear to require extra memory
references
• One to access the PTE
• Then the actual memory access
• But access to page tables has good locality
• So use a fast cache of PTEs within the CPU
• Called a Translation Look-aside Buffer (TLB)
• Typical: 16–512 PTEs, 0.5–1 cycle for hit, 10–100 cycles for miss,
0.01%–1% miss rate
• Misses could be handled by hardware or software

67
Fast Translation Using a TLB

68
TLB Misses
• If page is in memory
• Load the PTE from memory and retry
• Could be handled in hardware
• Can get complex for more complicated page table structures
• Or in software
• Raise a special exception, with optimized handler
• If page is not in memory (page fault)
• OS handles fetching the page and updating the page table
• Then restart the faulting instruction

69
TLB Miss Handler
• TLB miss indicates
• Page present, but PTE not in TLB
• Page not preset
• Must recognize TLB miss before destination register overwritten
• Raise exception
• Handler copies PTE from memory to TLB
• Then restarts instruction
• If page not present, page fault will occur

70
Page Fault Handler
• Use faulting virtual address to find PTE
• Locate page on disk
• Choose page to replace
• If dirty, write to disk first
• Read page into memory and update page table
• Make process runnable again
• Restart from faulting instruction

71
TLB and Cache Interaction
• If cache tag uses
physical address
• Need to translate before
cache lookup
• Alternative: use virtual
address tag
• Complications due to
aliasing
• Different virtual
addresses for shared
physical address

72
Processing in TLB + Cache Virtual address

TLB access
A reference may miss
in all 3 components:
TLB, VM, cache
TLB miss No Yes
TLB hit?
exception Physical address

No Yes
Write?

Try to read data

from cache No Write access Yes
bit on?

Write protection
exception Write data into cache,
No Yes update the tag, and put
Cache miss stall Cache hit? the data and the address
into the write buffer

Deliver data
73
to the CPU
TLB Event Combinations
TLB Page Cache Possible? Under what circumstances?
Table
Hit Hit Hit Yes – what we want!
Hit Hit Miss Yes – although the page table is not
checked if the TLB hits
Miss Hit Hit Yes – TLB miss, PA in page table
Miss Hit Miss Yes – TLB miss, PA in page table, but data
not in cache
Miss Miss Miss Yes – page fault
Hit Miss Miss/ Impossible – TLB translation not possible if
Hit page is not present in memory
Miss Miss Hit Impossible – data not allowed in cache if
page is not in memory
74
Memory Protection
• Different tasks can share parts of their virtual address spaces
• But need to protect against errant access
• Requires OS assistance
• Hardware support for OS protection
• Privileged supervisor mode (aka kernel mode)
• Privileged instructions
• Page tables and other state information only accessible in supervisor
mode
• System call exception (e.g., syscall in MIPS)

75
The Memory Hierarchy
The BIG Picture
• Common principles apply at all levels of the memory hierarchy
• Based on notions of caching
• At each level in the hierarchy
• Block placement
• Finding a block
• Replacement on a miss
• Write policy

76
Block Placement
• Determined by associativity
• Direct mapped
• One choice for placement
• n-way set associative
• n choices within a set
• Fully associative
• Any location
• Higher associativity reduces miss rate
• Increases complexity, cost, and access time

77
Finding a Block
Associativity Location method Tag comparisons
Direct mapped Index 1
n-way set Set index, then search n
associative entries within the set
Fully associative Search all entries #entries
Full lookup table 0

• Hardware caches
• Reduce comparisons to reduce cost
• Virtual memory
• Full table lookup makes full associativity feasible
• Benefit in reduced miss rate
78
Replacement
• Choice of entry to replace on a miss
• Least recently used (LRU)
• Complex and costly hardware for high associativity
• Random
• Close to LRU, easier to implement
• Virtual memory
• LRU approximation with hardware support

79
Write Policy
• Write-through
• Update both upper and lower levels
• Simplifies replacement, but may require write buffer
• Write-back
• Update upper level only
• Update the lower level when a block is replaced
• Need to keep more state
• Virtual memory
• Only write-back is feasible, given disk write latency

80
Sources of Misses
• Compulsory misses (aka cold start misses)
• First access to a block
• Capacity misses
• Due to finite cache size
• A replaced block is later accessed again
• Conflict misses (aka collision misses)
• In a non-fully associative cache
• Due to competition for entries in a set
• Would not occur in a fully associative cache of the same total size

81
Cache Design Trade-offs
Design change Effect on miss rate Negative performance
effect
Increase cache size Decrease capacity May increase access
misses time
Increase Decrease conflict May increase access
associativity misses time
Increase block size Decrease compulsory Increases miss
misses penalty. For very large
block size, may
increase miss rate
due to pollution.

82
Cache Control
• Example cache characteristics
• Direct-mapped, write-back, write allocate
• Block size: 4 words (16 bytes)
• Cache size: 16 KB (1024 blocks)
• 32-bit byte addresses
• Valid bit and dirty bit per block
• Blocking cache
• CPU waits until access is complete

31 10 9 4 3 0
Tag Index Offset
18 bits 10 bits 4 bits

83
Interface Signals

Read/Write Read/Write
Valid Valid
32 32
Address Address
32 Cache 128 Memory
CPU Write Data Write Data
32 128
Read Data Read Data
Ready Ready

Multiple cycles
per access

84
 Finite State Machines
• Use an FSM to sequence control steps
• Set of states, transition on each clock edge
• State values are binary encoded
• Current state stored in a register
• Next state
= fn (current state,
current inputs)
• Control output signals
= fo (current state)

85
Cache Controller FSM
Could
partition into
separate
states to
reduce clock
cycle time

86
Cache Coherence Problem
• Suppose two CPU cores share a physical address space
• Write-through caches

Time Event CPU A’s CPU B’s Memory

step cache cache
0 0
1 CPU A reads X 0 0
2 CPU B reads X 0 0 0

3 CPU A writes 1 to X 1 0 1

87
Coherence Defined
• Informally: Reads return most recently written value
• Formally:
• P writes X; P reads X (no intervening writes)
 read returns written value
• P1 writes X; P2 reads X (sufficiently later)
 read returns written value
• c.f. CPU B reading X after step 3 in example
• P1 writes X, P2 writes X
 all processors see writes in the same order
• End up with the same final value for X

88
Cache Coherence Protocols
• Operations performed by caches in multiprocessors to ensure
coherence
• Migration of data to local caches
• Reduces bandwidth for shared memory
• Replication of read-shared data
• Reduces contention for access
• Snooping protocols
• Each cache monitors bus reads/writes
• Directory-based protocols
• Caches and memory record sharing status of blocks in a directory

89
Invalidating Snooping Protocols
• Cache gets exclusive access to a block when it is to be written
• Broadcasts an invalidate message on the bus
• Subsequent read in another cache misses
• Owning cache supplies updated value

CPU activity Bus activity CPU A’s CPU B’s Memory

cache cache
0
CPU A reads X Cache miss for X 0 0
CPU B reads X Cache miss for X 0 0 0
CPU A writes 1 to X Invalidate for X 1 0
CPU B read X Cache miss for X 1 1 1
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Memory Consistency
• When are writes seen by other processors
• “Seen” means a read returns the written value
• Can’t be instantaneously
• Assumptions
• A write completes only when all processors have seen it
• A processor does not reorder writes with other accesses
• Consequence
• P writes X then writes Y
 all processors that see new Y also see new X
• Processors can reorder reads, but not writes

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Multilevel On-Chip Caches

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2-Level TLB Organization

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Supporting Multiple Issue
• Both have multi-banked caches that allow multiple accesses per
cycle assuming no bank conflicts
• Other optimizations
• Return requested word first
• Non-blocking cache
• Hit under miss
• Miss under miss
• Data prefetching

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RISC-V System Instructions
Type Mnemonic Name
Mem ordering fence.i Instruction fence
fence Fence
[Link] Address translation fence
CSR access csrrwi CSR read/write immediate
csrrsi CSR read/set immediate
csrrci CSR read/clear immediate
csrrw CSR read/write
csrrs CSR read/set
csrrc CSR read/clear
System ecall Environment call
ebreak Environment breakpoint
sret Supervisor exception return
wfi Wait for interrupt
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DGEMM
• Combine cache blocking and subword parallelism

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Pitfalls
• Byte vs. word addressing
• Example: 32-byte direct-mapped cache,
4-byte blocks
• Byte 36 maps to block 1
• Word 36 maps to block 4
• Ignoring memory system effects when writing or generating
code
• Example: iterating over rows vs. columns of arrays
• Large strides result in poor locality

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Pitfalls
• In multiprocessor with shared L2 or L3 cache
• Less associativity than cores results in conflict misses
• More cores  need to increase associativity
• Using AMAT to evaluate performance of out-of-order processors
• Ignores effect of non-blocked accesses
• Instead, evaluate performance by simulation
• Extending address range using segments
• E.g., Intel 80286
• But a segment is not always big enough
• Makes address arithmetic complicated

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Concluding Remarks
• Fast memories are small, large memories are slow
• We really want fast, large memories 
• Caching gives this illusion ☺
• Principle of locality
• Programs use a small part of their memory space frequently
• Memory hierarchy
• L1 cache  L2 cache  …  DRAM memory
 disk
• Memory system design is critical for multiprocessors

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Thank you for listening!

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