Discrete Control 4’th Year

Chapter Seven:

Realization of Digital Controller

7.1 Preface

Realization of digital controllers and digital filters may involve either

software or hardware or both. In general, realization of a pulse transfer
function means determining the physical layout for the appropriate
combination of arithmetic and storage options.
In a software realization we obtain computer programs for the digital
computer involved. In a hardware realization we build a special-purpose
processor using such circuitry as digital ladders, multipliers and delay
elements (shift registers, with a sampling period T as a unit time delay.
This chapter deals with block diagram realization of digital
filters/controllers using delay elements, adders and multipliers. Such block
diagram realizations can be used as a basis for a software or hardware
design. In fact, once the block diagram realization is completed, the physical
realization in hardware or software is straight-forward.
In what follows we shall deal with the digital filters that are used for filtering
and control purposes. The general form of the pulse transfer function
between the output Y(z) and input X(z) is given by:

𝑌(𝑧) 𝑏0 +𝑏1 𝑧 −1 +𝑏2 𝑧 −2 +⋯+𝑏𝑚 𝑧 −𝑚

𝐺 (𝑧) = = 𝑛 ≥ 𝑚 … . (7.1)
𝑋(𝑧) 1+𝑎1 𝑧 −1 +𝑎2 𝑧 −2 +⋯+𝑎𝑛 𝑧 −𝑛

Where the ai’s and bi’s are real coefficients (some of them may be zero).
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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

Note that the z-transfer function of z-1 represents a one-time delay unit.

Figure 7.1: Z-transfer function of a one-time delay unit.

7.2 Direct Programing

In direct programming, coefficients ai and bi (which ae real quantities)

appear as multipliers in the block diagram realization.
Consider the digital filter given by equation (7.1). Notice that the pulse
transfer function has n poles and m zeros.
Rearrange the equation (7.1) as:
Y(z)= - a1 z -1 Y(z) - a2 z -2 Y(z)- … - an z -n Y(z) + b0 X(z)

+ b1 z -1 X(z)+ … + bm z -m X(z)

Figure (7.2) shows a block diagram realization of the filter.

Figure (7.2): Block diagram realization of a filter showing direct programming.

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

The type of realization here is called direct programming. That means, we

realize the numerator and denominator of the pulse transfer function using
separate sets of delay elements. The numerator uses a set of m delay
elements and the denominator uses a different set of n delay elements.
Thus, the total number of delay elements used in direct programming is
m + n.

7.3 Standard Programing

The standard programming method uses a minimum possible number of

delay element. The number of delay elements used to realize the pulse
transfer function given by equation (7.1) can be reduced from n + m to n
(where n ≥ m) by rearranging the block diagram as follow.
First, rewrite the pulse transfer function Y(z)/X(z) given by equation (7.1)
as follows:
𝑌(𝑧) 𝑌(𝑧) 𝐻(𝑧)
=
𝑋(𝑧) 𝐻(𝑧) 𝑋(𝑧)
1
= (𝑏0 + 𝑏1 𝑧 −1 + 𝑏2 𝑧 −2 + ⋯ + 𝑏𝑚 𝑧 −𝑚 )
1 + 𝑎1 𝑧 −1 + 𝑎2 𝑧 −2 + ⋯ + 𝑎𝑛 𝑧 −𝑛

Where
𝑌(𝑧)
= 𝑏0 + 𝑏1 𝑧 −1 + 𝑏2 𝑧 −2 + ⋯ + 𝑏𝑚 𝑧 −𝑚 (7.2)
𝐻(𝑧)

And
𝐻 (𝑧 ) 1
= 1+𝑎 −1 −2 −𝑛 (7.3)
𝑋 (𝑧 ) 1 𝑧 +𝑎2 𝑧 +⋯+𝑎𝑛 𝑧

Then, draw block diagrams for the systems given by equations (7.2) and
(7.3), respectively.

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

To draw the block diagrams, we may rewrite equation (7.2) as:

𝑌 (𝑧) = 𝑏0 𝐻(𝑧) + 𝑏1 𝑧 −1 𝐻(𝑧) + 𝑏2 𝑧 −2 𝐻(𝑧) + ⋯ + 𝑏𝑚 𝑧 −𝑚 𝐻(𝑧) …(7.4)

And equation (7.3) as:

𝐻 (𝑧) = 𝑋(𝑧) − 𝑎1 𝑧 −1 𝐻(𝑧) − 𝑎2 𝑧 −2 𝐻(𝑧) − ⋯ − 𝑎𝑛 𝑧 −𝑛 𝐻(𝑧) …(7.5)

Then, from equation (7.4) we obtain figure (7.3).

Figure (7.3): Block diagram realization of equation (7.4).

And, from equation (7.5) we obtain figure (7.4).

Figure (7.4): Block diagram realization of equation (7.5).

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

The combination of these two block diagrams gives the block diagram for
the digital filter G(z), as shown in figure (7.5).

Figure (7.5): Block diagram realization of the digital filter given by equation (7.1) by standard
programming.

The block diagram realization as presented here is based on the standard

programming. Notice that we use only n delay elements. The coefficients
a1, a2, …, an appear as feedback elements, and the coefficients b0, b1, …, bm
appear as feedforward elements.

The error due to quantization of the coefficients ai and bi of the pulse

transfer function.
This error may become large as the order of the pulse transfer function is
increased. That is, in higher-order digital filter in direct structure, small
errors in the coefficients ai and bi cause large errors in the locations of the
poles and zeros of the filter.
This error may be reduced by decomposing a high order pulse transfer
function into a combination of lower-order pulse transfer functions. In this
way, the system may be made less sensitive to coefficient inaccuracies.
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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

7.4 Series Programing

The first approach used to avoid the sensitivity problem is to implement

the pulse transfer function G(z) as a series connection of first-order and/or
second-order pulse transfer functions. If G(z) can be written as a product of
pulse transfer functions
G(z) = G1(z)G2(z) … Gp(z)

Then the digital filter for G(z) may be given as a series connection of the
component digital filters G1(z), G2(z), …, Gp(z), as shown in figure (7.6).

Figure (7.6): Digital filter G(z) decomposed into a series connection of G1(z), G2(z), …, Gp(z).

In most cases Gi(z) (i = 1, 2, …, P) are chosen to be either first- or second-

order functions. If the poles and zeros of G(z) are known, G1(z), G2(z), …,
Gp(z) can be obtained by grouping a pair of conjugate complex poles and
pair of conjugate complex zeros to produce a second-order function or by
grouping real poles and real zeros to produce either first-or second-order
functions. It is possible to group two real zeros with a pair conjugate
complex poles, or vice versa. The grouping is, in a sense, arbitrary. It is
desirable to group several different ways to see which is best with respect to
the number of arithmetic operations required, the range of coefficients, and
so forth.
To summarize, G(z) may be decomposed as follows:
G(z) = G1(z)G2(z) … Gp(z)

𝑗 𝑝
−1
1 + 𝑏𝑖 𝑧 1 + 𝑒𝑖 𝑧 −1 + 𝑓𝑖 𝑧 −2
=∏ ∏
1 + 𝑎𝑖 𝑧 −1 1 + 𝑐𝑖 𝑧 −1 + 𝑑𝑖 𝑧 −2
𝑖=1 𝑖=𝑗+1

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

The block diagram for

𝑌(𝑧) 1 + 𝑏𝑖 𝑧 −1
= … (7.6)
𝑋(𝑧) 1 + 𝑎𝑖 𝑧 −1
And that for
𝑌(𝑧) 1 + 𝑒𝑖 𝑧 −1 + 𝑓𝑖 𝑧 −2
= … (7.7)
𝑋(𝑧) 1 + 𝑐𝑖 𝑧 −1 + 𝑑𝑖 𝑧 −2

Are shown in figures (7.7 a) and (7.7 b), respectively. The block diagram
for the digital filter G(z) is a series connection of p component digital filters
such as shown in figures (7.7 a) and (7.7 b).

(a)

(b)

Figure (7.7): (a) Block diagram representation of equation (7.6); (b) Block diagram
representation of equation (7.7).

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

7.5 Parallel Programing

The second approach to avoiding the coefficient sensitivity problem is to

expand the pulse transfer function G(z) into partial fraction.
If G(z) is expanded as a sum of A, G1(z), G2(z), …, Gq(z) or so that
G(z) = A + G1(z) + G2(z) + …+ Gq(z)
Where A is simply a constant, then the block diagram for the digital filter
G(z) can be obtained as a parallel connection of q + 1 digital filters, as shown
in figure below.

Figure (7.8): Digital filter G(z) decomposed as a parallel connection.

Because of the presence of the constant term A, the first- and second-order
functions can be chosen in simpler forms. That is, G(z) may be expressed as
G(z) = A + G1(z) + G2(z) + …+ Gq(z)
𝑗 𝑞

= 𝐴 + ∑ 𝐺𝑖 (𝑧) + ∑ 𝐺𝑖 (𝑧)
𝑖=1 𝑖=𝑗+1

𝑗 𝑞
𝑏𝑖 𝑒𝑖 + 𝑓𝑖 𝑧 −1
=𝐴+∑ + ∑
1 + 𝑎𝑖 𝑧 −1 1 + 𝑐𝑖 𝑧 −1 + 𝑑𝑖 𝑧 −2
𝑖=1 𝑖=𝑗+1

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Computer Engineering Department Dr. Loai Ali Talib
Discrete Control 4’th Year

The block diagram for

𝑌(𝑧) 𝑏𝑖
= … (7.8)
𝑋(𝑧) 1 + 𝑎𝑖 𝑧 −1
And that for
𝑌(𝑧) 𝑒𝑖 + 𝑓𝑖 𝑧 −1
= … (7.9)
𝑋(𝑧) 1 + 𝑐𝑖 𝑧 −1 + 𝑑𝑖 𝑧 −2
Are shown in figures (7.9 a) and (7.9 b), respectively. The parallel
connection of q + 1 component digital filters as shown in figure (7.9) will
produce the block diagram for the digital filter G(z).

(a)

(b)

Figure (7.7): (a) Block diagram representation of equation (7.8); (b) Block diagram
representation of equation (7.9).

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Computer Engineering Department Dr. Loai Ali Talib