Indian Institute of Information Technology

Allahabad

Embedded System Design (ESD)

Lab File

Aditya Kishore

IEC2023038

Department of Electronics and Communication Engineering

Contents
1 Experiment 1: Half Adder 3
1.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.1 Main Module (Half Adder) . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Experiment 2: Half Subtractor 5

2.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3.1 Main Module (Half Subtractor) . . . . . . . . . . . . . . . . . . . . . 5
2.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Experiment 3: 1-Bit Full Adder 7

3.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.1 Component (Half Adder) . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3.2 Main Module (Full Adder) . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3.3 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 Experiment 4: 1-Bit Full Subtractor 10

4.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3.1 Main Module (Full Subtractor) . . . . . . . . . . . . . . . . . . . . . . 10
4.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Experiment 5: 4-Bit Ripple Carry Adder 13

5.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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 5.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1 Main Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Experiment 6: 4x1 Multiplexer 16

6.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.2.1 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3.1 Main Module (MUX 4x1) . . . . . . . . . . . . . . . . . . . . . . . . 16
6.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Experiment 7: 4-Bit Sequential Multiplier 19

7.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.1 Main Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Experiment 8: 3-Bit Up Counter (3BUC) 22

8.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.3.1 Main Module (3-Bit Up Counter) . . . . . . . . . . . . . . . . . . . . 22
8.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

9 Experiment 9: Universal Shift Register 24

9.1 Aim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2 Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.2.1 Function Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.3 Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
9.3.1 Main Module (Universal Shift Register) . . . . . . . . . . . . . . . . . 24
9.3.2 Testbench . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9.4 Simulation and Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.4.1 Waveform Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Aditya Kishore | IEC2023038 Page 2

 1 Experiment 1: Half Adder
1.1 Aim
To design, implement, and verify a 1-bit Half Adder using a behavioral Verilog model.

1.2 Theory
A Half Adder is a fundamental combinational circuit used in digital logic to perform the addition
of two single-bit numbers. It accepts two 1-bit inputs (A and B) and produces two 1-bit outputs:
a Sum (S) and a Carry (C). It is termed "half" because it cannot accept a carry-in bit from a
previous addition stage, making it suitable only for the least significant bit (LSB) position in an
adder chain.
The logical operation is defined by the following Boolean expressions:
• Sum (S) = A ⊕ B (A XOR B)
• Carry (C) = A · B (A AND B)
This design uses an always @(*) block to model this combinational logic. The * sensitivity
list ensures that the block is re-evaluated immediately if any of the inputs (A or B) change, thus
behaving as a purely combinational circuit.

1.2.1 Truth Table

Table 1: Half Adder Truth Table

Inputs Outputs
A B Sum (S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

1.3 Verilog Code

1.3.1 Main Module (Half Adder)
1 ‘timescale 1ns / 1ps
2
3 module half_adder_behav (
4 input a,
5 input b,
6 output reg c, % Sum
7 output reg d % Carry
8 );
9 always @(*) begin
10 c = a ^ b; % Sum
11 d = a & b; % Carry
12 end
13 endmodule
Listing 1: Main Module (Half Adder)

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 1.3.2 Testbench
1 module hf_tb ();
2 reg a,b;
3 wire c,d;
4
5 half_adder_behav dut (a,b,c,d);
6
7 initial begin
8 a=1’b0; b=1’b0; #10;
9 a=1’b0; b=1’b1; #10;
10 a=1’b1; b=1’b0; #10;
11 a=1’b1; b=1’b1; #10;
12 $finish ;
13 end
14 endmodule
Listing 2: Testbench

1.4 Simulation and Results

The circuit was simulated for all 4 possible input combinations. The testbench steps through
each case (0+0, 0+1, 1+0, 1+1) with a 10ns delay.

1.4.1 Waveform Analysis

The simulation waveform in Figure 1.1 shows the output’s response to the testbench inputs.
• 0-10ns: A=0, B=0. The outputs are c (Sum)=0 and d (Carry)=0.
• 10-20ns: A=0, B=1. The outputs are c (Sum)=1 and d (Carry)=0.
• 20-30ns: A=1, B=0. The outputs are c (Sum)=1 and d (Carry)=0.
• 30-40ns: A=1, B=1. The outputs are c (Sum)=0 and d (Carry)=1.
This behavior perfectly matches the Half Adder truth table.

Figure 1: Simulation waveform for 1-bit Half Adder

1.5 Conclusion
The 1-bit Half Adder was successfully implemented and verified using a behavioral Verilog
model. The simulation confirms the circuit’s combinational functionality, showing that the Sum
and Carry outputs respond correctly to all four input combinations as defined by the standard
half adder truth table.

Aditya Kishore | IEC2023038 Page 4

 2 Experiment 2: Half Subtractor
2.1 Aim
To design, implement, and simulate a 1-bit Half Subtractor using a behavioral Verilog model.

2.2 Theory
A Half Subtractor is a combinational circuit that performs the subtraction of two single-bit
numbers. It accepts two 1-bit inputs, a minuend (A) and a subtrahend (B), and produces two
1-bit outputs: a Difference (D) and a Borrow-out (Bout). It is "half" because it does not have a
borrow-in, making it usable only for the LSB stage of a multi-bit subtractor.
The logical operation is defined by the following Boolean expressions:
• Difference (D) = A ⊕ B (A XOR B)
• Borrow (Bout) = ¬A · B (NOT A AND B)
The always @(*) block is used to model this combinational logic, ensuring the outputs are
updated immediately upon any change in the inputs A or B.

2.2.1 Truth Table

Table 2: Half Subtractor Truth Table

Inputs Outputs
A (Minuend) B (Subtrahend) Diff (D) Borrow (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

2.3 Verilog Code

2.3.1 Main Module (Half Subtractor)
1 ‘timescale 1ns / 1ps
2
3 module Half_Sub (
4 input a,
5 input b,
6 output reg diff ,
7 output reg borrow
8 );
9 always @(*) begin
10 diff = a ^ b;
11 borrow = (~a) & b; % Corrected logic
12 end
13 endmodule
Listing 3: Main Module (Half Subtractor)

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 2.3.2 Testbench
1 module Half_Sub_tb ;
2 reg a, b;
3 wire diff , borrow ;
4

5 Half_Sub dut (.a(a) ,.b(b) ,.diff(diff) ,. borrow ( borrow ));

6
7 initial begin
8 a=0; b=0; #10;
9 a=0; b=1; #10;
10 a=1; b=0; #10;
11 a=1; b=1; #10;
12 $finish ;
13 end
14 endmodule
Listing 4: Testbench

2.4 Simulation and Results

The testbench was written to exhaustively test all four possible input combinations, changing
the inputs every 10ns.

2.4.1 Waveform Analysis

The simulation waveform in Figure 2.1 shows the circuit’s operation.
• 0-10ns: A=0, B=0 (0-0). The outputs are diff=0 and borrow=0.
• 10-20ns: A=0, B=1 (0-1). This is the key case. The outputs are diff=1 and borrow=1.
• 20-30ns: A=1, B=0 (1-0). The outputs are diff=1 and borrow=0.
• 30-40ns: A=1, B=1 (1-1). The outputs are diff=0 and borrow=0.
The simulation results are in complete agreement with the Half Subtractor truth table.

Figure 2: Simulation waveform for 1-bit Half Subtractor

2.5 Conclusion
The 1-bit Half Subtractor was successfully designed and verified using a behavioral Verilog
model. The exhaustive simulation confirms that the circuit correctly implements the Boolean
logic for Difference and Borrow for all four input cases.

Aditya Kishore | IEC2023038 Page 6

 3 Experiment 3: 1-Bit Full Adder
3.1 Aim
To build and verify a 1-bit Full Adder using a structural Verilog model, composed of two Half
Adder components.

3.2 Theory
A Full Adder is a combinational circuit that forms the basis of most digital adders. It adds three
1-bit inputs (A, B, and a Carry-in, Cin) to produce a 2-bit result: a Sum (S) and a Carry-out
(Cout).
This experiment implements the Full Adder using a structural model. This means the circuit
is built by instantiating and connecting smaller, pre-defined components. A Full Adder can be
constructed from two Half Adders (see Experiment 1) and an OR gate, as follows:
1. A first Half Adder adds A and B, producing a partial sum (sum1) and partial carry
(carry1).
2. A second Half Adder adds the partial sum (sum1) and the Cin, producing the final Sum
(S) and a second carry (carry2).
3. An OR gate combines the two partial carries (carry1 and carry2) to create the final
Carry-out (Cout).
This structure implements the standard Full Adder logic: 𝑆 = ( 𝐴 ⊕ 𝐵) ⊕ 𝐶𝑖𝑛 and 𝐶𝑜𝑢𝑡 =
( 𝐴 · 𝐵) + (( 𝐴 ⊕ 𝐵) · 𝐶𝑖𝑛 ).

3.2.1 Truth Table

Table 3: Full Adder Truth Table

Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

3.3 Verilog Code

3.3.1 Component (Half Adder)
1 ‘timescale 1ns / 1ps
2
3 module half_adder ( input a, b, output sum , carry );

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 4 xor (sum , a, b);
5 and (carry , a, b);
6 endmodule
Listing 5: Component (Half Adder)

3.3.2 Main Module (Full Adder)

1 module full_adder ( input a, b, cin , output sum , carry );
2 wire sum1 , carry1 , carry2 ;
3
4 % Instantiate two half adders
5 half_adder ha1 (.a(a) ,.b(b) ,.sum(sum1) ,. carry ( carry1 ));
6 half_adder ha2 (.a(sum1) ,.b(cin) ,.sum(sum) ,. carry ( carry2 ));
7
8 % Combine the carries
9 or (carry , carry1 , carry2 );
10 endmodule
Listing 6: Main Module (Full Adder)

3.3.3 Testbench
1 module full_adder_tb ;
2 reg a, b, cin;
3 wire sum , carry ;
4

5 full_adder dut (a, b, cin , sum , carry );

6
7 initial begin
8 a=0; b=0; cin =0; #10
9 a=0; b=0; cin =1; #10
10 a=0; b=1; cin =0; #10
11 a=0; b=1; cin =1; #10
12 a=1; b=0; cin =0; #10
13 a=1; b=0; cin =1; #10
14 a=1; b=1; cin =0; #10
15 a=1; b=1; cin =1; #10
16 $finish ;
17 end
18 endmodule
Listing 7: Testbench

3.4 Simulation and Results

The testbench was designed to be exhaustive, checking all 23 = 8 possible input combinations
for A, B, and Cin. Each combination is held for 10ns.

3.4.1 Waveform Analysis

The simulation waveform in Figure 3.1 provides a visual verification of the truth table. For
example:
• t=30-40ns: Inputs are A=0, B=1, Cin=1. The outputs are Sum=0 and Carry=1.

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 • t=60-70ns: Inputs are A=1, B=1, Cin=0. The outputs are Sum=0 and Carry=1.
• t=70-80ns: Inputs are A=1, B=1, Cin=1. The outputs are Sum=1 and Carry=1.
All 8 combinations in the waveform correctly match the truth table.

Figure 3: Simulation waveform for 1-bit Full Adder

3.5 Conclusion
The 1-bit Full Adder was successfully implemented using a structural model by instantiating
two half_adder modules and one or gate. The exhaustive simulation confirms the circuit
functions correctly according to the Full Adder truth table, validating the structural design.

Aditya Kishore | IEC2023038 Page 9

 4 Experiment 4: 1-Bit Full Subtractor
4.1 Aim
To design and verify a 1-bit Full Subtractor using dataflow modeling in Verilog.

4.2 Theory
A Full Subtractor is a combinational circuit that performs the subtraction of three 1-bit numbers:
the minuend (A), subtrahend (B), and a borrow-in (Bin) from a previous, less significant stage.
It produces two outputs: the Difference (D) and the Borrow-out (Bout).
This implementation uses dataflow modeling, where assign statements are used to directly
implement the Boolean logic derived from the circuit’s truth table:
• Difference (D) = A ⊕ B ⊕ Bin
• Borrow-out (Bout) = (¬A · B) + (¬(A ⊕ B) · Bin)
(Note: + represents the OR operation).

4.2.1 Truth Table

Table 4: Full Subtractor Truth Table

Inputs Outputs
A B Bin Diff (D) Borrow (Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

4.3 Verilog Code

4.3.1 Main Module (Full Subtractor)
1 ‘timescale 1ns / 1ps
2
3 module full_sub ( input a, b, bin , output diff , bout);
4 assign diff = a ^ b ^ bin;
5 assign bout = (~a & b) | (~(a ^ b)) & bin;
6 endmodule
Listing 8: Main Module (Full Subtractor)

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 4.3.2 Testbench
1 module full_sub_tb ;
2 reg a, b, bin;
3 wire diff , bout;
4

5 full_sub dut (a, b, bin , diff , bout);

6
7 initial begin
8 a=0; b=0; bin =0;
9 #10 a=0; b=0; bin =1;
10 #10 a=0; b=1; bin =0;
11 #10 a=0; b=1; bin =1;
12 #10 a=1; b=0; bin =0;
13 #10 a=1; b=0; bin =1;
14 #10 a=1; b=1; bin =0;
15 #10 a=1; b=1; bin =1; #10
16 $finish ;
17 end
18 endmodule
Listing 9: Testbench

4.4 Simulation and Results

The testbench was written to exhaustively test all 23 = 8 possible input combinations, holding
each for 10ns.

4.4.1 Waveform Analysis

The simulation waveform in Figure 4.1 shows the circuit’s response. We can check a few key
cases against the truth table:
• t=10-20ns: A=0, B=0, Bin=1 (0-0-1). Outputs are Diff=1, Bout=1. Correct.
• t=30-40ns: A=0, B=1, Bin=1 (0-1-1). Outputs are Diff=0, Bout=1. Correct.
• t=50-60ns: A=1, B=0, Bin=1 (1-0-1). Outputs are Diff=0, Bout=0. Correct.
• t=70-80ns: A=1, B=1, Bin=1 (1-1-1). Outputs are Diff=1, Bout=1. Correct.
All 8 combinations shown in the waveform match the truth table.

Figure 4: Simulation waveform for 1-bit Full Subtractor

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4.5 Conclusion
The 1-bit Full Subtractor was successfully designed and implemented using Verilog’s dataflow
modeling. The exhaustive testbench confirmed that the circuit’s outputs for Difference and
Borrow-out perfectly match the standard truth table for all possible inputs.

Aditya Kishore | IEC2023038 Page 12

 5 Experiment 5: 4-Bit Ripple Carry Adder
5.1 Aim
To implement and test a 4-bit Ripple Carry Adder (RCA) using Verilog’s dataflow modeling
capabilities.

5.2 Theory
A 4-bit Ripple Carry Adder (RCA) is a digital circuit that adds two 4-bit binary numbers
(A[3:0] and B[3:0]) and an initial carry-in (Cin). It produces a 4-bit Sum (Sum[3:0]) and a final
carry-out (Carry).
It is constructed by cascading four 1-bit Full Adders (see Experiment 3 for the Full Adder’s
logic). It is called a "ripple" adder because the carry-out from one stage (e.g., bit 0) becomes
the carry-in for the next, more significant stage (bit 1). This chain reaction continues to the final
bit.
This design uses dataflow modeling, where assign statements describe the logic for each full
adder stage. The bit-concatenation syntax {c1, sum[0]} is used to assign the 2-bit result of
the addition to the carry-out wire (c1) and the sum output bit (sum[0]).
The primary drawback of this design is its speed, which is limited by the carry propagation
delay. The final sum and carry are not valid until the carry signal has "rippled" through all four
stages.

5.3 Verilog Code

5.3.1 Main Module
1 ‘timescale 1ns / 1ps
2
3 module rca (
4 input [3:0] a,
5 input [3:0] b,
6 input cin ,
7 output [3:0] sum ,
8 output carry
9 );
10 % Wires for intermediate carries
11 wire c1 , c2 , c3;
12
13 % Dataflow model of 4-bit RCA
14 assign {c1 , sum [0]} = a[0] + b[0] + cin;
15 assign {c2 , sum [1]} = a[1] + b[1] + c1;
16 assign {c3 , sum [2]} = a[2] + b[2] + c2;
17 assign {carry , sum [3]} = a[3] + b[3] + c3;
18
19 endmodule
Listing 10: Main Module

5.3.2 Testbench

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 1 module rca_tb ;
2 reg [3:0] a;
3 reg [3:0] b;
4 reg cin;
5 wire [3:0] sum;
6 wire carry ;
7

8 rca dut (a, b, cin , sum , carry );

9
10 initial begin
11 % Test 5 + 3 + 1 = 9
12 a = 4’ b0101 ;
13 b = 4’ b0011 ;
14 cin = 1;
15 #10;
16 $display ("A=%b B=%b C_in =%b, Sum =%b, C_out =%b", a, b, cin , sum ,
carry );
17 $finish ;
18 end
19 endmodule
Listing 11: Testbench

5.4 Simulation and Results

The testbench was designed to simulate a single test case: 5 + 3 + 1.
• Input a = 4’b0101 (Decimal 5)
• Input b = 4’b0011 (Decimal 3)
• Input cin = 1
The expected result is 5 + 3 + 1 = 9, which is 4’b1001 with a final carry-out of 0.

5.4.1 Waveform Analysis

The simulation waveform in Figure 5.1 shows the inputs a, b, and cin being set at the start of
the simulation. After a small propagation delay, the outputs stabilize to their final values:
• sum[3:0] = 4’b1001 (Decimal 9)
• carry = 0
The simulator log output from the $display command also confirms this result: A=0101
B=0011 C_in=1, Sum=1001, C_out=0.

Figure 5: Simulation waveform for 4-bit Ripple Carry Adder

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5.5 Conclusion
The 4-bit Ripple Carry Adder was successfully designed and implemented using Verilog’s
dataflow modeling. The simulation results, confirmed by both the waveform and the console
log, show that the circuit correctly performs 4-bit addition, validating the logic of the cascaded
full adders.

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 6 Experiment 6: 4x1 Multiplexer
6.1 Aim
To design and simulate a 4-to-1 Multiplexer (MUX) using a behavioral case statement in
Verilog.

6.2 Theory
A multiplexer (MUX), or data selector, is a combinational circuit that selects one of several
input lines and routes it to a single output line. A 4-to-1 MUX has four 1-bit data inputs (D0,
D1, D2, D3), two select lines (S0, S1), and one 1-bit output (Y). The 2-bit binary value on the
select lines determines which of the four data inputs is passed to the output.
This experiment implements the MUX using a behavioral Verilog model. This is a high-level ab-
straction that describes the circuit’s function. The always @(*) block creates a combinational
circuit that is sensitive to changes in any of its inputs. The case statement is an ideal construct
for describing multiplexer logic, as it directly maps the ’sel’ inputs to the corresponding data
input.

6.2.1 Function Table

Table 5: 4x1 MUX Function Table

Select Inputs Output
sel[1] sel[0] y
0 0 d[0]
0 1 d[1]
1 0 d[2]
1 1 d[3]

6.3 Verilog Code

6.3.1 Main Module (MUX 4x1)
1 ‘timescale 1ns / 1ps
2

3 module mux4x1 (
4 input [3:0] d,
5 input [1:0] sel ,
6 output reg y
7 );
8

9 always @(*) begin

10 case (sel)
11 2’b00: y = d[0];
12 2’b01: y = d[1];
13 2’b10: y = d[2];
14 2’b11: y = d[3];
15 default : y = 1’bx; % Good practice
16 endcase
17 end

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18 endmodule
Listing 12: Main Module (MUX 4x1)

6.3.2 Testbench
1 module mux_tb ;
2 reg [3:0] d;
3 reg [1:0] sel;
4 wire y;
5

6 mux4x1 uut (.d(d) ,.sel(sel) ,.y(y));

7
8 initial begin
9 d = 4’ b1101 ; % d[3]=1 , d[2]=1 , d[1]=0 , d [0]=1
10
11 sel = 2’b00; #10; % y should be d[0] (1)
12 sel = 2’b01; #10; % y should be d[1] (0)
13 sel = 2’b10; #10; % y should be d[2] (1)
14 sel = 2’b11; #10; % y should be d[3] (1)
15
16 $finish ;
17 end
18 endmodule
Listing 13: Testbench

6.4 Simulation and Results

The testbench sets the 4-bit data input d to a constant value of 4’b1101. This means d[0]=1,
d[1]=0, d[2]=1, and d[3]=1. The testbench then cycles the sel input through all four possible
states.

6.4.1 Waveform Analysis

The simulation waveform in Figure 6.1 clearly demonstrates the MUX operation:
• 0-10ns: sel is 2’b00. The output y correctly selects d[0], which is 1.
• 10-20ns: sel is 2’b01. The output y correctly selects d[1], which is 0.
• 20-30ns: sel is 2’b10. The output y correctly selects d[2], which is 1.
• 30-40ns: sel is 2’b11. The output y correctly selects d[3], which is 1.
The output y changes immediately in response to the changes in sel, confirming the circuit’s
combinational nature.

Figure 6: Simulation waveform for 4x1 Multiplexer

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6.5 Conclusion
The 4x1 Multiplexer was successfully designed using a behavioral case statement. The sim-
ulation results confirm that the circuit functions as a data selector, correctly routing one of the
four data inputs to the output based on the value of the select lines, in perfect alignment with
the MUX function table.

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 7 Experiment 7: 4-Bit Sequential Multiplier
7.1 Aim
To design a 4-bit sequential multiplier using the "add-and-shift" algorithm in Verilog.

7.2 Theory
A sequential multiplier computes the product of two binary numbers (A, the multiplicand, and
B, the multiplier) over several clock cycles. This is in contrast to a combinational multiplier,
which would be much larger. This design uses the "add-and-shift" algorithm.
The circuit uses an 8-bit register for the product (P), two 4-bit registers (A and B), and a counter.
The operation is as follows:
1. Initialization (on Reset): The multiplicand is loaded into A, the multiplier is
loaded into B, the product P is cleared to 0, and a count is initialized to 4 (for a 4-bit
operation).
2. Execution (on Clock Edge): For 4 clock cycles (while 𝑐𝑜𝑢𝑛𝑡 > 0), the circuit does the
following:
• Check LSB: It checks the least significant bit (LSB) of the multiplier, B[0].
• Add: If B[0] is 1, the current value of the multiplicand A (shifted appropriately) is
added to the partial product P.
• Shift: The multiplicand register A is shifted left by 1 bit, and the multiplier register
B is shifted right by 1 bit. This prepares A for the next addition (multiplying it by 2)
and exposes the next bit of B.
• Decrement: The count is decremented.
3. Done: After 4 cycles, the count reaches 0, the operation stops, and the final 8-bit product
is held in the P register.

7.3 Verilog Code

7.3.1 Main Module
1 ‘timescale 1ns / 1ps
2
3 module multiplier_4_bit (
4 input clk ,
5 input reset ,
6 input [3:0] multiplicand ,
7 input [3:0] multiplier ,
8 output reg [7:0] P
9 );
10
11 reg [3:0] A, B;
12 reg [2:0] count ;
13
14 always @( posedge clk or posedge reset ) begin
15 if ( reset ) begin
16 A <= multiplicand ;

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17 B <= multiplier ;
18 P <= 8’b0;
19 count <= 3’b100; % Initialize count to 4
20 end
21 else if ( count > 0) begin
22 if (B[0] == 1) begin
23 % Add multiplicand to P
24 P <= P + {4’b0000 , A};
25 end
26 A <= A << 1; % Shift multiplicand left
27 B <= B >> 1; % Shift multiplier right
28 count <= count - 1;
29 end
30 end
31 endmodule
Listing 14: Main Module

7.3.2 Testbench
1 % Testbench
2 module multiplier_4_bit_tb ;
3 reg clk;
4 reg reset ;
5 reg [3:0] multiplicand ;
6 reg [3:0] multiplier ;
7 wire [7:0] P;
8
9 multiplier_4_bit uut (. clk(clk), . reset ( reset ), . multiplicand (
10 multiplicand ), . multiplier ( multiplier ) ,.P(P));
11
12 initial clk = 0;
13 always #5 clk = ~clk; % Create a 10 ns clock period
14
15 initial begin
16 multiplicand = 4’d2; % A = 0010
17 multiplier = 4’d3; % B = 0011
18 reset = 1; #10;
19 reset = 0; #50; % Allow 5 clock cycles
20 $finish ;
21 end
22 endmodule
Listing 15: Testbench

7.4 Simulation and Results

The testbench initializes the inputs to A=2 (0010) and B=3 (0011). The circuit is reset and then
the calculation proceeds.

7.4.1 Waveform Analysis

The waveform in Figure 7.1 shows the step-by-step sequential calculation:
• Reset (t=0-10ns): reset is high. P is 0, A is 2, B is 3, count is 4.

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 • Cycle 1 (t=10ns posedge): 𝑐𝑜𝑢𝑛𝑡 > 0. B[0] is 1. P ← P + A (0 + 2). P becomes 2. A
shifts left to 4 (0100). B shifts right to 1 (0001). count becomes 3.
• Cycle 2 (t=20ns posedge): 𝑐𝑜𝑢𝑛𝑡 > 0. B[0] is 1. P ← P + A (2 + 4). P becomes 6. A
shifts left to 8 (1000). B shifts right to 0 (0000). count becomes 2.
• Cycle 3 (t=30ns posedge): 𝑐𝑜𝑢𝑛𝑡 > 0. B[0] is 0. No addition. A shifts left to 16
(overflow, but doesn’t matter). B shifts right to 0. count becomes 1.
• Cycle 4 (t=40ns posedge): 𝑐𝑜𝑢𝑛𝑡 > 0. B[0] is 0. No addition. count becomes 0.
• 𝑡 > 40𝑛𝑠: The 𝑐𝑜𝑢𝑛𝑡 > 0 condition is false. The circuit holds the final value P = 6.
The final result 06 (hex) is correct.

Figure 7: Simulation waveform for 4-bit Sequential Multiplier

7.5 Conclusion
The 4x4 sequential multiplier was successfully implemented using the "add-and-shift" algo-
rithm. The simulation trace clearly verified the correct step-by-step operation over four clock
cycles, and the testbench confirmed the final product (2 * 3 = 6) was correct.

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 8 Experiment 8: 3-Bit Up Counter (3BUC)
8.1 Aim
To design and simulate a 3-bit synchronous up-counter (Mod-8) with an active-high asyn-
chronous reset using Verilog.

8.2 Theory
A 3-bit up-counter is a sequential circuit that cycles through 8 distinct states, from 0 (000) to
7 (111), and then "rolls over" back to 0. This design is synchronous, meaning all internal
flip-flops share a common clock and change state at the same time (on the positive clock edge).
It also features an asynchronous reset. The always @(posedge clk or posedge reset)
sensitivity list means the block will trigger on a positive clock edge or a positive reset edge. If
reset goes high, the if (reset) condition is met, and the counter is immediately forced to
000, regardless of the clock.
The counting logic is a behavioral model of a T-Flip-Flop-based counter:
• count[0] <= ~count[0]; (T-FF for Q0 with T=1, always toggles).
• count[1] <= count[1] ^ count[0]; (T-FF for Q1 with T=Q0, toggles only if Q0 is 1).
• count[2] <= count[2] ^ (count[0] & count[1]);(T-FF for Q2 with T=Q0·Q1, toggles
only if Q0 and Q1 are both 1).

8.3 Verilog Code

8.3.1 Main Module (3-Bit Up Counter)
1 ‘timescale 1ns / 1ps
2
3 module ThreeBUC (
4 input wire clk ,
5 input wire reset ,
6 output reg [2:0] count
7 );
8 % Corrected T-Flip -Flop logic for a 3-bit counter
9 always @( posedge clk or posedge reset ) begin
10 if ( reset )
11 count <= 3’b000;
12 else begin
13 count [0] <= ~ count [0];
14 count [1] <= count [1] ^ count [0];
15 count [2] <= count [2] ^ ( count [0] & count [1]);
16 end
17 end
18 endmodule
Listing 16: Main Module (3-Bit Up Counter)

8.3.2 Testbench
1 % Testbench
2 module tb_up_counter_3bit ;

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 3 reg clk;
4 reg reset ;
5 wire [2:0] count ;
6
7 ThreeBUC uut (. clk(clk) ,. reset ( reset ) ,. count ( count ));
8
9 initial begin
10 clk = 0;
11 forever #5 clk = ~clk; % 10 ns clock period
12 end
13
14 initial begin
15 reset = 1;
16 #10;
17 reset = 0;
18 #200;
19 $finish ;
20 end
21 endmodule
Listing 17: Testbench

8.4 Simulation and Results

The testbench first asserts reset for 10ns, then de-asserts it, allowing the counter to run freely
for 200ns.

8.4.1 Waveform Analysis

The waveform in Figure 8.1 demonstrates two key behaviors:
1. Asynchronous Reset (t=0-10ns): reset is high. Even as the clk signal toggles, the
count output is immediately forced to and held at 0 (000).
2. Synchronous Counting (t > 10ns): Once reset goes low, the counter begins incre-
menting on every positive edge of the clk. The sequence 0-1-2-3-4-5-6-7 is clearly
visible. After reaching 7 (111), the counter correctly rolls over to 0 (000) and continues
the sequence.

Figure 8: Simulation waveform for 3-bit Up Counter

8.5 Conclusion
The 3-bit synchronous up-counter with asynchronous reset was successfully designed and
verified. The simulation confirmed both the immediate asynchronous reset to 0 and the correct
synchronous counting sequence from 000 to 111 with a proper rollover.

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9 Experiment 9: Universal Shift Register
9.1 Aim
To design and verify a 4-bit synchronous Universal Shift Register in Verilog, demonstrating
hold, parallel load, rotate-left, and rotate-right operations.

9.2 Theory
A Universal Shift Register is a highly versatile sequential circuit that combines multiple op-
erations into one module. This 4-bit register’s operation is controlled by a 2-bit select line
(S).
The design uses a single always @(posedge clk or posedge rst) block. This creates a
circuit that is sensitive to two events:
1. posedge rst: An active-high asynchronous reset. If rst goes high, the register immedi-
ately clears to 4’b0000, overriding any clock signal.
2. posedge clk: A synchronous clock edge. If rst is low, the circuit performs an operation
based on the S inputs at the moment of the clock’s rising edge.
The case statement implements the four operations:
• 2’b00 (Hold): Q <= Q; The register’s output is fed back to its input, so its value does
not change.
• 2’b01 (Rotate Left): Q <= {Q[2:0], Q[3]}; The bits are shifted left. The MSB
(Q[3]) is moved to the LSB position (Q[0]).
• 2’b10 (Rotate Right): Q <= {Q[0], Q[3:1]}; The bits are shifted right. The LSB
(Q[0]) is moved to the MSB position (Q[3]).
• 2’b11 (Parallel Load): Q <= parallel_in; The 4-bit parallel_in value is loaded
directly into the register.

9.2.1 Function Table

Table 6: Universal Shift Register Function Table

Select (S) Operation
S[1] S[0]
0 0 Hold (No Change)
0 1 Rotate Left
1 0 Rotate Right
1 1 Parallel Load

9.3 Verilog Code

9.3.1 Main Module (Universal Shift Register)

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 1 ‘timescale 1ns / 1ps
2
3 module uniShiftReg (
4 input wire clk ,
5 input wire rst ,
6 input wire [1:0] S,
7 input wire [3:0] parallel_in ,
8 output reg [3:0] Q
9 );
10
11 always @( posedge clk or posedge rst)
12 begin
13 if (rst)
14 Q <= 4’ b0000 ;
15 else
16 case (S)
17 2’b00: Q <= Q;
18 2’b01: Q <= {Q[2:0] , Q [3]};
19 2’b10: Q <= {Q[0] , Q [3:1]};
20 2’b11: Q <= parallel_in ;
21 endcase
22 end
23 endmodule
Listing 18: Main Module (Universal Shift Register)

9.3.2 Testbench
1 % Testbench
2 module tb ();
3 reg clk;
4 reg rst;
5 reg [1:0] S;
6 reg [3:0] parallel_in ;
7 wire [3:0] Q;
8
9 uniShiftReg dut (. clk(clk) ,.rst(rst) ,.S(S) ,. parallel_in ( parallel_in ) ,.Q
(Q));
10
11 always #25 clk = ~clk; % 50 ns clock period
12
13 initial begin
14 clk = 0;
15 rst = 1;
16 S = 2’b00;
17 parallel_in = 4’ b0010 ; % 2
18
19 #12 rst = 0;
20 S = 2’b11; #10; % Load 2
21 S = 2’b00; #10; % Hold 2
22 S = 2’b01; #10; % Rotate Left (Q becomes 4)
23 S = 2’b10; #10; % Rotate Right (Q becomes 2)
24 parallel_in = 4’ b1011 ; % 11
25 S = 2’b11; #10; % Load 11
26 $finish ;
27 end

Aditya Kishore | IEC2023038 Page 25

28 endmodule
Listing 19: Testbench

9.4 Simulation and Results

The testbench was designed to test all four operations in sequence after an initial reset.

9.4.1 Waveform Analysis

The waveform in Figure 9.1 shows the behavior (note: changes happen on the positive clock
edge *after* the select lines change):
• Reset (t=0-12ns): rst is high, Q is held at 0 (0000).
• Load (t=12-22ns): S=11, parallel_in=2. At the next posedge clk, Q becomes 2 (0010).
• Hold (t=22-32ns): S=00. At the next posedge clk, Q remains 2 (0010).
• Rotate Left (t=32-42ns): S=01. At the next posedge clk, Q (0010) rotates left to become
4 (0100).
• Rotate Right (t=42-52ns): S=10. At the next posedge clk, Q (0100) rotates right to
become 2 (0010).
• Load (t=52-62ns): S=11, parallel_in=11. At the next posedge clk, Q becomes 11
(1011).

Figure 9: Simulation waveform for 4-bit Universal Shift Register

9.5 Conclusion
The 4-bit Universal Shift Register was successfully implemented and verified. The simulation
clearly demonstrates the correct functionality of the asynchronous reset and all four synchronous
operations (Hold, Rotate Left, Rotate Right, and Parallel Load), validating the design.

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