Digital System Design – EC661

[Link] - VLSI SYSTEMS

Dr. SRINIVASULU JOGI

Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHONOLOGY TIRUCHIRAPPALLI
TIRUCHIRAPPALLI-620015
 Digital System Design-EC661

Course Content
⚫ Mapping algorithms into Architectures: Data path synthesis, control structures,
critical path and worst case timing analysis. FSM and Hazards.

⚫ Combinational network delay. Power and energy optimization in combinational

logic circuit. Sequential machine design styles. Rules for clocking. Performance
analysis.

⚫ Sequencing static circuits. Circuit design of latches and flip-flops. Static

sequencing element methodology. Sequencing dynamic circuits. Synchronizers.

⚫ Data path and array subsystems: Addition / Subtraction, Comparators, counters,

coding, multiplication and division. SRAM, DRAM, ROM, serial access memory,
context addressable memory.

⚫ Reconfigurable Computing- Fine grain and Coarse grain architectures,

Configuration architectures-Single context, Multi context, partially
reconfigurable, Pipeline reconfigurable, Block Configurable, Parallel processing.
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Assessment Methodology

 Module 3-Sequencing Static Circuits

Sequencing Static Circuits

⚫ Sequential circuits are usually designed with flip-flops or latches,

which are sometimes called memory elements, that hold data called
tokens.
⚫ The purpose of these elements is not really memory; instead it is to
enforce sequence, to distinguish current token from the previous or
next token.
⚫ Therefore the latches and flip-flops are called as sequencing
elements.
⚫ This module discusses about sequencing (for both static and
dynamic circuits) and synchronization.
 Module 3-Sequencing Static Circuits

Causality Arrows:
⚫ Arrow shows cause and effect.
⚫ Arrows are also used to show the delay between two signals.
 Module 3-Sequencing Static Circuits

Sequencing Static Circuits

⚫ Latches and flip-flops are the two most commonly used sequencing
elements.
⚫ An ideal sequencing methodology would introduce
⚫ no sequencing overhead,

⚫ allow sequencing elements back-to-back with no logic in

between,
⚫ grant the designer flexibility in balancing the amount of logic in

each clock cycle,

⚫ tolerate moderate amounts of clock skew without degrading

performance,
⚫ consume zero area and power.
 Module 3-Sequencing Static Circuits

Sequencing Static Circuits

⚫ The three most widely used methods of sequencing static circuits

with these elements are
⚫ flip-flops,

⚫ 2-phase transparent latches,

⚫ pulsed latches
 Module 3-Sequencing Static Circuits

Sequencing Static Circuits

⚫ Flip-flops based
sequencing method
⚫

⚫ 2-phase transparent
latches based
sequencing method

⚫ pulsed latches based

sequencing method
 Module 3-Sequencing Static Circuits

Flip-flop based sequencing

⚫ The token in captured in the first flip-flop on the first rising edge of
the clock.
⚫ It then propagates through the combinational logic and reaches the
second flip-flop on the second rising edge of the clock.
⚫
 Module 3-Sequencing Static Circuits

Flip-flop based sequencing

⚫ Flip-flop based systems use one flip-flop on each cycle boundary.
⚫ Tokens advance from one cycle to the next on the rising edge.
⚫ If a token arrives too early, it waits at the flip-flop until the next
cycle.
 Module 3-Sequencing Static Circuits

Flip-flop based sequencing

⚫ The flip-flop can be viewed as a pair of back-to-back latches using
clk and its complement.
 Module 3-Sequencing Static Circuits

Latch based sequencing

⚫ If we separate the latches, we can divide the full cycle of
combinational logic into two phases called half-cycles.
 Module 3-Sequencing Static Circuits

Pulsed Latch based sequencing

⚫ Pulse latch systems eliminate one of the latches from each cycle
and apply a brief pulse to the remaining latch.
⚫ Pulse width is tpw.
⚫ Each token will advance through only one clock cycle on each
pulse.
 Module 3-Sequencing Static Circuits

Delays and Timing constraints

⚫ The delays and timing constraints of the combinational logic and
sequencing elements are given as follows
 Module 3-Sequencing Static Circuits

Delays and Timing constraints

⚫ The delays and timing constraints of the combinational logic and
sequencing elements are given as follows
 Module 3-Sequencing Static Circuits

Terminology
⚫ A pair of lines indicates that a signal is stable but that we don’t care
about its value.

⚫ Criss-crossed lines indicate that the signal might change at that

time.

⚫ A pair of lines with cross-hatching indicates that the signal may

change once or more over an interval of time.
 Module 3-Sequencing Static Circuits

Delays definitions
⚫ For changes in A, the output Y cannot change instantaneously.
⚫ There is a minimum amount of time needed for a change in logic
input to result in an initial change at an output. This time is called
contamination delay (tcd).
⚫ Output Y settles and become stable after propagation delay (tpd).
⚫ The tcd and tpd are different because of multiple paths through the
combinational logic.
 Module 3-Sequencing Static Circuits

Delays definitions
⚫ Response of a flip-flop is shown.
⚫ D input must obey setup and hold time.
⚫ The output begins to change after a clock-to-Q contamination delay
(tccq) and completely settles after a clock-to-Q propagation delay
tpcq.
 Module 3-Sequencing Static Circuits

Delays definitions
⚫ Response of a latch is shown.
⚫ Input D must setup and hold around the falling edge that defines the
end of sampling period.
⚫ Output Q initially changes at tccq and finally settles at tpcq.
⚫ While the latch is transparent, the output will continue to track the
input after the delays tcdq and tpdq.
 Module 3-Sequencing Static Circuits

Maximum Delays constraints

⚫ Ideally, the entire clock cycle would be available for computations
in the combinational logic.
⚫ If the combinational logic delay is too great, the receiving element
will miss its setup time and sample the wrong value. This is called a
setup time failure or max-delay failure.
⚫ It can be solved by redesigning the logic to be faster or by
increasing the clock period.
⚫ Now we compute the actual time available for logic and the
sequencing overhead of each of our favorite sequencing elements:
flip-flops, two-phase latches, and pulsed latches.
⚫ .
 Module 3-Sequencing Static Circuits

Maximum Delays constraints-Flip-flop

⚫ The path begins with the rising edge of the clock triggering F1.
⚫ The data must propagate to the output of the flip-flop Q1 and
through the combinational logic to D2, setting up at F2 before the
next rising clock edge.
 Module 3-Sequencing Static Circuits

Maximum Delays constraints-Flip-flop

⚫ This implies

⚫ So, Maximum allowable delay

 Module 3-Sequencing Static Circuits

Maximum Delays constraints-2 phase latch

⚫ Let us assume that
data D1 arrives at
L1 while the latch
is transparent (ϕ1
high). The data
propagates through
L1, the first block
of combinational
logic, L2, and the
second block of
combinational
logic..
 Module 3-Sequencing Static Circuits

Maximum Delays constraints-2 phase latch

⚫ Technically, D3 could
arrive as late as a setup
time before the falling
edge of ϕ1 and still be
captured correctly by L3.
⚫ To be fair, we will insist
that D3 nominally arrive
no more than one clock
period after D1 because,
in the long run, it is
impossible for every
single-cycle path in a
design to consume more
than a full clock period.
 Module 3-Sequencing Static Circuits

Maximum Delays constraints-2 phase latch

⚫ Certain paths may take
longer if other paths take
less time; this technique
is called time borrowing.
⚫ Assuming the path takes
no more than a cycle, we
see the cycle time must
be

⚫ Max delay is
 Module 3-Sequencing Static Circuits

Maximum Delays constraints-2 phase latch

⚫ Max allowable delay is

 Module 3-Sequencing Static Circuits

Minimum Delays constraints-Flip-flop

⚫ If the hold time is large and the contamination delay is small, data
can incorrectly propagate through two successive elements on one
clock edge, corrupting the state of the system.
⚫ This is called race condition, hold-time failure or min-delay failure.
⚫ This can be fixed by redesigning the logic and not by slowing the
clock.
 Module 3-Sequencing Static Circuits

Minimum Delays constraints-Flip-flop

⚫ Minimum delay
 Module 3-Sequencing Static Circuits

Minimum Delays constraints-2 phase latch

⚫ Fig shows the min-
delay timing
constraints on a
path from one
transparent latch to
the next.
⚫ The path begins
with data passing
through L1 on the
rising edge of ϕ1.
 Module 3-Sequencing Static Circuits

Minimum Delays constraints-2 phase latch

⚫ It must not reach
L2 until a hold time
after the previous
falling edge of ϕ2
because L2 should
have become safely
opaque before L1
becomes
transparent.
 Module 3-Sequencing Static Circuits

Minimum Delays constraints-2 phase latch

⚫ As the edges are
separated by
t_nonoverlap , the
minimum logic
contamination
delay through each
phase of logic is
 Module 3-Sequencing Static Circuits

Clock Skew-Flip-flop-Max delay

⚫ The analysis so far has assumed ideal clocks with zero skew.
⚫ In reality, clocks have some uncertainty in their arrival times that
can cut into the time available for useful computation.
 Module 3-Sequencing Static Circuits

Clock Skew-Flip-flop-Min delay

⚫
 Module 3-Sequencing Static Circuits

Clock Skew-2 phase latch-Max and Min delay

⚫ In the system using transparent latches, clock skew does not
degrade performance.
⚫ Even though the clocks are skewed, the data can still arrive at the
latches while they are transparent.
⚫ Therefore, the transparent latch-based systems are skew-tolerant.
⚫ Max logic delay (both with and without clock skew):

⚫ Skew effectively increases hold time in each half-cycle.

⚫ Min logic delay with skew:
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Conventional CMOS latches are built
⚫ using pass transistors or tri-state buffers to pass the data while the

latch is transparent and

⚫ using feedback to hold the data while the latch is opaque.

⚫ It is also possible to build logic functions into the latches to reduce

the sequencing overhead.
⚫ (a) Simple latch
⚫ It is compact and fast

⚫ Output does not swing rail-to-rail

⚫ Because output never rises above VDD – Vt

⚫ Output is dynamic.

⚫ Noise on the output can corrupt the state.

⚫ D drives diffusion input of a pass transistor directly, leading to

potential noise issues.

 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ (b) latch
⚫ Single nMOS transistor is replaced by a CMOS transmission gate.
⚫ It requires complementary clock signals.

⚫ Advantages – rail-to-rail output swing.

⚫ (c) An output inverter is added so that the state node X is isolated

from noise on the output.
⚫ Of course, this creates an inverting latch.
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ (d) Inverting latch with a buffered input but un-buffered output.
⚫ Inverter followed by a transmission gate is essentially equivalent

to a tristate inverter.
⚫ (c) and (d) are fast dynamic latches

⚫ Need for feedback

⚫ Subthreshold leakage.

⚫ Dynamic nodes retain their values for only a short time.

 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ (e) So to prevent the dynamic nodes from floating, latches need to
be staticized by adding feedback.
⚫ When the clock is 0, the input transmission gate turns OFF.

⚫ However, the feedback tristate turns ON, holding X at the correct

level.
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ (f) An inverter is added at the input, so the input is a transistor gate
rather then unbuffered diffusion.
⚫ Both (e) and (f) reintroduced output noise sensitivity: A large

noise spike on the output can propagate backward through the

feedback gates and corrupt the state node X.
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ (g)Robust Latch
⚫ The latch is static

⚫ All nodes swing rail-to-rail

⚫ The state noise is isolated from output noise, and

⚫ The input drives transistor gates rather than diffusion

⚫ Such a latch is widely used in standard cell applications including

the Artisan standard cell library

 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Clocked CMOS (C2MOS)
⚫ The dynamic latch of (d) can also be drawn as clocked tristate as

shown
⚫ Called clocked CMOS (C MOS)
2

⚫ The conventional form using the inverter and transmission gate is

slightly faster because the output is driven through the nMOS and
pMOS working in parallel.

C2MOS latch
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Conventional CMOS Flip-Flops
⚫ Fig shows dynamic inverting flip-flop built from a pair of back-

to-back dynamic latches.

⚫ Either the first or the last inverter can be removed to reduce

delay at the expense of greater noise sensitivity on the

unbuffered input or output.
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Conventional CMOS Flip-Flops
⚫ Fig shown adds feedback and another inverter to produce a non-

inverting static flip-flop.

⚫ Most standard cell libraries employ this design because it is

simple, robust, compact, and energy-efficient.

 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Transmission gate based dynamic flip-flop
⚫ When φ falls, both the clock and its complement are momentarily

low turning on the clocked pMOS transistors in both transmission

gates.
⚫ If the skew (i.e., inverter delay) is too large, the data can sneak

through both latches on the falling clock edge, leading to

incorrect operation.
⚫ Problem: both master and slave can be transparent at the same

time.
⚫ Solution: clocked CMOS (C MOS)
2
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Transmission gate based dynamic flip-flop
⚫ When φ falls, both the clock and its complement are momentarily

low turning on the clocked pMOS transistors in both transmission

gates.
 Module 3- Circuit Design of Latches and FF

Circuit Design of Latches and Flip-flops

⚫ Transmission gate based dynamic flip-flop
⚫ Because each stage inverts, data passes through the nMOS stack

of one latch and the pMOS of the other, so skew that turns on
both clocked pMOS transistors is not a hazard.

C2MOS dynamic Flip-Flop

 Module 3- Circuit Design of Latches and FF

Resettable Latches and Flip-flops

⚫ Types of resets : Synchronous and Asynchronous
⚫ Asynchronous reset forces Q low immediately, while synchronous

reset waits for the clock.

⚫ Synchronous reset signals must be stable for a setup and hold

time around the clock edge.

⚫ Asynchronous reset is characterized by a propagation delay

from reset to output

 Module 3- Circuit Design of Latches and FF

Resettable Latches and Flip-flops

⚫ Types of resets : Synchronous and Asynchronous
⚫ Asynchronous reset forces Q low immediately, while synchronous

reset waits for the clock.

⚫ Synchronous reset signals must be stable for a setup and hold

time around the clock edge.

⚫ Asynchronous reset is characterized by a propagation delay

from reset to output

 Module 3- Circuit Design of Latches and FF

Resettable Latches and Flip-flops

⚫ Types of resets : Synchronous and Asynchronous
⚫ Asynchronous reset forces Q low immediately, while synchronous

reset waits for the clock.

⚫ Synchronous reset signals must be stable for a setup and hold

time around the clock edge.

⚫ Asynchronous reset is characterized by a propagation delay

from reset to output

 Module 3- Circuit Design of Latches and FF

Enabled Latches and Flip-flops

⚫ Sequencing elements also often accept an enable input.
⚫ When enable en is low, the element retains its state independent of
the clock.
⚫ The enable can be performed with an
⚫ input multiplexer (or )

⚫ clock gating
 Module 3- Circuit Design of Latches and FF

Enabled Latches and Flip-flops

⚫ Multiplexer
⚫ The input multiplexer feeds back the old state when the element is

disabled.
⚫ The multiplexer adds area and delay.

⚫ Clock gating.
⚫ Clock gating does not affect delay from the data input.

⚫ Moreover, it significantly reduces power consumption because the

clock on the disabled element does not toggle.

⚫ However, the AND gate delays the clock, potentially introducing

clock skew.
 Module 3- Circuit Design of Latches and FF

Static Sequencing Element Methodology

⚫ Flip-flops, pulsed latches, and transparent latches offer trade-offs in
sequencing overhead, skew tolerance, and simplicity.
⚫ Flip-flops
⚫ They have high sequencing overhead.

⚫ Yet they are so simple

⚫ Most ASIC methodologies use flip-flops exclusively for pipelines

and state machines.

⚫ Pulsed Latches
⚫ They are faster than flip-flops and offer some time-borrowing

capability at the expense of greater hold time.

⚫ Transparent Latches
⚫ have lower sequencing overhead than flip-flops.

⚫ Permits nearly half a cycle of time borrowing.

 Module 3- Static Sequencing Methodology

Static Sequencing Element Methodology

⚫ State Retention Registers.
⚫ State retention registers receive a second power supply to hold their
state while the rest of the unit is powered down (or power gated).

⚫ The unit must either reinitialize itself when power is reapplied or

must maintain its state during power down.

⚫ State retention registers require special design

⚫ to achieve low leakage

⚫ By using high VT transistors or thick oxide transistors.

⚫ to prevent corruption when their inputs become invalid.

 Module 3- Static Sequencing Methodology

Static Sequencing Element Methodology

⚫ State Retention Registers.
⚫ Fig. shows a flip-flop with a
balloon circuit for state
retention

⚫ The cross-coupled inverters

in the balloon circuit use
low-leakage transistors
connected to a separate
power supply to hold state
while the power is gated to
the remainder of the flip-
flop
 Module 3- Static Sequencing Methodology

Static Sequencing Element Methodology

⚫ State Retention Registers.
⚫ The balloon circuit typically
uses minimum-sized high-Vt
and/or thick oxide
transistors to minimize
leakage

⚫ The control signals

SAMPLE (S) and HOLD
(H) are 0 during normal
operation, as shown. When
the unit is about to be
power-gated, ϕ stops low
with the slave latch opaque
 Module 3- Static Sequencing Methodology

Static Sequencing Element Methodology

⚫ State Retention Registers.
⚫ SAMPLE is pulsed for long enough to write the state into the
balloon
⚫ Then HOLD is asserted to retain the state.
⚫ Now, the virtual power rail can be deactivated to power down the
unit.
⚫ Even if the clock or other latch control signals such as reset or data
toggle during power down, the copy of the state will be safely
stored in the balloon
⚫ When the unit powers back up, SAMPLE is pulsed again to copy
the state from the balloon back to the slave latch.
⚫ Then HOLD is deasserted and finally the unit can restart ϕ and
resume normal operation.
 Module 3- Synchronizer

Synchronizer
⚫ Need for Synchronizers.
⚫ If the data changes during the aperture between the setup and hold
times, the output may be unpredictable and the time for the output
to settle to a good logic level may be unbounded.
⚫ However, many interesting systems must interface with data
coming from sources that are not synchronized to the same clock.

⚫ A synchronizer is a circuit that accepts an input that can change at

arbitrary times and produces an output aligned to the synchronizer’s
clock.
⚫ Because the input can change during the synchronizer’s aperture,
the synchronizer has a nonzero probability of producing a
metastable output.
 Module 3- Synchronizer

Synchronizer
⚫ Metastability.
⚫ A latch is a bistable device; i.e., it has two stable states (0 and 1).
Under the right conditions, that latch can enter a metastable state in
which the output is at an indeterminate level between 0 and 1.
⚫ Because A = B when the latch is opaque, the stable states are A = B
= 0 and A = B = VDD . The metastable state is A = B = Vm, where
Vm is an invalid logic level. This point is called metastable because
the voltages are self-consistent and can remain there indefinitely.
 Module 3- Synchronizer

Synchronizer
⚫ Metastability.
⚫ A latch is a bistable device; i.e., it has two stable states (0 and 1).
Under the right conditions, that latch can enter a metastable state in
which the output is at an indeterminate level between 0 and 1.
 Module 3- Synchronizer

Synchronizer
⚫ A simple Synchronizer.
⚫ A synchronizer accepts an input D and a clock ϕ. It produces an
output Q that ought to be valid some bounded delay after the clock.
The synchronizer has an aperture defined by a setup and hold time
around the rising edge of the clock

⚫ If the data is stable during the aperture, Q should equal D. If the

data changes during the aperture, Q can be chosen arbitrarily.

⚫ Unfortunately, it is impossible to build a perfect synchronizer

because the duration of metastability can be unbounded
 Module 3- Synchronizer

Synchronizer
⚫ A simple Synchronizer.
⚫ Fig. shows a simple synchronizer built from a pair flip-flops. F1
samples the asynchronous input D.
⚫ The output X may be metastable for some time, but will settle to a
good level with high probability if we wait long enough.
 Module 3- Synchronizer

Synchronizer
⚫ A simple Synchronizer.
⚫ F2 samples X and produces an output Q that should be a valid logic level
and be aligned with the clock.
⚫ The synchronizer has a latency of one clock cycle, Tc . It can fail if X has
not settled to a valid level by a setup time before the second clock edge.
⚫ If the synchronizer receives an average of N asynchronous input changes
at D each second, the probability of synchronizer failure in any given
second is
 Module 3- Synchronizer

Synchronizer
⚫ A simple Synchronizer.
⚫ If the synchronizer receives an average of N asynchronous input changes
at D each second, the probability of synchronizer failure in any given
second is

⚫ and the mean time between failures increases exponentially with cycle
time
 Module 3- Synchronizer

Synchronizer
⚫ Example: A particular synchronizer flip-flop in a 0.25 𝜇 m process has 𝜏s
= 20 ps and T0 = 15 ps. Assuming the input toggles at N = 50 MHz and
the setup time is negligible, what is the minimum clock period Tc for
which the MTBF exceeds one year?
 Module 3- Synchronizer

Synchronizer
Example: For each of the following sequencing styles, determine the
maximum logic propagation delay available within a 500 ps clock cycle.
Assume there is zero clock skew.
a) Flip-flops
b) Two-phase transparent latches