Digital System Design – EC661

[Link] - VLSI SYSTEMS

Dr. SRINIVASULU JOGI

Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHONOLOGY TIRUCHIRAPPALLI
TIRUCHIRAPPALLI-620015
 Digital System Design-EC661

Course Content
⚫ Mapping algorithms into Architectures: Data path synthesis, control structures,
critical path and worst case timing analysis. FSM and Hazards.

⚫ Combinational network delay. Power and energy optimization in combinational

logic circuit. Sequential machine design styles. Rules for clocking. Performance
analysis.

⚫ Sequencing static circuits. Circuit design of latches and flip-flops. Static

sequencing element methodology. Sequencing dynamic circuits. Synchronizers.

⚫ Data path and array subsystems: Addition / Subtraction, Comparators, counters,

coding, multiplication and division. SRAM, DRAM, ROM, serial access memory,
context addressable memory.

⚫ Reconfigurable Computing- Fine grain and Coarse grain architectures,

Configuration architectures-Single context, Multi context, partially
reconfigurable, Pipeline reconfigurable, Block Configurable, Parallel processing.
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Content
 Digital System Design-EC661

Course Assessment Methodology

 Module 4-Data Path and Array Subsystems

Introduction

⚫ CMOS system design consists of partitioning the system into

subsystems
⚫ Chip functions generally can be divided into the following
categories:
⚫ Datapath operators

⚫ Memory elements

⚫ Control structures

⚫ Special-purpose cells

⚫ Many options exist that make trade-offs between speed, density

programmability, ease of design, and other variables
 Module 4-Data Path and Array Subsystems

Data Path Subsystems:

⚫ A data path is a set of functional units that carry out data processing
operations.
⚫ Datapaths, along with a control unit, make up the CPU (central

processing unit) of a computer system.

⚫ Common datapath operations considered are:

⚫ Addition / Subtraction

⚫ Comparators,

⚫ Counters,

⚫ Coding,

⚫ Multiplication.
 Module 4-Data Path and Array Subsystems

Implementation of boolean expressions with

CMOS -2-input gate
 Module 4-Data Path and Array Subsystems

Data Path Subsystems-Addition

⚫ Addition forms the basis for many processing operations, from
ALUs to address generation to multiplication to filtering.

⚫ As a result, adder circuits that add two binary numbers are of great
interest to digital system designers

⚫ An extensive, almost endless, assortment of adder architectures

serve different speed/power/area requirements.
 Module 4-Data Path and Array Subsystems

Data Path Subsystems-Single bit Addition

⚫ The half adder of Fig. adds two single-bit inputs, A and B.
⚫ If multiple adders are to be cascaded, each must be able to receive
the carry-in.
⚫ Such a full adder as shown in Fig has a third input called C or Cin.
 Module 4-Data Path and Array Subsystems

Data Path Subsystems-Single bit Addition

⚫ For a full adder, it is sometimes useful to define Generate (G),
Propagate (P), and Kill (K) signals.
⚫ The adder generates a carry when Cout is true independent of Cin,
so G = A · B
 Module 4-Data Path and Array Subsystems

Data Path Subsystems-Single bit Addition

⚫
 Module 4-Data Path and Array Subsystems

Data Path Subsystems-Single bit Addition

⚫ For full adder logic

⚫ The most straightforward approach to designing an adder is with

logic gates.
⚫ The carry gate is also called a majority gate because it produces a 1
if at least two of the three inputs are 1.
 Module 4-Data Path and Array Subsystems

Full Adder-Implementation
⚫ Full Adder Implementation
 Module 4-Data Path and Array Subsystems

Full Adder-Implementation
⚫ The full adder of above fig employs 32 transistors (6 for the
inverters, 10 for the majority gate, and 16 for the 3-input XOR)

⚫ A more compact design is based on the observation that S can be

factored to reuse the Cout term as follows:

⚫ Such a design is shown below in fig and uses only 28 transistors

 Module 4-Data Path and Array Subsystems

Full Adder-Implementation
⚫ Optimized Implementation-gate level
 Module 4-Data Path and Array Subsystems

Full Adder-Implementation
⚫ Optimized Implementation-Transistor level
 Module 4-Data Path and Array Subsystems

Full Adder-Implementation
⚫ Optimized Implementation-Transistor level
⚫ A more compact design is based on the observation that S can be
factored to reuse the Cout term.
⚫ This uses 28 transistors.
⚫ Note that the pMOS network is identical to the nMOS network
⚫ So the topology is called a mirror adder
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder

⚫ An N-bit adder can be constructed by cascading N full adders, as
shown in fig.
⚫ This is called a carry-ripple adder (or ripple-carry adder)
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder

⚫ An inverting full adder receiving complementary inputs produces
true outputs.
⚫ Fig. shows a carry ripple adder built from inverting full adders
⚫ Every other stage operates on complementary data
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ We can generalize these signals to describe whether a group
spanning bits i...j, inclusive, generate a carry or propagate a carry.
⚫ A group of bits generates a carry if its carry-out is true independent
of the carry in; it propagates a carry if its carry-out is true when
there is a carry-in.
⚫
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ Carry Generate and Propagate (for 1-stage RCA)
⚫
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ Carry Generate and Propagate (2-stage RCA)
⚫
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ We can generalize these signals to describe whether a group
spanning bits i...j, inclusive, generate a carry or propagate a carry.
⚫ A group of bits generates a carry if its carry-out is true independent
of the carry in; it propagates a carry if its carry-out is true when
there is a carry-in.
⚫
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ In other words, a group generates a carry if the upper (more
significant) or the lower portion generates and the upper portion
propagates that carry.
⚫ The group propagates a carry if both the upper and lower portions
propagate the carry
⚫ The carry-in must be treated specially. Let us define C0 = Cin and
CN = Cout. Then we can define generate and propagate signals for
bit 0 as
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ Observe that the carry into bit i is the carry-out of bit i–1 and is Ci–1
= Gi–1:0.
⚫ This is an important relationship; group generate signals and carries
will be used synonymously in the subsequent sections. We can thus
compute the sum for bit i using
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ Hence, addition can be reduced to a three-step process:
⚫ Computing bitwise generate and propagate signals using

⚫ Combining PG signals to determine group generates Gi–1:0 for all

N >=i >= 1 using

⚫ Calculating the sums using

 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ These steps are illustrated in Fig.
 Module 4-Data Path and Array Subsystems

Carry Ripple Adder-Generate and propagate

⚫ These steps are illustrated in Fig.
 Module 4-Data Path and Array Subsystems

Full Adder-Implementation

Assignment
(a)Implement a full adder with PTL logic and
Transmission gate logic and submit the report.
(b) Implement carry look ahead/carry skip
adder.
 Module 4-Data Path and Array Subsystems

Subtraction
⚫ An N-bit subtracter uses the two’s complement relationship.
⚫ This involves inverting one operand to an N-bit CPA and adding 1
via the carry input, as shown.
⚫ An adder/subtracter uses XOR gates to conditionally invert B,
 Module 4-Data Path and Array Subsystems

Subtraction
⚫ An N-bit subtracter uses the two’s complement relationship.
⚫ This involves inverting one operand to an N-bit CPA and adding 1
via the carry input, as shown.
⚫ An adder/subtracter uses XOR gates to conditionally invert B,
 Module 4-Data Path and Array Subsystems

One/Zero detectors
⚫ Detecting all ones or zeros on wide N-bit words requires large fan-
in AND or NOR gates.
⚫ One can build a tree of AND gates, as shown. Here, alternate
NAND and NOR gates have been used. The path has log N stages.
 Module 4-Data Path and Array Subsystems

One/Zero detectors
⚫ If the word being checked has a natural skew in the arrival time of
the bits the designer might consider an asymmetric design that
favors the late-arriving inputs, as shown
⚫ Another fast detector uses a pseudo-nMOS or dynamic NOR
structure to perform the “wired-OR,” as shown
 Module 4-Data Path and Array Subsystems

Comparators-Magnitude comparator
⚫ A magnitude comparator determines the larger of two binary
number
⚫ To compare two unsigned numbers A and B, compute

⚫ Figure shows a 4-bit unsigned comparator

⚫ built from a carry-ripple adder and
⚫ two’s complementer.
⚫ The relative magnitude is determined from
⚫ the carry-out (C) and zero (Z) signals
⚫ according to Table
 Module 4-Data Path and Array Subsystems

Comparators-Equality comparator
⚫ An equality comparator determines if (A = B). This can be done
more simply and rapidly with XNOR gates and a ones detector, as
shown
⚫
 Module 4-Data Path and Array Subsystems

Counters-
⚫ An N-bit binary counter sequences through 2N outputs in binary
order.
⚫ Simple designs have a minimum cycle time that increases with N,
but faster designs operate in constant time.
⚫ Some of the common features of counters include the following
⚫
 Module 4-Data Path and Array Subsystems

Counters-Binary Counters
⚫ The simplest binary counter is the asynchronous ripple-carry
counter, as shown in fig.
⚫ It is composed of N registers connected in toggle configuration,
where the falling transition of each register clocks the subsequent
register
⚫ Therefore, the delay can be quite long.
⚫ It has no reset signal, making it difficult
⚫ to test.
⚫ In general, asynchronous circuits
⚫ introduce a whole assortment of
⚫ problems
 Module 4-Data Path and Array Subsystems

Counters-Binary Counters
⚫ A general synchronous up/down counter is shown in Fig. a
⚫ It uses a resettable register and full adder for each bit position.
⚫ The cycle time is limited
⚫ by the ripple-carry delay.
⚫ If only an up counter
⚫ (also called an incrementer)
⚫ is required, the full adder
⚫ degenerates into a
⚫ half adder, as shown in Fig. b
 Module 4-Data Path and Array Subsystems

Counters-Binary Counters
⚫ A general synchronous up/down counter is shown in Fig. a
⚫ It uses a resettable register and full adder for each bit position.
⚫ The cycle time is limited by the ripple-carry delay.
 Module 4-Data Path and Array Subsystems

Counters-Ring and Johnson Counters

⚫ A ring counter consists of an M-bit shift register with the output fed
back to the input, as shown in Fig. a
⚫ On reset, the first bit is initialized to 1 and the others are initialized
to 0. TC toggles once every M cycles.
⚫ Ring counters are a convenient way to build extremely fast
prescalars because there is no logic between flip-flops, but they
become costly for larger M.
 Module 4-Data Path and Array Subsystems

Counters-Ring and Johnson Counters

⚫ A Johnson or Mobius counter is similar to a ring counter, but
inverts the output before it is fed back to the input, as shown in
Fig.b
⚫ The flip-flops are reset to all zeros and count through 2M states
before repeating.
⚫ Table shows the sequence for a 3-bit Johnson counter.
 Module 4-Data Path and Array Subsystems

Multipliers-
⚫ Multiplication is less common than addition, but is still essential for
microprocessors, digital signal processors, and graphics engines
⚫ The most basic form of multiplication consists of forming the
product of two unsigned (positive) binary numbers.
⚫ M × N-bit multiplication P = Y × X can be viewed as forming N
partial products products of M bits each, and then summing the
appropriately shifted partial products to produce an M + N-bit result
P
 Module 4-Data Path and Array Subsystems

Multipliers-Hardware implementation
⚫
 Module 4-Data Path and Array Subsystems

Multipliers-Hardware implementation
⚫
 Module 4-Data Path and Array Subsystems

Multipliers-Hardware implementation
⚫
 Module 4-Data Path and Array Subsystems

Multipliers-Hardware implementation
⚫
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory arrays often account for the majority of transistors in a
CMOS system-on-chip.
⚫ Arrays may be divided into categories as shown
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory arrays
⚫ SRAM

⚫ DRAM

⚫ ROM

⚫ Serial access memory

⚫ Content addressable memory

 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory arrays
⚫ Random access memory is accessed with an address and has a

latency independent of the address.

⚫ – In contrast, serial access memories are accessed sequentially so

no address is necessary.
⚫ Content addressable memories determine which address(es)
contain data that matches a specified key.
⚫ Random access memory is commonly classified as – read-only

memory (ROM) or – read/write memory (confusingly called

RAM).
⚫ Even the term ROM is misleading because many ROMs can be

written as well.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory arrays
⚫ A more useful classification is volatile vs. nonvolatile memory.

⚫ – Volatile memory retains its data as long as power is applied

⚫ Eg read/write memory (so called RAM)

⚫ – While nonvolatile memory will hold data indefinitely.

⚫ ROM
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Volatile Memory
⚫ Static

⚫ Dynamic

⚫ Static cells use some form of feedback to maintain their state.

⚫ Dynamic cells use charge stored on a floating capacitor through an
access transistor.
⚫ Charge will leak away through the access transistor even while

the transistor is OFF, so dynamic cells must be periodically read

and rewritten to refresh their state.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Non-Volatile Memory

⚫ The contents of a mask ROM are hardwired during fabrication and

cannot be changed
⚫ A programmable ROM (PROM) can be programmed once after
fabrication by blowing on-chip fuses with a special high
programming voltage.
⚫ An erasable programmable ROM (EPROM) is programmed by
storing charge on a floating gate.
⚫ It can be erased by exposure to ultraviolet (UV) light for several

minutes to knock the charge off the gate.

⚫ Then the EPROM can be reprogrammed.

⚫ Electrically erasable programmable ROMs (EEPROMs) are similar,

but can be erased in microseconds with on-chip circuitry.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Non-Volatile Memory

⚫ Flash memories are a variant of EEPROM that erases entire blocks

rather than individual bits.
⚫ – Flash memories are widely used.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ Memory cells can have one or more ports for access.

⚫ On a read/write memory, each port can be read-only, write-only, or
capable of both read and write.
⚫ A memory array contains 2n words of 2m bits each.
⚫ Each bit is stored in a memory cell.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ Memory cells can have one or more ports for access.

⚫ On a read/write memory, each port can be read-only, write-only, or
capable of both read and write.
⚫ A memory array contains 2n words of 2m bits each.
⚫ Each bit is stored in a memory cell.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ Memory cells can have one or more ports for access.

⚫ On a read/write memory, each port can be read-only, write-only, or
capable of both read and write.
⚫ A memory array contains 2n words of 2m bits each.
⚫ Each bit is stored in a memory cell.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays
⚫ Fig. shows the organization of a
small memory array containing 16
4-bit words (n = 4, m = 2).
⚫ The simplest design with one row
per word and one column per bit.
⚫ The row decoder uses the address to
activate one of the rows by asserting
the wordline.
⚫ During a read operation, the cells on
this wordline drive the bitlines,
which may have been conditioned
to a known value in advance of the
memory access
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ The column circuitry may contain

amplifiers or buffers to sense the
data.
⚫ A typical memory array may have
thousands or millions of words of
only 8–64 bits each, which would
lead to a tall, skinny layout that is
hard to fit in the chip floorplan and
slow because of the long vertical
wires.
⚫ Therefore, the array is often folded
into fewer rows of more columns.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ After folding, each row of the

memory contains 2k words, so
the array is physically organized
as 2n – k rows of 2m + k columns or
bits.
⚫ Fig shows a two-way fold (k = 1)
with eight rows and eight
columns
⚫ The column decoder controls a
multiplexer in the column
circuitry to select 2m bits from
the row as the data to access.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays

⚫ Larger memories are generally

built from multiple smaller
subarrays so that the wordlines
and bitlines remain reasonably
short, fast, and low in power
dissipation.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays-SRAM

⚫ SRAM - the most widely used form of on-chip memory

⚫ Static RAMs use a memory cell with internal feedback that retains
its value as long as power is applied.
⚫ A SRAM cell needs to be able to read and write data and to hold the
data as long as the power is applied.
⚫ An ordinary flip-flop could accomplish this requirement, but the
size is quite large.
⚫ Advantages of SRAM:
⚫ – Denser than flip-flops

⚫ – Compatible with standard CMOS processes

⚫ – Faster than DRAM

⚫ – Easier to use than DRAM

 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays-SRAM

⚫ The SRAM consists of an array of memory cells along with the row
and column circuitry.
⚫ It requires six transistors per bit.
⚫ The two additional pass transistors M5 and M6 are called access
transistors.
⚫ They serve to control the access to a storage cell during the read

and write operations.

 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays-SRAM

⚫ The 6T-SRAM is shown .

⚫ It requires six transistors per bit.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- SRAM- Read Operation

⚫ To read 1: i.e. Stored values are Q = 1 and Q_bar = 0

⚫ Initially both the bit lines are precharged to VDD.
⚫ During read operation, the value stored in Q and Q_bar are
transferred to the bit lines.
⚫ – BL remains high while BL_bar discharges towards gnd.

⚫ – The difference between BL and BL_bar is sensed by sense

amplifier and the correct logic is inferred.

⚫ A careful sizing of transistor is necessary as otherwise Q_bar is
pulled up towards the precharge value of BL_bar. This may flip the
cell in worst case. This malfunction is called read upset.
⚫ To avoid this problem, width of M1 > M5.

⚫ Similar procedure can be followed to read 0.

 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- SRAM- Read Operation

⚫
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- SRAM- write
Operation
⚫ Initially let Q = 1, Q_bar = 0
⚫ To write 0: i.e. we want to make Q
= 0, Q_bar = 1
⚫ New value cannot be written
through M5 due to sizing
constraint imposed by read
stability. (i.e width of M1 > M5)
⚫ So new value must be written
through M6.
⚫ A "0" is written in the cell by
setting BL = 0 and BL_bar = 1.
For this write operation to happen,
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays-DRAM-1T DRAM
⚫ Dynamic RAMs (DRAMs) store their contents as charge on a
capacitor rather than in a feedback loop.
⚫ Needs refresh (every 1 to 4 ms) otherwise charge gets leaked.
⚫ Refresh operation consists of reading the cell contents followed by
a write operation.
⚫ Though DRAM has simple structure, the reduction in cell
complexity is compensated more by the added system complexity
imposed by refresh requirement.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM- Read
Operation-1T DRAM
⚫ A 1-transistor (1T) dynamic RAM
cell consists of a transistor and a
capacitor
⚫ Like SRAM, the cell is accessed
by asserting the wordline to
connect the capacitor to the bitline
⚫ On a read, the bitline is first
precharged to VDD / 2.
⚫ When the wordline rises, the
capacitor shares its charge with the
bitline, causing a voltage change
that can be sensed.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM- write
Operation-1T DRAM
⚫ The read disturbs the cell contents
at x, so the cell must be rewritten
after each read.
⚫ On a write, the bitline is driven
high or low and the voltage is
forced onto the capacitor. Some
DRAMs drive the wordline to
VDDP = VDD + Vt to avoid a
degraded level when writing a ‘1.’
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM- write
Operation-3T DRAM
⚫ Write operation:
⚫ (WWL – Write-word line; RWL –
read-word line)
⚫ Set WWL = 1;
⚫ BL1 = Data to be written.
⚫ BL1 = 0 => Cs is discharged to
ground. (i.e. 0 is written)
⚫ BL1 = 1 => Cs is charged to logic
1.
⚫ Data is retained once the WWL is
lowered because node X becomes
high impedance.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM- Read
Operation-3T DRAM
⚫ Read operation:
⚫ (WWL – Write-word line; RWL –
read-word line)
⚫ Let BL2 is precharged to VDD
and let X = 1.
⚫ If RWL = 1, BL2 is pulled low
through series connection of M3
and M2.
⚫ If X = 0, BL2 remains at VDD.
⚫ So the inverse value of the stored
signal is sensed on the bit line i.e.
cell is inverting.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM- Read
Operation-3T DRAM
⚫ Read operation:
⚫ (WWL – Write-word line; RWL –
read-word line)
⚫ Hence for refresh operation, read
stored data and put its inverse on
BL1 and assert WWL.
⚫
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM-
Properties of 3T DRAM
⚫ DRAM is independent of device
sizes/ratios. (SRAM is rationed)
⚫ In contrast to other DRAM cells,
reading is non-destructive i.e.
stored value is not affected by
read.
⚫ No special process steps are
needed. The stored capacitance is
just the gate capacitance of the
readout device.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- DRAM-
Properties of 3T DRAM
⚫ Writing 1 on X equals VWWL -
VTN. This reduces current drive of
M2 during read operation, which
then increases read access time.
⚫ Solution : Raise VWWL to a value
higher than VDD
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories

⚫ Using the basic SRAM cell and/or registers, we can construct a

variety of serial access memories including shift registers and
queues.
⚫ These memories avoid the need for external logic to track addresses
for reading or writing.
⚫ Shift register
⚫ Queues
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories

⚫ Shift register
⚫ Examples

– Serial In Parallel Out (SIPO) memory.

– Parallel In Serial Out (PISO) memory.
⚫ These are also often useful in signal processing and
communications systems.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories
⚫ Shift register
⚫ A shift register is commonly used in signal processing applications
to store and delay data. A shift register is commonly used in signal
processing applications to store and delay data.
⚫ Example: a simple 4-stage 8-bit shift register constructed from 32
flip-flops
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access
Memories
⚫ Shift register
⚫ As there is no logic between the registers,
particular care must be taken that hold
times are satisfied.
⚫ Flip-flops are rather big, so large, dense
shift registers use dual-port RAMs instead
⚫ The RAM is configured as a circular
buffer with a pair of counters specifying
where the data is read and written
⚫ The read counter is initialized to the first
entry and the write counter to the last
entry on reset, as shown
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories

⚫ Queues
⚫ FIFO and LIFO
⚫ Queues allow data to be read and written at different rates.
⚫ The read and write operations each are controlled by their own
clocks that may be asynchronous.
⚫ The queue internally maintains read and write pointers indicating
which data should be accessed next.
⚫ FIFO
⚫ First in First out queue. Used to buffer data between two
asynchronous streams.
⚫ The FIFO is organized as a circular buffer.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories
⚫ FIFO
⚫ On reset, the read and write pointers are both initialized to the first
element and the FIFO is EMPTY
⚫ On a write, the write pointer advances to the next element.
⚫ – If it is about to catch the read pointer, the FIFO is FULL.

⚫ On a read, the read pointer advances to the next element. If it

catches the write pointer, the FIFO is EMPTY again.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Serial Access Memories
⚫ LIFO
⚫ Last In First Out queues (also called stack)
⚫ used in applications such as subroutine or interrupt stacks in

microcontrollers.
⚫ The LIFO uses a single pointer for both read and write.
⚫ On reset, the pointer is initialized to the first element and the LIFO
is EMPTY.
⚫ On a write, the pointer is incremented.
⚫ – If it reaches the last element, the LIFO is FULL.

⚫ On a read, the pointer is decremented.

⚫ If it reaches the first element, the LIFO is EMPTY again.
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Content Addressable Memory-CAM

⚫ The CAM acts as an ordinary SRAM that can be read or written

given adr and data, but also performs matching operations.
⚫ Matching asserts a match-line output for each word of the CAM
that contains a specified key.
⚫ A common application of CAMs is translation look aside buffers
(TLBs) in microprocessors supporting virtual memory.
⚫ The virtual address is given as the key to the TLB CAM.
⚫ If this address is in the CAM, the corresponding match line is
asserted. This match line can serve as the wordline to access a
RAM containing the associated physical address
 Module 4-Data Path and Array Subsystems

Array Subsystems-
⚫ Memory Arrays- Content Addressable Memory-CAM

⚫ The CAM acts as an ordinary SRAM that can be read or written

given adr and data, but also performs matching operations.
⚫
 Module 4-Data Path and Array Subsystems

Array Subsystems-
Memory Arrays- Content Addressable
Memory-CAM
⚫ 10T CAM

⚫ 10T CAM cell consisting of a normal

SRAM cell with additional transistors to

perform the match.
⚫ Multiple CAM cells in the same word are

tied to the same matchline.

⚫ The matchline is either precharged or

pulled high as a distributed pseudo-nMOS

gate.
⚫ Key to be matched is made available in

the bit lines in true (bit) and complement

form (bit_b).
 Module 4-Data Path and Array Subsystems

Array Subsystems-
Memory Arrays- Content Addressable
Memory-CAM
⚫ 10T CAM

⚫ Only if all of the key bits match all of the

bits stored in the word of memory will the

match-line for that word remain high.
⚫ The key can contain a “don’t care” by

setting both bit and bit_b low.