Total No. of Questions : 8] SEAT No.

7
23
PD-4063

ic-
[Total No. of Pages : 3

tat
[6402]-22

9s
5:5
S.E.

02 91
9:3
(Electronics/E&TC/Electronics (VLSI & Design &

0
50
Technology) Electronics & Communication Advanced
5/0 13
Communication Technology)
0
5/2
.23 GP

ELECTRONIC CIRCUITS
(204181) (2019 Pattern) (Semester - III)
E
71

7
C

23
Time : 2½ Hours] [Max. Marks : 70

ic-
Instructions to the candidate:
16

tat
1) Answer Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.
8.2

9s
2) Neat diagrams must be drawn wherever necessary.
.24

5:5
91
3) Figures to the right side indicate full marks.
49

9:3
4) Use of Calculator is allowed.
30
50

5) Assume Suitable data if necessary

01
02
5/2

Q1) a) Enlist the advantages and disadvantages of SMPS over linear power
GP

supply. Draw the block diagram of SMPS and explain each block in
5/0

detail. [8]
CE
71

7
23
.23

ic-
b) Design an adjustable voltage regulator using LM317 for output voltage
16

5 V to 15 V and draw necessary connection diagrams. Assume R1=240  ,

tat
8.2

1adj=100  A.
9s

[9]
.24

5:5
91
49

OR
9:3
30
50

Q2) a) Draw the block diagram of a regulated DC power supply and explain the
01
02

function of each block in detail. [9]

5/2
GP
5/0

b) Explain the following performance parameters of DC power supply [8]

CE
71

i) Load regulation ii) Line regulation,

.23
16

iii) Ripple rejection and iv) Efficiency.

8.2

P.T.O.
.24
49
 7
23
ic-
Q3) a) Explain the following op-amp parameters: [8]

tat
9s
i) Input offset Voltage

5:5
02 91
ii) CMRR

9:3
0
50
iii) 5/0 13
Slew Rate
0
5/2
iv) Unity gain bandwidth.
.23 GP

b) What is current minor circuit? Draw and explain working of differential

E
71

7
amplifier with current mirror circuit. Why current mirror circuit is used in
C

23
Op Amp? [6]

ic-
16

tat
c) State the values of all ideal parameters of Op Amp. [3]
8.2

9s
.24

5:5
OR
91
49

9:3
30

Q4) a) Draw block diagram of Op-Amp. Explain the functions of each block in
50

detail. [8]
01
02
5/2
GP

b) A dual input, balanced output(DIBO) differential amplifier has following

specifications: RC1=RC2=2.2 k  , RE= 4.7 k  , Rin1 = Rin2=50  , + Vcc=
5/0
CE

10V, -VEE = –10V,  dc =  ac =100 and VBE = 0.7 V.

71

[6]

7
23
.23

Calculate : i) IC ii) VCEQ

ic-
iii) Voltage gain : Ad
16

tat
iv) Input and output resistance
8.2

9s
.24

5:5

c) Explain how to improve CMMR in Op Amp. [3]

91
49

9:3

Q5) a) What are the limitations of ideal integrator? How these are overcome in
30
50

practical integrator? Draw the circuit diagram of practical integrator and

01
02

its frequency response. Write equation for output voltage Vo and explain
5/2
GP

its operation. [9]

5/0

b) Draw an inverting summing amplifier with three inputs. Derive an

CE
71

expression for its output voltage. [6]

.23
16

c) Draw square wave generator using Op Amp with relevant waveforms[3]

8.2
.24

[6402]-22 2
49
 OR

7
23
Q6) a) Explain with a neat circuit diagram, working of inverting symmetric Schmitt

ic-
trigger with its input output waveform and hysteresis plot. [9]

tat
9s
b) Enlist the requirements of instrumentation amplifier. Draw and explain

5:5
instrumentation amplifier using three Op Amp. [6]

02 91
9:3
0
50
c) Draw full wave precision rectifier with relevant waveforms. [3]
5/0 13
0
Q7) a) Draw circuit diagram and explain successive approximation ADC. [6]
5/2
.23 GP

b) Explain the following characteristics of DAC [6]

E
71

7
C

23
i) Resolution, ii) Accuracy and iii) Settling time.

ic-
16

tat
8.2

c) Draw the block diagram of PLL and explain each block in detail. [6]

9s
.24

5:5
91
OR
49

9:3
30
50

Q8) a) Draw and explain circuit diagram for 3- bit weighted resistor D/A converter,
01
02

and give output voltage equation for the same. [6]

5/2
GP

b) Calculate the output frequency fO, lock range and capture range of PLL if
5/0

RT = 10 k  ,CT (Timing capacitor) = 0.01  F, CF (Filter capacitor) 10

CE
71

7
 F, R (Internal filter resistor) 3.6k  .

23
[6]
.23

ic-
16

tat
c) Draw and explain the block diagram of frequency multiplier with relevant
8.2

9s

output waveforms. [6]

.24

5:5
91
49

9:3
30
50

  
01
02
5/2
GP
5/0
CE
71
.23
16
8.2
.24

[6402]-22 3
49
Total No. of Questions : 8] SEAT No. :

8
23
PB3621 [Total No. of Pages : 2
[6261]-26

ic-
tat
S.E. (Electronics /E&TC)

0s
ELECTRONIC CIRCUITS

1:4
(2019 Pattern) (Semester-III) (204181)

02 91
4:2
0
Time : 2½ Hours] [Max. Marks : 70

41
7/0 13
Instructions to the candidates:
0
1) Attempt Q1 or Q2, Q3 or Q4, Q5 or Q6, Q7 or Q8.
5/2
.23 GP

2) Figures to the right indicate full marks.

3) Assume suitable data if necessary.
E
81

4) Neat diagrams must be drawn wherever necessary.

8
C

23
ic-
Q1) a) Define Voltage regulation. Explain the any three performance parameters
16

tat
of voltage regulator. [6]
8.2

0s
.24

b) IC Voltage Regulator using IC 317, Calculate values of R2 for the output

1:4
91
voltage l0v to 20v, assume R1= 240  and Iadj = l00A. [6]
49

4:2
30

c) Compare Linear power supply and Switch Mode Power Supply (SMPS).
41

[6]
01
02
5/2

OR
GP
7/0

Q2) a) Draw and explain the block diagram of Power Supply. [6]
CE
81

8
23
b) IC Voltage Regulator using IC 317, Calculate values of R2 for the output
.23

voltage 5v to l0v, assume R1= 240  and Iadj = l00A. [6]

ic-
16

tat
c) Write a Short note on “Low drop out Voltage regulator”. [6]
8.2

0s
.24

1:4
91
49

4:2

Q3) a) Draw Block diagram of OP - AMP. and explain the function of each
30
41

block. [5]
01
02

b) Define the following Characteristics of OPAMP [6]

5/2
GP

i) Input offset voltage

7/0
CE

ii) Slew Rate

81
.23

iii) CMRR (Common Mode Rejection Ratio)

16

c) Compare Concept of Voltage Series and Voltage Shunt in OP AMP. [6]

8.2

OR
.24
49

P.T.O.
Q4) a) List types of differential amplifiers. Draw dual input balanced output

8
differential amplifier. [5]

23
ic-
b) State Ideal and Typical values of OP AMP parameters (IC 741). [6]

tat
c) Explain with circuit diagram necessity of level shifting in OP AMP. [6]

0s
1:4
02 91
4:2
Q5) a) Draw and explain Inverting amplifier. Draw its input and output waveforms.

0
41
7/0 13 [6]
b) Design a Practical differentiator circuit for the input signal having
0
5/2
.23 GP

maximum frequency of operation 250 Hz. [6]

c) Draw and explain Inverting Schmitt trigger circuit using OP AMP. [6]
E
81

8
C

23
OR

ic-
16

Q6) a) Compare Inverting and Non-Inverting amplifier in OP AMP. [6]

tat
8.2

0s
b) Design a Practical Integrator circuit to operate at f=4 KHz and gain equal
.24

1:4
to 4. [6]
91
49

4:2
c) Draw and explain square wave Generator using OP AMP. [6]
30
41
01
02

Q7) a) Draw and explain V to I Converter using grounded load using OP AMP.[5]
5/2
GP

b) Draw and explain the circuit of R/2R DAC using OP AMP. [6]
7/0

c) With the help of neat block diagram explain operation of PLL. [6]
CE
81

8
23
OR
.23

Q8) a) Draw and explain I to V Converter using OP AMP. ic-[5]

16

tat
8.2

0s

b) Draw and explain the circuit of binary weighted resistor DAC using OP
.24

AMP. [6]
1:4
91
49

4:2

c) Define the following specifications of ADC [6]

30
41

i) Resolution
01
02

ii) Accuracy
5/2
GP

iii) Conversion time

7/0
CE
81

eeee
.23
16
8.2
.24

[6261]-26 2
49
Total No. of Questions : 4] SEAT No. :

8
23
PC392 [6359]-512 [Total No. of Pages : 3

ic-
S.E. (ELECTRONICS / E&TC)(Electronics (VLSI Design & Tech.)

tat
6s
(Electronics & Comm.-Adv. Comm. Tech.)(Insem)

3:2
ELECTRONIC CIRCUITS

02 91
0:5
(2019 Pattern) (Semester - III) (204181)

0
Time : 1 Hour] [Max. Marks : 30

41
8/1 13
Instructions to the candidates:
1) Answer Q.1 or Q.2, Q.3 or Q.4.
0
2) Figures to the right indicate full marks.
0/2
.23 GP

3) Draw neat diagram wherever necessary.

4) Assume suitable data, if necessary.
E
80

8
C

23
ic-
Q1) a) Draw and explain transfer and drain characteristics of E-MOSFET. [5]
16

tat
b) Define Threshold Voltage, Pinch-off Voltage, Ohmic Region, Drain
8.2

6s
Resistance, Trans-conductance of E-MOSFET. [5]
.24

3:2
91
c) A common source amplifier circuit shown in the Figure [1] uses a
49

0:5
E-MOSFET with ID(ON) = 200 mA at VGS(ON) = 4 V, VT = 2V and
30
41

gm = 23 mA/V. Assume Vi = 25mV. [5]

01
02

Find,
0/2
GP

i) VGS
8/1

ii) ID
CE
80

8
23
iii) VDS
.23

ic-
16

tat
8.2

6s
.24

3:2
91
49

0:5
30
41
01
02
0/2
GP
8/1
CE
80
.23
16

OR
8.2
.24

P.T.O.
49

[6359]-512 1
Q2) a) Draw the common source E-MOSFET amplifier and explain frequency

8
23
response with diagram. [5]

ic-
tat
b) Explain any two non-ideal current-voltage characteristics of

6s
E-MOSFET. [5]

3:2
02 91
c) Determine IDQ, VDSQ VGSQ and Vs for the E-MOSFET circuit shown in

0:5
figure [2]. [5]

0
41
8/1 13
Given for E-MOSFET, VT = 3V, ID(ON) = 5mA, VGS(ON) = 6V
0
0/2
.23 GP
E
80

8
C

23
ic-
16

tat
8.2

6s
.24

3:2
91
49

0:5
30
41
01
02
0/2
GP
8/1
CE
80

8
23
Q3) a) Explain advantages of negative feedback in amplifiers. [5]
.23

ic-
16

tat
8.2

6s
.24

b) Explain effect of negative feedback on [5]

3:2
91
49

0:5

i) Input impedance
30
41
01

ii) Output impedance

02
0/2
GP

iii) Gain
8/1
CE
80

iv) Bandwidth
.23

v) Gain stability
16
8.2

c) Identify topology of feedback and determine Avf, Rif, Rof for the amplifier
.24
49

[6359]-512 2
 shown in Figure [3]. For the MOSFET, gm = 2mA/V,

8
23
rd = 40K. [5]

ic-
tat
6s
3:2
02 91
0:5
0
41
8/1 13
0
0/2
.23 GP
E
80

8
C

23
ic-
16

tat
8.2

6s
.24

3:2
OR
91
49

0:5
Q4) a) Explain MOSFET as Resistor. [5]
30
41
01
02

b) Draw circuit diagram of RC phase shift oscillator and calculate the

0/2
GP

operating frequency, if R = 10 K and C = 5nF. [5]

8/1
CE
80

8
c) Compare different types of feedback topologies with respect to different

23
.23

parameter. [5]
ic-
16

tat
8.2

6s

… … …
.24

3:2
91
49

0:5
30
41
01
02
0/2
GP
8/1
CE
80
.23
16
8.2
.24
49

[6359]-512 3
Total No. of Questions : 8] SEAT No. :

8
23
P1485 [Total No. of Pages : 2

ic-
[6002]-112

tat
S.E. (Electronics/ E&T.C)

9s
ELECTRONIC CIRCUITS.

6:1
(2019 Pattern) (Semester-III) (204181)

02 91
0:2
0
Time : 2½ Hours] [Max. Marks : 70

31
4/0 13
Instructions to the candidates:
1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
0

om
6/2
2) Figure to the right indicate full marks.
.23 GP

3) Neat diagrams must be drawn wherever necessary.

4) Assume suitable additional data, if necessory.
E
81

rsic-238
.c
5) Use of non-programmable calculator is allowed.
16
C

tat
Q1) a) Draw block diagram of regulated power supply and explain the function
8.2

es
of each block? [6]

:19
.24

:26p
b) With the help of neat diagram explain buck-boost converter? [6]
02P 91
c) Draw and explain low dropout regulator? [6]
49

0a
OR
0
31
4/0 n13

Q2) a) Design a regulated power supply using LM 317 for output voltage gv and
15v IAdj=100 uA. [6]
P0
6/2
8 1 io

b) Explain the working of SMPS with neat diagram? [6]

.23 tG

c) Compare regulated and unregulated power supply? [6]

CE
s

38
Q3) a) List all parameter’s of op-amp. Explain any four in brief ? [6]
ue

c-2
b) Explain significance of negative feed back, in op-amp amplifier? [5]
i
16

tat
c) A dualt input balanced output differential amplifier has following specifi-
Q
8.2

9s

cation Rc=2.7KΩ, RE=4.5kΩ, ± VCC= ± 10v, β=100; VBE=0.7V;

.24

6:1

re=26.34Ω calculate [6]

PU

91
49

i) Voltage gain (Ad)

0:2
30

ii) Rin
31

iii) Ro
SP

01
02

OR
6/2
GP

Q4) a) Draw block diagram of op-amp and explain each block? [6]
4/0

b) Compare inverting and non-inverting configuration of op-amp with

CE
81

following parameters:
i) Feedbock Type
.23

ii) Ri
16

iii) Gain
8.2

iv) Bandwith [5]

.24

P.T.O.
49

[6002]-112 1
 c) Determine the Q point for dual input and balanced output differential

8
amplifier with RC=RE=65KΩ and supply voltage ± 15V assume suitable

23
ic-
data. [6]

tat
9s
Q5) a) Draw an inverting summing amplifier with three input and derive expression

6:1
for the output voltage Vo= – (Va+Vb+Vc) [6]

02 91
b) Design a practical Integrator with input Signal of 1.5 vpp and cut off

0:2
frequency of 3KHz for DC voltage gain of 10. [6]

0
31
c) 4/0 13
Draw circuit diagram of 30p-amp Intrumentation amplifier and write its
o/p equation? [6]
0

om
6/2
.23 GP

OR
E

Q6) a) With the help of neat diagram explain working of symmetrical schmitt
81

rsic-238
.c
C

trigger? [6]
b) Design a square wave generater using op-amp for frequency 1KHz to 10
16

tat
KHz with 50 % duty cycle. draw diagram with component value. [6]
8.2

es
c) Explain practical differentiator circuit with neat diagram? list limitations

:19
.24

:26p
of ideal differentiator? [6]
02P 91
49

0a
0

Q7) a) Explain voltage to current converter with floating load? [6]

31
4/0 n13

b) Determine the output voltage produced by 4 bit R-2R ladder DAC with
Vret=5v for bit sequence i) 0110 ii) 1101 [5]
P0
6/2
8 1 io

c) Explain working of flash ADC in details. [6]

.23 tG

OR
CE

Q8) a) Define terms. [6]

s

38
i) Lock range
ue

c-2
ii) Capture range.
i
16

tat
iii) Pull in time
Q
8.2

9s

iv) Free running frequency.

.24

6:1

b) With the neat diagram explain working of weighted resistor DAC? [6]
PU

91
49

0:2

c) Find the digital output of an ADC having t1=83.33 Msec and VR=100
30

mv for an input voltage. of +100mV. The clock frequency is kHz [5]

31
SP

01
02
6/2
GP


4/0
CE
81
.23
16
8.2
.24
49

[6002]-112 2
Total No. of Questions : 4] SEAT No. :

8
23
P-5386 [Total No. of Pages : 3

ic-
[6186]-512

tat
0s
S.E. (Electronics/E&TC)

3:1
ELECTRONIC CIRCUITS

02 91
0:4
(2019 Pattern) (Semester - III) (204181)

0
31
0/1 13
0
Time : 1 Hour] [Max. Marks : 30

om
0/2
.23 GP

Instructions to the candidates:

1) Answer Q.1 or Q.2, Q.3 or Q.4.
E
81

rsic-238
.c
2) Figures to the right indicate full marks.
C

3) Draw neat diagram wherever necessary.

16

4) Assume suitable data, if necessary.

tat
8.2

es
:10
.24

Q1) a)
:43p
Draw & Explain drain characteristics of N-EMOSFET. Write drain
02P 91
49

current equation for the respective region? [5]

0a
0
31

b) Explain any two non-ideal current voltage characteristics of MOSFET

0/1 n13

transistor. [5]
P0
0/2

c) For the circuit diagram shown in Figure [1], calculate VDS, ID & VGS.
8 1 io
.23 tG

Assume : R1 = 10 M, R2 = 3.6 M, RD = 10K, Kn = 0.5 mA/V2,

CE
s

38
VTN = 1.5 V. [5]
ue

c-2
i
16

tat
Q
8.2

0s
.24

3:1
PU

91
49

0:4
30
31
SP

01
02
0/2
GP

Figure [1]
0/1

OR
CE
81

Q2) a) Draw the common source E-MOSFET amplifier and explain frequency
.23

response with diagram. [5]

16

b) Explain construction and working of N-Type Enhancement MOSFET

8.2

in details. [5]
.24
49

P.T.O.
 c) For the circuit shown in Figure [2]. Calculate IDQ, VDSQ and VD.

8
Assume : R 1 = 22 M, R D = 3 K, R 2 = 18 M, V TN = 3 V,

23
RS = 0.82 K, Kn = 0.12 mA/V2, VGS = 10.48 V. [5]

ic-
tat
0s
3:1
02 91
0:4
0
31
0/1 13
0

om
0/2
.23 GP
E
81

rsic-238
.c
C

Figure [2]
16

tat
8.2

es
Q3) a) Explain advantages of negative feedback in amplifiers. [5]

:10
.24

:43p
02P 91
b) Explain effect of negative feedback on : [5]
49

0a
0

i) Input impedance
31
0/1 n13

ii) Output impedance

P0
0/2
8 1 io

iii) Gain
.23 tG
CE

iv) Bandwidth
s

38
ue

c-2
v) Gain stability
i
16

tat
c) Identify topology of feedback and determine AVf, Rif, Rof for the
Q
8.2

0s

amplifier shown in Figure [3]. For the MOSFET gm = 2mA/V,

.24

3:1

rd = 40 K. [5]
PU

91
49

0:4
30
31
SP

01
02
0/2
GP
0/1
CE
81
.23
16
8.2

Figure [3]
.24
49

[6186]-512 2
 OR

8
23
Q4) a) Explain Barkhausen Criteria for sustained oscillations and draw the

ic-
circuit diagram of RC phase shift oscillator. [5]

tat
0s
b) Draw the block diagram of Current Series topology and write the

3:1
equation for Rif and Rof. [5]

02 91
0:4
c) Compare different types of feedback topologies with respect to different

0
31
parameter.0/1 13 [5]
0

om
0/2
.23 GP


E
81

rsic-238
.c
16
C

tat
8.2

es
:10
.24

:43p
02P 91
49

0a
0
31
0/1 n13
P0
0/2
8 1 io
.23 tG
CE
s

38
ue

c-2
i
16

tat
Q
8.2

0s
.24

3:1
PU

91
49

0:4
30
31
SP

01
02
0/2
GP
0/1
CE
81
.23
16
8.2
.24
49

[6186]-512 3
Total No. of Questions : 8] SEAT No. :

8
23
P9101 [Total No. of Pages : 2

ic-
[6179]-226

tat
S.E. (Electronics/E & TC)

0s
ELECTRONICS CIRCUITS

7:0
02 91
(2019 Pattern) (Semester - III) (204181)

9:3
0
30
Time : 2½ Hours] 9/1 13 [Max. Marks : 70
Instructions to the candidates:
0
2/2
.23 GP

1) Attempt Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.

2) Figures to the right indicate full marks.
E

3) Assume suitable data, if required.

82

8
C

23
4) Neat diagrams must be drawn wherever necessary.

ic-
16

tat
Q1) a) Explain the IC 317 voltage regulator with diagram and write its output
8.2

0s
voltage equation. [6]
.24

7:0
b) IC Voltage Regulator using IC 317, Calculate the variable output voltages,
91
49

9:3
assume R1 = 240 Ω, R2 = 5KΩ (pot) and Iadj = 100 uA. [6]
30
30

c) Explain concept of Switch Mode Power Supply (SMPS) and list type of
01
02

SMPS. [6]
2/2
GP

OR
9/1

Q2) a) Draw and explain the concept of Current boosting in Voltage regulator.[6]
CE
82

8
23
b) IC Voltage Regulator using IC 317, Calculate values of R2 for the output
.23

voltage 5v to 10v, assume R1 = 240 Ω and Iadj = 100 μA. [6]

ic-
16

tat
c) Write a short note on “Low drop out Voltage regulator”.
8.2

[6]
0s
.24

7:0
91
49

9:3

Q3) a) Draw block diagram of OP - AMP. And explain the function of each
30
30

block. [5]
01
02

b) Define the following characteristics of OPAMP: [6]

2/2
GP

i) Input offset voltage

9/1
CE

ii) Slew Rate

82
.23

iii) PSRR (Power Supply Rejection Ratio)

16

c) Explain the concept of Current mirror circuit. [6]

8.2

OR
.24

P.T.O.
49
Q4) a) List types of differential amplifiers. Draw dual input balanced output

8
23
differential amplifier. [5]

ic-
b) State ideal and typical values of OP AMP parameters (IC 741). [6]

tat
c) Explain with circuit diagram necessity of level shifting in OP AMP. [6]

0s
7:0
02 91
9:3
Q5) a) Draw and explain Inverting amplifier. Draw its input and output waveforms.[6]

0
30
b) Design a practical differentiator circuit for the input signal having maximum
9/1 13
frequency of operation 250 Hz. [6]
0
2/2
.23 GP

c) Draw Inverting Schmitt trigger circuit using OP AMP. Write the equation
of VUTP and VLTP. [6]
E
82

8
OR
C

23
ic-
Q6) a) Compare open loop and close loop comparator in OP AMP. [6]
16

tat
b) Design a practical Integrator circuit to operate at f = 4 KHz and gain
8.2

0s
equal to 4. [6]
.24

7:0
91
49

c) Draw and explain Instrumentation using three OP AMP. [6]

9:3
30
30
01
02

Q7) a) Draw and explain V to I Converter using grounded load using OP AMP.[5]
2/2
GP

b) Draw and explain the circuit of R/2R DAC using OP AMP. [6]
9/1

c) With the help of neat block diagram explain operation of PLL. [6]
CE
82

8
23
OR
.23

ic-
16

Q8) a) Draw and explain I to V Converter using OP AMP. [5]

tat
8.2

0s

b) Draw and explain the circuit of binary weighted resistor DAC using OP
.24

7:0

AMP. [6]
91
49

9:3

c) Define the following specifications of ADC : [6]

30
30

i) Resolution
01
02

ii) Accuracy
2/2
GP
9/1

iii) Conversion time

CE
82
.23
16


8.2
.24

[6179]-226
49

2
Total No. of Questions : 8] SEAT No. :

8
23
P620 [Total No. of Pages : 2

ic-
[5869]-242

tat
S.E. (Electronics & Telecommunication)

1s
ELECTRONIC CIRCUITS

3:5
02 91
(2019 Pattern) (Semester - III)

8:4
0
20
Time : 2½ Hours] [Max. Marks : 70
4/0 13
Instructions to the candidates:
0
6/2
1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.
.23 GP

2) Figures to the right indicate full marks.

3) Neat diagrams must be drawn whenever necessary.
E
82

8
4) Make suitable assumptions whenever necesary.
C

23
ic-
16

Q1) a) Draw the block diagram of a regulated dc power supply and explain the

tat
8.2

1s
function of each block in it. [6]
.24

3:5
b) With the help of a block diagram explain the concept of SMPS. [6]
91
49

c) Design an adjustable voltage regulator using LM317 for output voltage

8:4
30

1.25V to 15V and draw necessary connection diagrams. Assume

20

R1=240Ω, ladj=100uA. [6]

01
02

OR
6/2
GP

Q2) a) With the help of a neat diagram explain the operation of an adjustable
4/0

voltage regulator using IC LM 317. [6]

CE
82

8
b) Compare linear and switch mode power supply [6]

23
.23

c) Explain the concept of current boosting with necessary diagram. [6]

ic-
16

tat
Q3) a) An emitter biased Dual input balanced output differential amplifier has
8.2

1s

the following specifications:

.24

3:5

VC C= ±12 V, RC1=RC2=3.7kΩ and RE=4.2kΩ,

91
49

8:4

β=100 & VBE=0.7 V. Calculate:

30
20

i) Voltage Gain (Ad)

01
02

ii) Input Resistance (Ri)

6/2

iii) Output Resistance (Ro) [6]

GP
4/0

b) Define the following characteristics of OP-AMP

CE

i) input bias current

82

ii) Slew rate

.23

iii) CMRR [6]

16

c) Explain Current mirror circuit with neat diagram. [5]

8.2

OR
.24

P.T.O.
49

[5869]-242 1
Q4) a) Draw a block diagram of the op-amp and explain in detail. [6]

8
23
b) Find the Q point for a Dual input Balanced output differentail amplifier

ic-
with RC=RE=65Kohm. Supply voltage used is ±15V, VBE=0.7V. [6]

tat
c) Compare ideal & practical parameters of an Op-amp. [5]

1s
3:5
02 91
Q5) a) Draw and inverting summing amplifier with three inputs and derive

8:4
expression for its output voltageVO= – (Va+Vb+Vc). [6]

0
20
b) 4/0 13
Draw a circuit diagram of three op-amp Instrumentation amplifiers and
write its output equation. [6]
0
6/2
.23 GP

c) Design and inverting Schmitt Trigger circuit whose VUT and VLT are ±5V.
Draw input and output waveforms. Assume op-amp saturates at ±13.5V.
E
82

[6]

8
C

23
OR

ic-
16

Q6) a) Design a practical integrator with input signal of 2Vpp and cut off

tat
8.2

frequency of 2.5KHz for DC voltage gain of 10. [6]

1s
.24

3:5
b) Explain in detail the working of square wave generators with a neat circuit
91
diagram. draw waveform of output voltage and capacitor voltage. [6]
49

8:4
30

c) Explain the operation of a precision full wave rectifier with necessary

20

waveforms. [6]
01
02
6/2
GP

Q7) a) Draw block diagram and explain any one application of IC PLL 565 in
4/0

detail. [6]
CE
82

8
b) Draw circuit diagram and explain D/A converter with binary weighted

23
.23

resistors and give output voltage equation VO=? [6]

ic-
16

tat
c) With neat circuit diagram explain V to I converter. [5]
8.2

1s

OR
.24

3:5

Q8) a) For PLL IC 565 define and give expression of free running frequency,
91
49

8:4

lock range and capture range. [6]

30
20

b) Design a PLL circuit using 565 IC to get free running frequency 4.5KHz,
01
02

lock range 2 KHz and capture range 100 Hz. Assume supply voltage of
6/2

± 10V. [6]
GP
4/0

c) With neat circuit diagram explain I to V converter. [5]

CE
82
.23


16
8.2
.24
49

[5869]-242 2
Total No. of Questions : 4] SEAT No. :

8
23
PA-5 [Total No. of Pages : 2

ic-
[5931] -7

tat
0s
S.E .(E & TC)

0:2
ELECTRONIC CIRCUITS

02 91
(2019 Pattern) (Semester - I) (204181)

0:4
0
31
Time : 1 Hour]
7/0 13 [Max. Marks : 30
0
Instructions to the candidates:
1/2
.23 GP

1) Solve Q.1 or Q.2, Q.3 or Q.4.

2) Figures to the right indicate full marks.
E
81

3) Draw the neat sketch wherever necessary.

8
C

23
ic-
16

tat
Q1) a) Explain construction and working of N-Type Enhancement MOSFET in
8.2

0s
details? [5]
.24

0:2
91
b) List the non-Ideal characteristics of MOSFET? What is channel length
49

0:4
modulation. Explain in details? [5]
30
31

c) Design a common source amplifier with voltage divider bias for

01
02

ID = 1mA, VDS = 6.4V, VTN = 2.0V, VDD = 10V and Kn = 0.80 mA/V2.
1/2
GP

Assume suitable data as require. [5]

7/0
CE
81

8
23
OR
.23

ic-
16

tat
Q2) a) Using V-I characteristics, show in which regions MOSFET operates?
8.2

0s

Write drain current equation for the respective regions? [5]

.24

0:2
91
49

b) How Body effect & Temperature effect will impact on overall

0:4
30

performance of MOSFET? [5]

31
01
02

c) Determine the current ZD and O/P voltage VDS for the DC bias MOSFET
1/2
GP

circuit using voltage divider bias using parameter as, RG1= 270K ,
7/0

RG2= 240 K , RS = 3.9K , RD = 10K , VDD = 5V, Kn = 0.16mA/V2,

CE
81

VGS = 2.45V, VTN = 1.2V [5]

.23
16
8.2
.24

P.T.O.
49
Q3) a) Explain the effect of negative feedback on amplifier circuit? [5]

8
23
b) Draw block diagram of current series feedback amplifier and derive

ic-
equation of gain, Rif and Rof? [5]

tat
0s
c) Draw a RC phase shift oscillater and calculate Frequency of oscillation

0:2
for R = 8.9kohm and C = 0.1  F. [5]

02 91
0:4
0
31
7/0 13 OR
0
1/2
.23 GP

Q4) a) Calculate the value of Rif, Rof, Avf for a voltage series feedback amplifier
for given specification Ri = 1.2K , AV = 75, Ro = 7.3K ,   0.20. [5]
E
81

8
C

23
b) Compare all four types of feedback amplifier with parameter Avf,

ic-
16

bandwidth, Rif, Rof and output? [5]

tat
8.2

0s
c) What is barskhausen criteria for sustain oscillation? Explain working of
.24

0:2
91
oscillator? [5]
49

0:4
30
31
01

 
02
1/2
GP
7/0
CE
81

8
23
.23

ic-
16

tat
8.2

0s
.24

0:2
91
49

0:4
30
31
01
02
1/2
GP
7/0
CE
81
.23
16
8.2
.24

[5931]-7 2
49
Total No. of Questions : 8] SEAT No. :

8
23
PA-1190 [Total No. of Pages : 2

ic-
[5925]-212

tat
S.E. (E & TC/Electronics)

2s
ELECTRONIC & CIRCUITS

9:0
02 91
(2019 Pattern) (Semester-III) (204181)

3:3
0
31
Time : 2½ Hours] [Max. Marks : 70
6/0 13
Instructions to the candidates:
0
1) Attempt [Link].1 or [Link].2, [Link].3 or [Link].4, [Link].5 or [Link].6, [Link].7 or [Link].8.
2/2
.23 GP

2) Figures to the right indicate full marks.

3) Assume suitable data, if necessary.
E

4) Neat diagrams must be drawn wherever necessary.

80

8
C

23
ic-
Q1) a) Explain with diagram the operation of an adjustable voltage regulater
16

tat
using IC LM 317. [7]
8.2

2s
.24

b) Design the adjustable voltage regulator for the following specification

9:0
91
output voltage = 5V – 10V I0 = 1.2 A, Iadj = 100A, R1 = 240 [7]
49

3:3
30

c) What is SMPS? Explain working principle of it. [4]

31
01

OR
02
2/2

Q2) a) Draw and explain the block diagram of LM 337 and list the specification
GP
6/0

of it? [7]
CE
80

b) Determine the range of output voltage for adjustable voltage regulator

8
23
LM317 for R1 = 240, R2 = 4.7 k Assume Iadj = 100 A. [7]
.23

c) ic-
Which are the factor that affect on the output of the voltage regulator?[4]
16

tat
8.2

2s
.24

9:0

Q3) a) List different configuration of differential amplifier and explain dual input
91
49

3:3

dual output in details? [7]

30
31

b) Define the characteristics of op-amp [6]

01
02

i) Input bias current

2/2
GP

ii) Slew rate

6/0

iii) CMRR
CE
80

c) Find the ‘Q’ point for a dual input balanced output differential amplifier
.23

with RC = RE = 65 k. supply voltage used is ± 1s V. [4]

16

OR
8.2
.24

P.T.O.
49

[5925]-212 1
Q4) a) Explain the need of level shifting stage in op-amp. Explain any one circuit

8
23
for the same. [7]

ic-
b) Draw and explain voltage series feedback amplifier and list their

tat
advantages. [6]

2s
c) Explain the concept of current mirror circuit? [4]

9:0
02 91
3:3
0
Q5) a) Draw an inverting summing amplifier with three inputs and derive

31
6/0 13
expression for its output voltage Vo? [8]
0
b) Design a practical integrator with input signal of 2VPP and cutoff
2/2
.23 GP

frequency of 2.5 kHz. for DC voltage gain to 10. [6]

c) Explain with diagram the concept of voltage follower circuit using
E
80

8
op-amp. [4]
C

23
ic-
OR
16

tat
8.2

Q6) a) Draw and explain an Instrumentation amplifier interface with RTD bridge

2s
for temperature measurement. [8]
.24

9:0
91
b) Using IC 741 op-amp with supply voltage of ±15V design an inverting
49

3:3
schmitt trigger circuit to have VUTP = +3V, VLTP = –3V. [6]
30
31

c) What is the difference between inverting and non-inverting amplifier. [4]

01
02
2/2
GP
6/0

Q7) a) Classify different types of ADC and explain iwth diagram dual scope
CE

ADC. [6]
80

8
23
b) Calculate the O/P voltage for a DAC whose output range is 0 to 10 V
.23

and input binary number 1001. [6] ic-

16

tat
8.2

c) Explain various specification of ADC. [5]

2s
.24

9:0

OR
91
49

3:3

Q8) a) Explain with neat diagram the register weighted and R-2R DAC? [6]
30
31

b) For on 10 bit successive approximation type A/D converter driven by a

01
02

2MHz clock, find the conversion time? [6]

2/2
GP

c) Draw and explain V to I convertor. [5]

6/0
CE
80
.23
16


8.2
.24
49

[5925]-212 2
Total No. of Questions : 8] SEAT No. :

7
23
PD-5277 [Total No. of Pages : 2

ic-
[6402]-23R

tat
1s
S.E. (Electronics & Computer) (Electronics/E&TC)

0:3
(Electronics-VLSI Design & Technology/

02 91
9:4
Electronics & Comm.-(A.C.T.))

0
50
7/0 13
DIGITAL CIRCUITS
0
(2019 Pattern) (Semester - III) (204182)
5/2
.23 GP

Time : 2½ Hours] [Max. Marks : 70

E

Instructions to the candidates:

71

7
C

23
1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8 .

ic-
2) Neat diagrams must be drawn wherever necessary.
16

tat
3) Figures to the right indicate full marks.
8.2

1s
.24

0:3
Q1) a) Design a full adder using 2 half adders. [7]
91
49

9:4
30

b) Design and implement one bit comparator. [5]

50
01
02

c) Design 16:1 multiplexer using two 8:1 multiplexer. [5]

5/2
GP

OR
7/0
CE
71

7
Q2) a) Design and explain 1:4 DEMUX with block diagram, truth-table,

23
.23

equation and logic diagram. [7]

ic-
16

tat
b) Implement the full subtractor using a 1:8 demultiplexer. [5]
8.2

1s
.24

0:3

c) Draw and explain the look-ahead carry generator. [5]

91
49

9:4
30
50
01

Q3) a) Design a sequence generator using T FFs for sequence 1101. [8]
02
5/2
GP

b) Distinguish between synchronous counter and asynchronous counter.

7/0

[5]
CE
71

c) Explain with diagram the working of D type Flip-flop. Give its truth
.23

table. [5]
16
8.2

OR
.24

P.T.O.
49
Q4) a) Draw and explain 3 bit asynchronous counter using JK FF. [8]

7
23
b) Design a 3 bit twisted ring counter. Draw logic diagram. [5]

ic-
c) Compare Moore and Mealy machines. [5]

tat
1s
0:3
02 91
Q5) a) What do you mean by excitation table of flip flop? Write the excitation

9:4
table of [9]

0
50
i) 7/0 13
D flip flop
0
5/2
ii) J-K flip flop
.23 GP

b) Explain : [8]
E
71

7
i) State Table
C

23
ic-
ii) State Diagram
16

tat
iii) State Assignment
8.2

1s
iv) ASM chart
.24

0:3
91
49

OR
9:4
30

Q6) a) Design a sequence detector to detect a sequence 1101 using D FF (Use

50

Moore machine) [9]

01
02
5/2

b) Explain in short:
GP
7/0

i) Moore Machine
CE
71

7
ii) Mealy Machine [8]

23
.23

ic-
16

tat
Q7) a) Explain block diagram of FPGA with its basic characteristics. [8]
8.2

1s

b) Write short notes on memories. [10]

.24

0:3
91

OR
49

9:4
30

Q8) a) Implement following Boolean function using PAL. [8]

50

F1 =  m (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)

01
02
5/2

F2 = m  (1, 2, 8, 12, 13).

GP
7/0

b) Describe with neat diagram AND-OR structure of PLA and PAL. [10]
CE
71
.23


16
8.2
.24
49

[6402]-23R 2
Total No. of Questions : 6] SEAT No. :

8
23
PC393 [Total No. of Pages : 2
[6359]-513

ic-
tat
S.E. (ELECTRONICS / E&TC/Electronics & Computer (Electronics

1s
Eng.(VLSI Design & Tech.)/Electronics & Comm.-Adv. Comm. Tech.)

0:2
02 91
DIGITAL CIRCUITS

0:4
(Insem) (2019 Pattern) (Semester-III) (204182)

0
41
Time : 1 Hour] 9/1 13 [Max. Marks : 30
0
Instructions to the candidates:
0/2
.23 GP

1) Answer Q1 or Q2, Q3 or Q4, Q5 or Q6.

2) Figures to the right indicates full marks.
E
80

8
3) Neat diagram must be drawn wherever necessary.
C

23
ic-
4) Use of non-programmable calculator is allowed.
16

tat
5) Assume suitable data, if necessary.
8.2

1s
.24

Q1) a) Explain the following characteristics of digital IC’s: [6]

0:2
91
49

0:4
i) Figure of Merit
30
41

ii) Propagation delay.

01
02
0/2

iii) VIH and VOH

GP
9/1

b) Draw and explain the working of CMOS Inverter. [4]

CE
80

8
23
OR
.23

Q2) a) Draw and explain the working of 2- input TTL NAND gate. ic-
[6]
16

tat
8.2

1s

List advantages of Totem Pole.

.24

0:2
91

b) Explain the following characteristics of digital IC’s: [4]

49

0:4
30

i) Noise Margin
41
01
02

ii) Fan out and Fan in

0/2
GP
9/1
CE
80

Q3) a) Design full adder using logic gates. [4]

.23

b) Minimize the following expression using K-map and implement using

16

logic gates : Y = m(1, 3, 5, 9, 11, 13) [6]

8.2

OR
.24

P.T.O.
49
Q4) a) Design 3-bit Gray code to Binary converter. [6]

8
23
b) Design full subtractor using logic gates. [4]

ic-
tat
1s
Q5) a) Minimize the following function using K-map and implement it using

0:2
only NAND gates. [6]

02 91
0:4
F(P,Q,R,S) = m(4,5,6,7,8,12) + d(l,2,3,9,l1,14)

0
41
b) Compare TTL and CMOS logic families.
9/1 13 [4]
OR
0
0/2
.23 GP

Q6) a) Explain the current parameters in TTL logic. [4]

E
80

8
b) Minimize the following function using Quine Mc Clusky method. [6]
C

23
ic-
F(A, B, C, D) = (0, 3, 5, 7, 12, 15) + d(2, 9).
16

tat
8.2

1s
.24

0:2
91
49

eeee
0:4
30
41
01
02
0/2
GP
9/1
CE
80

8
23
.23

ic-
16

tat
8.2

1s
.24

0:2
91
49

0:4
30
41
01
02
0/2
GP
9/1
CE
80
.23
16
8.2
.24

[6359]-513 2
49
Total No. of Questions : 8] SEAT No. :

8
23
PB3622 [Total No. of Pages : 2

ic-
[6261]-27

tat
S.E. (E & TC/Electronics/Computer Engineering)

1s
DIGITAL CIRCUITS

6:5
(2019 Pattern) (Semester - III) (204182)

02 91
3:3
Time : 2½ Hours] [Max. Marks : 70

0
41
1/0 13
Instructions to the candidates:
1) Answer Q. No.1 or [Link].2, [Link].3 or [Link].4, [Link].5 or [Link].6 and [Link].7 or [Link].8.
0
2) Neat diagrams must be drawn wherever necessary.
5/2
.23 GP

3) Figures to the right indicate full marks.

4) Use of Calculator is allowed.
E
82

5) Assume Suitable data, if necessary.

8
C

23
ic-
16

tat
8.2

1s
Q1) a) Explain implementation of full adder using 8 : 1 MUX. [6]
.24

b) Explain 3-bit parity checker circuit. [6]

6:5
91
c) Implement 1 : 16 demux using 1 : 4 demux. [6]
49

3:3
30
41

OR
01
02

Q2) a) Implement the given logic function using a 4 : 1 multiplexer. [6]

f (A, B, C) =  m (0, 1, 2, 4, 7)
5/2
GP
1/0
CE
82

b) Implement 3-bit parity generator circuit. [6]

8
23
c) Explain the working of a half-subtractor? Draw its logic diagram. [6]
.23

ic-
16

tat
Q3) a) Design a circuit to generate the following sequence using D FFs 1011.[8]
8.2

1s
.24

6:5

b) Explain with neat diagram the types of shift register. [9]

91
49

3:3
30

OR
41

Q4) a) Design a 3- Bit asynchronous counter using JK FF. [9]

01
02

b) Convert SR flip - flop into JK flip flop. [8]

5/2
GP
1/0

Q5) a) Write short note on state diagram and state table with suitable example.[6]
CE
82

b) Write short note on Principal Component of an ASM Chart. [6]

.23

c) Draw the state diagram of SR flip flop and JK flip flop. [6]
16
8.2

OR
.24

P.T.O.
49

[6261]-27 1
Q6) a) Draw ASM chart for 2 bit binary counter having enable line E Such that :

8
23
E = 1, Count Enable and E = 0, Count Disable. [9]

ic-
b) Compare Mealy and Moore machine. [9]

tat
1s
Q7) a) Classify and explain the characteristics of memories. [9]

6:5
02 91
b) Implement 3-bit binary to Gray code converter using PROM. [8]

3:3
0
41
1/0 13 OR
0
Q8) a) Design and implement 2-bit comparator using PAL? [9]
5/2
.23 GP

b) Explain CPLD architecture. [8]

E
82

8
C

23
ic-
… … …
16

tat
8.2

1s
.24

6:5
91
49

3:3
30
41
01
02
5/2
GP
1/0
CE
82

8
23
.23

ic-
16

tat
8.2

1s
.24

6:5
91
49

3:3
30
41
01
02
5/2
GP
1/0
CE
82
.23
16
8.2
.24
49

[6261]-27 2
Total No. of Questions : 8] SEAT No. :

8
23
P1486 [Total No. of Pages : 2
[6002]-113

ic-
tat
S.E. (Electronics/Electronics & Computer/E & TC)

8s
DIGITAL CIRCUITS

1:1
(2019 Pattern) (Semester - III) (204182)

02 91
0:4
Time : 2½Hours] [Max. Marks : 70

0
31
Instructions to the candidates:
6/0 13
1) Answer [Link].1 or [Link].2, [Link].3 or [Link].4, [Link].5 or [Link].6, [Link].7 or [Link].8.
0
2) Neat diagrams must be drwan wherever necessary.

om
6/2
.23 GP

3) Figures to the right indicates full marks.

E

Q1) a) Explain the working of a half-adder? Draw its logic diagram. [7]
81

rsic-238
.c
C

b) Implement the full subtractor using a 1 : 8 demultiplexer. [5]

c) Implement the following function using multiplexer
16

tat
f (A,B,C) = ∑m (0, 2, 4, 6). [5]
8.2

es
OR

:18
.24

Q2) a) Draw the logic diagram of full-adder and its truth table. [7]
:41p
02P 91
b) Implement a full-adder using Demultiplexer. [5]
49

0a
c) Implement the given logic function using a 4 : 1 multiplexer.
0
31
6/0 n13

f (A,B,C) = ∑m (0, 2, 4, 6). [5]

P0
6/2
8 1 io

Q3) a) For the state diagram shown in figure, obtain the state table and design
.23 tG

the circuit using minimum number of J = K flip - flops. [8]

CE
s

38
ue

c-2
i
16

tat
Q
8.2

8s
.24

1:1
PU

91
49

0:4
30
31
SP

01
02
6/2
GP

b) Explain the function of a shift register. Give its application. [5]

6/0

c) Explain with truth table the working of clocked RS flip-flop. [5]

CE

OR
81

Design a sequence generator using T FFs 0 → 1 → 7 → 4 → 2 .

.23

Q4) a) [8]
↑ |
16

b) Explain the types of shift register. [5]

8.2

c) Explain with diagram the working of D type Flip-flop. Give its truth table.[5]
.24

P.T.O.
49
 8
Q5) a) Design the clocked sequential circuit for the state diagram using JK flip

23
flop. [9]

ic-
tat
8s
1:1
02 91
0:4
0
31
6/0 13
0

om
6/2
.23 GP

b) Draw ASM chart for a 2 bit up-down counter having mode control input
M. [8]
E
81

rsic-238
.c
C

M=1 Up counter.
M = 0 Down Center.
16

tat
OR
8.2

es
Q6) a) Design a sequential circuit using Mealy machine for detecting the

:18
.24

sequence......1001.......Use Jk Flip-flop. [9]

:41p
02P 91
b) Explain in short: [8]
49

0a
i) State Diagram.
0
31
6/0 n13

ii) ASM chart.

P0
6/2

Q7) a) Explain the classification of memories based on their principle of

8 1 io
.23 tG

operation. [8]
CE

b) Write a short note on concept of PLA and PAL. [10]

s

38
ue

c-2
OR
i
16

tat
Q8) a) Explain with circuit diagram the dynamic MOS memory. [8]
Q
8.2

8s

b) A combinational circuit defined by the function. [10]

.24

F1(A, B, C) = ∑ (3, 5, 6, 7) and F2(A, B, C) = ∑ (0, 2, 4, 7)

1:1
PU

91

Implement the circuit with PLA having 3 inputs, 3 products terms and 2
49

0:4

out puts.
30
31
SP

01
02

  
6/2
GP
6/0
CE
81
.23
16
8.2
.24

[6002]-113 2
49
Total No. of Questions : 6] SEAT No. :

8
23
P-5387 [Total No. of Pages : 2

ic-
[6186]-513

tat
6s
S.E. (Electronics/Computer Engineering/E&TC) (Insem.)

0:4
DIGITAL CIRCUITS

02 91
0:4
(2019 Pattern) (Semester - III) (204182)

0
31
1/1 13
0
Time : 1 Hour] [Max. Marks : 30

om
0/2
.23 GP

Instructions to the candidates:

1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6.
E
81

rsic-238
.c
2) Figures to the right indicate full marks.
C

3) Neat diagrams must be drawn wherever necessary.

16

4) Use of non-programmable calculator is allowed.

tat
8.2

5) Assume suitable data, if necessary.

es
:46
.24

:40p
02P 91
Q1) a) Explain the following characteristics of digital IC’s : [6]
49

0a
0

i) Fan In and Fan Out

31
1/1 n13

ii) IIL and IOH

P0
0/2
8 1 io

iii) Propagation delay

.23 tG

b) Draw and explain the operation of CMOS inverter for LOW and HIGH
CE
s

inputs. [4]

38
ue

c-2
OR
i
16

tat
Q2) a) Draw and explain the working of 2-input CMOS NAND gate. [6]
Q
8.2

6s

b) Explain the following characteristics of digital IC’s : [4]

.24

0:4
PU

91

i) Noise Margin
49

0:4
30

ii) Power Dissipation

31
SP

01
02
0/2
GP

Q3) a) Implement and explain the working of full adder using basic gates.
1/1

[5]
CE
81

b) Minimize the following expression using K-map and implement using

.23

logic gates : [5]

16

d( ) indicates don’t care conditions

8.2

Y = m(1, 3, 7, 11, 15) + d(0, 2, 5)

.24
49

P.T.O.
 OR

8
23
Q4) a) Design 3-bit Gray to Binary code converter. [6]

ic-
tat
b) Design full subtractor using half subtractors. [4]

6s
0:4
02 91
0:4
Q5) a) Design and implement BCD to Excess-3 code converter using logic

0
31
gates. [6]
1/1 13
b) Draw and explain the working of 2-input TTL NAND gate. [4]
0

om
0/2
.23 GP

OR
E
81

rsic-238
.c
Q6) a) Explain the difference between current sourcing and current sinking in
C

TTL logic. [4]

16

tat
b) Minimize the following function using Quine Mc Clusky method.[6]
8.2

es
:46
.24

F(A, B, C, D) = m(0, 1, 2, 3, 5, 7, 8, 9, 11, 14)

:40p
02P 91
49

0a
0
31
1/1 n13


P0
0/2
8 1 io
.23 tG
CE
s

38
ue

c-2
i
16

tat
Q
8.2

6s
.24

0:4
PU

91
49

0:4
30
31
SP

01
02
0/2
GP
1/1
CE
81
.23
16
8.2
.24
49

[6186]-513 2
Total No. of Questions : 8] SEAT No. :

8
23
P9102 [Total No. of Pages : 2

ic-
[6179]-227

tat
S.E. (Electronics / E & TC / Computer)

5s
DIGITAL CIRCUITS

7:0
02 91
(2019 Pattern) (Semester-III) (204182)

9:3
0
40
Time : 2½ Hours] 1/0 13 [Max. Marks : 70
0
Instructions to the candidates:
1/2
.23 GP

1) Solve [Link].1 or [Link].2, [Link].3 or [Link].4, [Link].5 or [Link].6, [Link].7 or [Link].8.

2) Neat diagrams must be drawn wherever necessary.
E
80

3) Figures to the right indicate full marks.

8
C

23
4) Use of Calculator is allowed.

ic-
5) Assume suitable data, if necessary.
16

tat
Q1) a) Explain binary subtraction using l’s compliment and two’s compliment
8.2

5s
method with example. [6]
.24

7:0
91
b) Design and explain 3-bit parity generator circuit. [6]
49

9:3
30

c) Implement 1:8 demux using 1:4 demux. [6]

40
01
02

OR
1/2
GP

Q2) a) Design and explain 2-bit comparator circuit using logic gates. [6]
1/0
CE

b) Implement 16:1 Mux using 4:1 Mux. [6]

80

8
23
.23

c) Explain Look ahead carry generator circuit. [6]

ic-
16

tat
8.2

5s

Q3) a) Explain working of SR Flip flop with neat Block diagram and truth table.
.24

7:0
91

[6]
49

9:3
30

b) Convert JK flip flop into D flip flop. [6]

40
01
02

c) Design and implement 2-bit synchronous counter using T flip flop. [5]
1/2
GP

OR
1/0

Q4) a) Explain working of JK Flip flop with neat Block diagram and truth table.
CE
80

[6]
.23

b) Convert SR flip flop into T flip flop. [6]

16
8.2

c) Write short note on Shift registers. [5]

.24

P.T.O.
49
 8
23
Q5) a) Design the sequential circuit for the given state diagram using T flip flop.

ic-
[9]

tat
5s
7:0
02 91
9:3
0
40
1/0 13
0
1/2
.23 GP

b) Design and implement circuit using D flip flop to detect the following
E

binary sequence 110. [8]

80

8
C

23
ic-
Q6) a) Draw ASM chart for 2 bit binary counter having enable line E such that:
16

tat
E=1, Count Enable and E=0, Count Disable. [9]
8.2

5s
b) Write short note on state reduction with suitable example. [8]
.24

7:0
91
49

Q7) a) Explain the block diagram of memory unit? [9]

9:3
30

b) Explain FPGA architecture. [9]

40

OR
01
02

Q8) a) Design and implement Full Subtractor using PAL? [9]

1/2
GP

b) Explain CPLD architecture. [9]

1/0
CE
80

8
23
.23

   ic-
16

tat
8.2

5s
.24

7:0
91
49

9:3
30
40
01
02
1/2
GP
1/0
CE
80
.23
16
8.2
.24

[6179]-227 2
49
Total No. of Questions : 8] SEAT No. :

8
23
PA-1191 [Total No. of Pages : 2

ic-
[5925]-213

tat
S.E. (Electronics/E & T.C/Electronics & Computer)

1s
3:3
DIGITAL CIRCUITS

02 91
3:3
(2019 Pattern) (Semester-III) (204182)

0
31
Time : 2½ Hours] 7/0 13 [Max. Marks : 70
0
Instructions to the candidates:
2/2
.23 GP

1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6, Q.7 or Q.8.

2) Neat diagrams must be drawn wherever necessary.
E
80

8
3) Figures to the right indicate full marks.
C

23
ic-
16

Q1) a) Draw the logic diagram of full-adder and its truth table. [7]

tat
8.2

1s
b) Implement a full-adder using Demultiplexer. [5]
.24

3:3
91
c) Implement the given logic function using a 4:1 multiplexer [5]
49

3:3
30

f ( A, B, C ) =  m(0, 2, 4,6)
31
01
02

OR
2/2
GP

Q2) a) Explain the working of a half-adder? Draw its logic diagram. [7]
7/0
CE
80

b) Implement the full subtractor using a 1:8 demultiplexer. [5]

8
23
.23

c) Implement the following function using multiplexer [5]

ic-
16

tat
f ( A, B, C ) =  m(0, 2, 4,6)
8.2

1s
.24

3:3
91
49

3:3

Q3) a) Design a sequence generator using T FFs. [8]

30
31

b) Explain the types of shift register. [5]

01
02

c) Explain with diagram the working of D type Flip-flop. Give its truth table.
2/2
GP

[5]
7/0

OR
CE
80

Q4) a) Design a 3-Bit synchronous counter using JK FF. [8]

.23

b) With the neat diagram, explain the working operation of 4-bit SISO. [5]
16
8.2

c) Explain S-R flip-flop using NOR gates. [5]

.24

P.T.O.
49
 8
Q5) a) Design the clocked sequential circuit for the state diagram using JK flip

23
flop. [9]

ic-
tat
1s
3:3
02 91
3:3
0
31
7/0 13
0
2/2
.23 GP
E
80

8
b) Draw ASM chart for 2 bit binary counter having one enable line E such
C

23
that: E=1, [8]

ic-
16

tat
c) Count Enable and E=0, Count Disable.
8.2

1s
OR
.24

3:3
91
Q6) a) Design a sequence detector to detect a sequence 1101 using D FF [9]
49

3:3
30

(Use Moore machine).

31
01

b) Explain in short: [8]

02

i) State Assignment
2/2
GP

ii) ASM chart

7/0
CE
80

8
Q7) a) Explain the classification based on their physical characteristics. [8]

23
.23

b) Explain the concept of PLA with the help of a block diagram. [10]
ic-
16

tat
OR
8.2

1s

Q8) a) Explain the meaning of static and dynamic memories. State their
.24

3:3

applications. [8]
91
49

b) Describe with neat diagram AND-OR structure of PLA and PAL. [10]
3:3
30
31
01
02


2/2
GP
7/0
CE
80
.23
16
8.2
.24

[5925]-213
49

2
Total No. of Questions : 6] SEAT No. :

8
23
PA-423 [Total No. of Pages : 2

ic-
[5931]-8

tat
S.E. (Electronics/E&TC/Electronics & Computer)

1s
0:3
DIGITAL CIRCUITS

02 91
0:4
(2019 Pattern) (Semester - I) (204182)

0
31
8/0 13
0
Time : 1 Hour] [Max. Marks : 30
1/2
.23 GP

Instructions to the candidates:

E

1) Answer Q.1 or Q.2, Q.3 or Q.4, Q.5 or Q.6.

81

8
C

23
2) Figures to the right indicate full marks.

ic-
3) Neat diagrams must be drawn wherever necessary.
16

tat
4) Use of non-programmable calculator allowed.
8.2

1s
5) Assume suitable data, if necessary.
.24

0:3
91
49

0:4
30

Q1) a) Explain the following characteristics of digital IC’s. [6]

31
01
02

i) Figure of Merit
1/2
GP

ii) Propagation delay

8/0

iii) VIH and VOH

CE
81

8
23
b) Draw and explain the working of CMOS Inverter. [4]
.23

OR ic-
16

tat
8.2

1s

Q2) a) Draw and explain the working of 2-input TTL NAND gate. List advantages
.24

0:3

of Totem Pole. [6]

91
49

0:4

b) Explain the following characteristics of digital IC’s. [4]

30
31

i) Noise Margin
01
02

ii) Fan out and fan in

1/2
GP
8/0
CE

Q3) a) Design full adder using logic gates. [4]

81
.23

b) Minimize the following expression using K-map and implement using

logic gates : Y = Σm (1, 3, 5, 9, 11, 13). [6]
16
8.2

OR
.24

P.T.O.
49
Q4) a) Design 3-bit Gray code to Binary converter. [6]

8
23
b) Design full subtractor using logic gates. [4]

ic-
tat
1s
0:3
Q5) a) Minimize the following function using K-map and implement it using only

02 91
0:4
NAND gates. F(P, Q, R, S) = Σm (4, 5, 6, 7, 8, 12) + d (1, 2, 3, 9, 11, 14)

0
31
[6]
8/0 13
0
b) Compare TTL and CMOS logic families.
1/2 [4]
.23 GP

OR
E
81

8
C

23
Q6) a) Explain the current parameters in TTL logic. [4]

ic-
16

tat
b) Minimize the following function using Quine Mc Clusky method.
8.2

F(A, B, C, D) = Σπ (0, 3, 5, 7, 12, 15) + d (2, 9).

1s
[6]
.24

0:3
91
49

0:4
30


31
01
02
1/2
GP
8/0
CE
81

8
23
.23

ic-
16

tat
8.2

1s
.24

0:3
91
49

0:4
30
31
01
02
1/2
GP
8/0
CE
81
.23
16
8.2
.24

[5931]-8
49