Digital Electronics Lab (Pattern 2015)
Assignment No: 9 Group B
R C O T Dated
(2) (4) (2) (2) Sign
Title: Ripple Counter
Objective: Ripple up and down counter using IC 7476
Problem statement: To design and implement 3 bit UP, Down, Ripple Counter using
JK Flip-flop.
Hardware & software requirements:
IC 7476 (MS-JK Flip-flop), Digital Trainer Kit, patch cords, +5V power supply.
Theory:
1) Asynchronous counter:
A digital counter is a set of flip flop. An Asynchronous counter uses T flip
flop to perform a counting function. The actual hardware used is usually J-K flip-flop
connected to logic 1.
In ripple counter, the first flip-flop is clocked by the external clock pulse &
then each successive flip-flop is clocked by the Q or /Q’ output the previous flip-flop.
Therefore in an asynchronous counter the flip-flop are not clocked simultaneously. The
input of MS-JK is connected to VCC because when both inputs are one output is toggled.
As MS-JK is negative edge triggered at each high to low transition the next flip-flop is
triggered. On this basis the design is done for MOD-8 counter.
2) Up Counter:
Fig 1 shows 3 bit Asynchronous Up Counter. Here Flip-flop A act as a
MSB Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to the
Clock of flip-flop C. Output of Flip-flop C (Qc) is connected to clock of next flip-flop(i.e.
Flip-flop B) and so on. As soon as clock pulse changes out put is going to -change(at the
negative edge of clock pulse) as a Up count sequence. For 3 bit Up counter Truth table is
as shown below.
3) Down Counter:
Fig 2 shows 3 bit Asynchronous Down Counter. Here Flip-flop a act as
a MSB Flip-flop and Flip-flop C can act as a LSB Flip-flop. Clock pulse is connected to
the Clock of flip-flop C. Output of Flip-flop C (Qc’) is connected to clock of next flip-
flop (i.e. Flip-flop B) and so on. As soon as clock pulse changes output is going to change
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Digital Electronics Lab (Pattern 2015)
(at the negative edge of clock pulse) as a down count sequence. For 3 bit down counter
Truth table is as shown below.
In both the counters Inputs J and K are connected to Vcc, hence J-K Flip flop can work in
toggle mode. Preset and Clear both are connected to logic 1.
Truth Table:
Up Counter Down Counter
Counter States F/F Output Counter States F/F Output
QA QB QC
QA QB QC
0 0 0 0 7 1 1 1
1 0 0 1 6 1 1 0
2 0 1 0 5 1 0 1
3 0 1 1 4 1 0 1
4 1 0 0 3 0 1 1
5 1 0 1 2 0 1 0
6 1 1 0 1 0 0 1
7 1 1 1 0 0 0 0
Logic diagram:
Fig 1: 3 Bit Asynchronous Up Counter
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Digital Electronics Lab (Pattern 2015)
Fig 2: 3 Bit Asynchronous Down Counter
Timing Diagram:
1. 3 Bit Asynchronous Up Counter
CLK
Qa 0 0 0 0
3 1 1 1
Aa
+
.
1
Qb 0 0 1 1 0 0 1 1
Aa
Qc 0 0 0 0 1 1 1 1
Aa
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Digital Electronics Lab (Pattern 2015)
2. 3 Bit Asynchronous Down Counter:
CLK
Qc 0 0 0 0
1 1 1 1
Aa
Qb 0 1 1 0 0 1 1 0
Aa
Qa 0 0 0 0
Aa 1 1 1 1
Uses:
1) The counters are specially used as the counting devices.
2) They are also used to count number of pulses applied.
3) It also works for dividing frequency.
4) It helps in counting the number of product coming out of the machinery where
product is coming out at equal interval of time.
Outcomes: Thus, we implemented up and down ripple counter. Using IC 7476
Enhancements/modifications:
As the design part is done for the 3 bit Counter, we can implement the same for 4 bit
counter.
FAQ’s with answers:
What do you mean by Counter?
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Digital Electronics Lab (Pattern 2015)
A Counter is a register capable of counting the no. of clock pulses arriving at Its
clock- inputs. Count represents the no. of clock pulses arrived. A specified sequence of
states appears as the counter output.
What are the types of Counters? Explain each.
There are two types of counters as Asynchronous Counter and Synchronous Counter.
Asynchronous Counter: In this counter, the first flip-flop is clocked by the external
clock pulse and then each successive flip-flop is clocked by the Q or Q’ o/p of the
previous flip-flop. Hence in Asynchronous Counter flip-flops are not clocked
simultaneously and hence called as Ripple Counter.
Synchronous Counter: In this counter, the common clock input is connected to all the
flip-flops simultaneously.
What are the problems involved in Ripple Counter?
There are two problems in Ripple Counter as
i. Glitch
ii. Propagation delay of flip-flop.
Why asynchronous counters are called as ripple counters?
In asynchronous counter the first flip-flop is clocked by the external clock pulse &
then each successive flip-flop is clocked by the Q or /Q’ output of the previous flip-flop
i.e. clock (pulses) applied ripple from stage to stage to stage (LSB to MSB) hence
asynchronous counters are called as ripple counters.
What do you mean by pre-settable counters?
A counter in which starting state is not zero can be designed by making use of the
Preset inputs of the flip flops. This is referred to as loading the counter asynchronously.
This is referred to as pre-settable counter.
What are the applications of asynchronous counters?
Digital clock
Frequency divider circuits
Whether frequency division takes place in asynchronous counters?
Yes. In counter, the signal at the output of last flip flop (i.e. MSB) will have a
frequency equal to the input clock frequency divided by the MOD number of the counter.
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Digital Electronics Lab (Pattern 2015)
Can n- bit up asynchronous counter will act as n- bit down asynchronous
counter without changing the position of the clock?
Yes. Instead of taking output of a counter from uncomplimentary output (Q), if we
take it from complimentary output (Q bar), the same counter circuit will work as down
counter.
Assignments Questions:
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