SI99-01
Surging Ideas
TVS Diode Application Note
PROTECTION PRODUCTS
PCB Design Guidelines for ESD Suppression
Printed circuit board (PCB) layout is a critical compo- z As a minimum alternative to power and ground
nent for ESD immunity. Initial effort invested in a grids or multilayer boards, keep power and ground
sound PCB layout will save costly debugging and traces close together (Figure 3).
rework. While TVS diodes are required to suppress the z Another method for reducing loop area and in-
effects of direct charge injection that results from the duced currents is to minimize parallel paths be-
ESD, PCB design mainly impacts the effects due to the tween interconnected devices (Figure 4).
EM fields that are generated by the discharge current. z Guard traces may be used in situations where a
This application note will provide PCB design guidelines long (> 30cm) interconnected signal trace cannot
for optimum ESD immunity. be avoided (Figure 5). An even better solution is to
place a ground plane opposite the signal line. The
Circuit Loops signal line should be within 13 mm of the guard
Current is induced into any loop that encloses a changing trace or ground plane.
magnetic flux. The magnitude of the current will be z Transpose long sections (> 30cm) of signal or
proportional to the size of the loop. Larger loops power lines of very sensitive components with their
enclose more flux and thus higher currents are induced ground line as shown in Figure 6. The lines should
in the circuit. Therefore it is important to minimize loop be transposed at regular intervals from top to
areas. Some guidelines for minimizing loops areas are: bottom or left to right.
Line Lengths
z One of the most common sources of loop areas
are those formed by power and ground traces as Long signal traces will act as antennas to receive energy
shown in Figure 1. Whenever possible, multilayer from fields that are produced by the ESD pulse. By
PCBs with power and ground planes should be keeping line lengths as short as possible, the efficiency of
utilized. Multilayer boards not only minimize the the line to act as an antenna for ESD related fields is
loop area between power and ground, but also reduced.
mitigate the effects of high frequency EMI fields
that are produced by the ESD pulse. ·z Minimize interconnecting line lengths by placing
z If a multilayer board is not feasible, then multiple devices with the most interconnects as close
power and ground traces should be connected in a together as possible.
grid pattern as shown in Figure 2. The grid emu-
lates power and ground planes. Vias are used to Ground Charge Injection
connect traces on each layer. Connections should A direct ESD into the ground plane can cause damage to
be made every 6cm in each direction. sensitive circuits. One or more high frequency bypass
Figure 1 - Power and Ground PCB Loop
Revision 04/21/2003 1 [Link]
SI99-01
Surging Ideas
TVS Diode Application Note
PROTECTION PRODUCTS
capacitors along with a TVS diode should be placed voltage seen by the protected circuit will be the sum of
between the power and ground of vulnerable compo- clamping voltage of the TVS diode and the voltage due
nents. The bypass capacitors serve to reduce charge to parasitic inductance (VT = VC + VL). An ESD induced
injection and thus the voltage differential between power transient reaches a peak in less than 1ns (per IEC
and ground. The TVS diverts induced currents and 61000-4-2). Assuming a trace inductance of 20nH per
maintains the voltage differential at the level of the inch and a quarter inch trace, the voltage overshoot
clamping voltage of the TVS. The TVS and capacitors will be 50 volts for a 10A pulse. The primary rule of
should be placed as close as possible to the protected IC thumb is to minimize the effects of parasitic induc-
(Figure 7). Make sure TVS path length to ground and tance by making the shunt paths as short as possible.
capacitor lead lengths are minimized to reduce the All inductive paths must be considered including the
effects of parasitic inductance (described below).
Connectors should attach to the PCB by means of a
copper land. Ideally, the land should be separate from
the PCB ground plane and attached to the chassis via
a short strap.
Miscellaneous Guidelines
z Avoid running critical signal traces (clocks, resets,
etc.) near PCB edges.
z Fill unused portions of the PCB with ground plane. POOR
z Separate chassis ground traces from components
and signal traces by at least 4mm.
z Keep the chassis ground trace length-to-width ratio
<5:1 to minimize inductance.
z Protect all external connections with TVS diodes. BEST
Parasitic Inductance in the Protection Circuit
Figure 3 - Power and Ground Loop Reduction
Parasitic inductance in the path of the TVS diode can
result in severe voltage overshoot during an ESD
event. Significant overshoot may still exceed the
damage threshold of the protected IC despite the use
of TVS diodes. Recall that the voltage developed
across an inductive load is proportional to the time
rate of change in current flow (VL = L di/dt). The total
POOR
BETTER
Figure 2 - Power and Ground Grid
Figure 4 - Minimize Parallel Paths
2003 Semtech Corp. 2 [Link]
SI99-01
Surging Ideas
TVS Diode Application Note
PROTECTION PRODUCTS
ground return path, the path between the TVS and the
protected line, and the path from the connector to the
TVS device. Protected signal lines should be routed
directly to the TVS diode. Ground connections should
be made directly to the ground plane. If no ground
plane is present, the ground return trace must be kept
as short as possible. The distance between the ground
Figure 5 - Guard Trace
connection of the TVS diode and the ground connec-
tion of the protected circuit should also be minimized
to reduce parasitic inductance in the ground plane.
Finally, The TVS device should be placed as close to
the connector as possible to reduce transient coupling
into nearby traces. The secondary effects of radiated
emissions can cause upset to other areas of the board
even if there is no direct path to the connector.
UNTRANSPOSED LINES
References:
z Boxleitner, Warren, “Electrostatic Discharge and
Electronic Equipment,” IEEE Press, 1989.
z Mardiguian, Michel, “Electrostatic Discharge,
TRANSPOSED LINES
Understand, Simulate and Fix ESD problems,”
Interference Control technologies, 1992.
z Russell, Bill, “Power Protection is Critical For Figure 6 - Transpose Sensitive Signal Lines
Today’s Shrinking System Designs,” Wireless
Systems Design, February 1999.
z Standler, Ronald B., “Protection of Electronic
Circuits from Overvoltages,” John Wiley & Sons,
1989.
Figure 7 - TVS & Capacitor on Power Line
2003 Semtech Corp. 3 [Link]