A 0.

13µm CMOS integrated LC filter for a

Bluetooth receiver.

Frédéric Rey

1st July 2005

 Abstract

Le but de ce stage a été la réalisation d’un filtre LC à inductance intégrée

pour un récepteur Bluetooth. Le facteur de qualité du filtre est de 30 et sa
fréquence centrale est de 2, 442GHz. L’analyse des problèmes induits par
l’intégration de l’inductance, la procédure complète de conception du filtre
ainsi que les résultats de simulation du filtre intégré au modulateur Σ-∆ sont
présentés dans ce document.

The aim of this internship was to design a LC filter with an integrated

inductor for a Bluetooth receiver. The quality factor of the filter is equal to
30 and its center frequency is 2.442GHz. The analysis of the issues induced
by the integration of the inductor, the complete design procedure of the filter
and the simulation results of the filter in the Σ-∆ modulator are presented
in this document.
 I would like to thank Hassan Aboushady for the clarity of his explana-
tions, for preventing me from taking blind alleys and of course for having
accepted my application for this internship.

I would like to thank Nicolas Beilleau for his kindness and all the time
he spent helping me, I found real pleasure in working with him.

I would like to thank Marie-Minerve Louërat for the precious remarks she
did about my presentation, for trying to have me understand CAIRO+ in 1
hour and also for all the work she did to implement the design procedure ;
all the credit for that goes to her and I am very grateful to her.

I would like to thank Jacky Porte for his availability and the talks we
had. His pieces of advice have always been very useful to me.

Eventually, I want to thank all the people I have met at the LIP6 lab-
oratory and that made that 11 weeks experience even more pleasant and
interesting.

1
Contents

1 Introduction 5

2 Integrated Inductances 6
2.1 Non-Idealities . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.1 Related to the metal . . . . . . . . . . . . . . . . . . . 7
2.1.2 Related to the substrate . . . . . . . . . . . . . . . . . 9
2.1.3 Quality factor and self-resonance frequency . . . . . . . 9
2.2 Equivalent models . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 Broadband model . . . . . . . . . . . . . . . . . . . . . 10
2.2.2 Narrowband model . . . . . . . . . . . . . . . . . . . . 11
2.3 ASITIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 Principles . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.2 Technology file . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Layout effects on quality factor . . . . . . . . . . . . . . . . . 14
2.4.1 Geometry . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.2 Number of turns (N ) . . . . . . . . . . . . . . . . . . . 14
2.4.3 Winding width (w) . . . . . . . . . . . . . . . . . . . . 16
2.4.4 Winding spacing (s) . . . . . . . . . . . . . . . . . . . 16
2.4.5 Layers used . . . . . . . . . . . . . . . . . . . . . . . . 16

3 Integrated LC filter 18
3.1 Back to basics . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Quality factor enhancement circuit . . . . . . . . . . . . . . . 19
3.3 2nd order structure . . . . . . . . . . . . . . . . . . . . . . . . 21
3.4 Design procedure based on the quality factor . . . . . . . . . . 22
3.4.1 Simple RLC network . . . . . . . . . . . . . . . . . . . 23
3.4.2 RLC with R and C substrate parasitics . . . . . . . . . 23
3.4.3 Automatic sizing procedure with CAIRO+ . . . . . . . 25
3.5 Noise and linearity performances simulation . . . . . . . . . . 26

2
4 RF LC Σ-∆ Modulator 30
4.1 Basic principle . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.2 Noise shaping . . . . . . . . . . . . . . . . . . . . . . . 30
4.2 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . 31

5 Conclusions 33

3
List of Figures

2.1 A typical integrated inductor. . . . . . . . . . . . . . . . . . . 6

2.2 Current flow constriction to the surface of the conductor due
to skin effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Current flow constriction in the inner’s inductor winding due
to proximity effect. . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Parasitic capacitive coupling. . . . . . . . . . . . . . . . . . . 9
2.5 Parasitic magnetic coupling. . . . . . . . . . . . . . . . . . . . 10
2.6 The inductor broadband model. . . . . . . . . . . . . . . . . . 11
2.7 The inductor narrowband model. . . . . . . . . . . . . . . . . 11
2.8 Layer parameters used by ASITIC. . . . . . . . . . . . . . . . 12
2.9 Q and L versus N . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10 Q and L versus w. . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11 Q and L versus s. . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.1 Filter’s impedance for Q = 1 and Q = 100. . . . . . . . . . . . 19

3.2 The positive feedback system in the filter. . . . . . . . . . . . 20
3.3 Structure of the negative resistance. . . . . . . . . . . . . . . . 20
3.4 Differential topology of the filter. . . . . . . . . . . . . . . . . 21
3.5 Compensation of the effects of CSub and RSub . . . . . . . . . . 24
3.6 LC tank with CSub and RSub equivalent circuit. . . . . . . . . 25
3.7 Noise and linearity performances of the filter. . . . . . . . . . 27
3.8 Even harmonics rejection due to differential topology. . . . . . 29

4.1 Continous time Σ-∆ modulator. . . . . . . . . . . . . . . . . . 31

4.2 NTF of a modulator based on a lowpass and a bandpass filter. 31
4.3 SNR as a function of input amplitude. . . . . . . . . . . . . . 32

4
Chapter 1

Introduction

The aim of this internship was to design an integrated passband LC filter that
could be included in a Σ-∆ modulator of a RF reception stage. To be more
specific, the final goal is to meet the specifications required for Bluetooth
applications. Therefore, the first requirement for the filter will be to have a
2.442GHz center frequency and a 80MHz bandwidth, which corresponds to a
f0
quality factor (Q) of 30 (indeed Q = BW ). This involves the use of a negative
resistance device in order to compensate the losses induced by the integration
of the inductance in this CMOS technology. Unfortunately, as the negative
resistance device is made of active circuitry it will degrade the noise and the
linearity performances of the filter that are crucial to this application. But
this half-passive/half-active solution has proved to show better performances
than purely active devices and that is why it sounds like a good compromise
to us.
The first chapter of this report is dedicated to integrated inductors, the
reasons of their complex behaviour, the mean employed to simulate it, and
the choices we had to make in order to enhance their performances. The
second chapter describes our work to design the LC filter, the way we com-
pensate the losses induced by the integrated inductor, and then presents the
results of simulations and the performances achieved. The third chapter is
about the integration of the filter into a model of the ∆-Σ modulator and
the overall simulated performances of the system.

5
Chapter 2

Integrated Inductances

In CMOS technologies an inductor is simply made of metal windings. De-

pending on the technology possibilities, several metal layers may be used and
different geometries adopted (spiral, polygonal . . . ). A typical integrated in-
ductor is presented in figure 2.1.

Figure 2.1: A typical integrated inductor.

But compared to their discrete equivalent, their behaviour is far less ideal
due to several physical phenomena we will now discuss.

2.1 Non-Idealities
This section takes the inventory of the most important non idealities that
need to be taken into account in order to understand the behaviour of an
integrated inductor. The complexity and the number of those will lead the

6
reader to understand how necessary a simulation tool is in order to make
accurate predictions. The reader can refer to [5] for a more description of
those issues.

2.1.1 Related to the metal

Ohmic losses
The first non ideality which is not specific to the integrated inductors, is
due to the fact that the metal used is not a perfect [Link] as a
current flows in it, the inductor dissipates power through well known Joules
effect. In the technology we use the typical metal layer resistivity is about
50mΩ per square.

Skin effect
The skin effect is a physical phenomenon occurring at high frequencies that
causes the constriction of currents at the conductor’s surface (cf fig 2.2).
The modification in the current flow distribution translates into an efficient
section decreasing, leading to an increased wire resistance. The skin depth
(δ) is given by the following formula :
c
δ=√
µσf
where c is the speed of light, µ is the permeability and σ the conductivity of
the conductor.

Proximity effect
Each part of the inductor is subject to the influence of the magnetic field
created by the rest of it. Induced currents take place in the metal trace to
oppose this external magnetic field penetration. And as they superpose to
the initial current a new modification in the current flow appears (mainly a
limitation to the inner part of each winding) which depends on the magnetic
field intensity and hence of the winding considered (the magnetic field is the
strongest at the center of the inductor). See figure 2.3.

Inter winding capacity

The different windings separated by the oxide and made of the same metal
layer or not behave like capacitors. This lowers the self resonance frequency
of the inductor. See figure 2.4.

7
Figure 2.2: Current flow constriction to the surface of the conductor due to
skin effect.

Figure 2.3: Current flow constriction in the inner’s inductor winding due to
proximity effect.

8
2.1.2 Related to the substrate
The substrate is the major source of losses in CMOS integrated inductors.
This explains why the most effective way to enhance the quality factor is to
use technologies in which the substrate is non-conductive (e.g. saphir SiO2
substrate) or to use selective substrate etching techniques to make suspended
inductors.

Electrical coupling
The inductor-oxide-substrate device acts like a capacitor which has two ef-
fects. First of all it distorts the frequency behaviour of the inductor and it
induces new losses because of the Joules effect produced by the displacement
currents in the resistive substrate. See figure 2.4.

Figure 2.4: Parasitic capacitive coupling.

Magnetic coupling
As the time-varying magnetic field created by the inductor penetrates the
substrate, it gives birth in it to eddy currents which as two detrimental effects
: they increase the losses by Joules effect and induce an opposed magnetic
field that consequently lowers the device’s inductance. See figure 2.5.

2.1.3 Quality factor and self-resonance frequency

The quality factor (Q) of an inductor can be defined as follows :
Im(Z)
Q=−
Re(Z)
where Z is the impedance of the inductor. It follows that the Q is frequency
dependent.

9
 Figure 2.5: Parasitic magnetic coupling.

The self resonance frequency FSRES is defined by Q(FSRES ) = 0 which means

that the reactance is equal to zero. This happens because the capacitive cou-
plings (which have almost no effect at lower frequencies) cancel the inductive
behaviour of the device at high frequency. Above this frequency the device is
thus capacitive and losses all interest. But before going to zero, the Q peaks
and it is interesting to us to design our inductor so that the main frequency
of the circuit corresponds to the maximum Q.

2.2 Equivalent models

In order to model the behaviour of integrated inductors more or less complex
2-port networks exist, the choice of which depends on the desired accuracy
and the frequency range it is to be used.

2.2.1 Broadband model

This equivalent model -called the Pi model (see figure 2.6)- has proved to
match quite good with actual behaviour. The resistor RS in series with the
inductor LS models the losses in the inductor (including skin and crowding ef-
fects), the capacitor CS models the inter winding capacitance, the capacitors
COx model the capacitive coupling between the inductor and the substrate
through the oxide layer, and CSi and RSi respectively model the capacitive
coupling between the substrate and a possible ground plate, and the losses
induced in the substrate.

10
 Figure 2.6: The inductor broadband model.

2.2.2 Narrowband model

If only a narrow band (i.e. around a certain frequency) model is needed
then the one presented in figure 2.7 may be sufficient. It can be seen as an
equivalent circuit of the Pi-model at a given frequency.

Figure 2.7: The inductor narrowband model.

2.3 ASITIC
2.3.1 Principles
ASITIC (Analysis of Si Inductors and Transformers for ICs) is a CAD tool
created at the University of California at Berkeley by Ali M. Niknejad. It
is freely distributed via the University of Berkeley web site [2]. Its aim is
to help in designing inductors and transformers for integrated circuits. It
allows to simulate the high frequency effects so that accurate modeling can
be achieved (confer [1] for more details about ASITIC).

11
2.3.2 Technology file
In order to describe the technology ASITIC uses a small file containing geo-
metrical and electrical informations. Geometrical informations include metal
and oxide layers thicknesses as their relative positions. Electrical information
are mainly the metal conductivity and the dielectric constant of oxide layers
(see figure 2.8).

Figure 2.8: Layer parameters used by ASITIC.

Finding these pieces of information has not been a easy thing. We have
found most of them in the Design Rule Manuel (DRM) provided by ST Mi-
cro, but we have had to take peculiar values or infer missing ones in some
cases(Alucap thickness and substrate resistivity).

2.3.3 Simulation
ASITIC allows automatic design of various geometries of inductors. These
are circular or polygonal inductors, that can be symmetric or not. For ex-
ample, the command :
ASITIC>: poly name=a sides=8 radius=100 w=10 s=2 n=4 metal=m6
creates a 4-turn polygonal inductor called ’a’, made of metal 6, with a radius
of 100µm, a wire width of 10µm and a wire spacing equal to 2µm.
It is also possible to create multi-layer inductor by using the shunt to shunt
inductors, or join to create stacked series connected inductors.

12
< chip >
chipx = 512 ; chip x-dimension
chipy = 512 ;
fftx = 256 ; fft size /x (must be a power of 2, defines the spatial resolution)
ffty = 256 ;
TechFile = [Link] ; name of this file
TechPath = /home/niknejad/tekf ; directory where the data-files are stored
freq = 2.4 ;
eddy = 0 ; Layer 0 is defined as conductive, eddy currents will be taken into account

<layer> 0 ; Substrate
rho = 1 ; Resistivity (Ωcm)
t = 400 ; Thickness (µm)
eps = 11.9 ; Relative permitivity

<layer> 1 ; First oxide layer

rho = 15
t = 1
eps = 11.9

<metal> 0 ; First metal layer

layer = 1 ; Included in layer 1 (oxide)
rsh = 30 ; Resistivity (mΩ/square)
t = 0.1
d = .5 ; Space to the bottom of the layer
name = msub ; Name used in ASITIC
color = yellow ; colour in ASITIC

<via> 0 ; First via

top = 1 ; Connects metal layer 1
bottom = 0 ; to 0
r = 5 ; Resistance of a via
width = .4 ; width of a via
space = 1.3 ; minimal space between two vias
overplot1 = .3 ; minimal over plot of the first metal
overplot2 = .3 ; minimal over plot of the second metal
name = via0 ; name in ASITIC
color = purple ; colour in ASITIC

Table 2.1: ASITIC sample techfile.

13
Many analysis commands are available, the most accurate being pix which
allows to make a full resolution of the problem (all the parasitics being taken
into account) at a given frequency and returns the narrow-band model pa-
rameters plus the quality factor of the inductor. It is invoked this way for a
2.4GHz analysis of the inductor ’a’ :
ASITIC>: pix a 2.4

2.4 Layout effects on quality factor

As the technology is imposed, the only mean to enhance the performances
of the inductor was to optimize its geometrical parameters. This section
presents the parameters we could make vary, a simple analysis describing
their effect on the quality factor, and the results of simulations with ASITIC.
Many publications deal with those problems, as in [8] for example. All sim-
ulation results are given for an octagonal inductor with an external radius of
100µm using the three top metal layers (alucap, m6, m5) shunted together
and at a 2.4GHz frequency.

2.4.1 Geometry
This is the easiest parameter to deal with as it is neither frequency nor
substrate dependent. If we consider a one-turn inductor then its inductance
value is proportional to its surface (S) and its equivalent resistance R to its
length (l). Therefore :
L S
Q=ω ∝
R l

The table 2.2 gives the length of the square and the octagon for a given
surface. Of course (although it is not obvious to demonstrate), the geometry
maximizing the ratio surface over perimeter is the circle. Still, due to techno-
logical limitations (the angle between two metal segments can’t be less than
45 degrees) the octagon is the best we can do.

2.4.2 Number of turns (N )

Given a certain external radius for the inductor, increasing the number of
turns by a factor n means a higher inductance (nα=2 times more, due to
mutual coupling between the windings if they had the same surface, but
as the winding’s surface decreases α is closer to 1) but also an increase in

14
 R l
geometry Rcircle
∝ lcircle
circle 1
octagon 1.027
square 1.128

Table 2.2: Length of the square and the octagon compared to the circle for
a given surface.

the inductor’s resistance. Unfortunately, this increase is not just almost

proportional to n, because of the proximity effect : the inner windings of the
inductor will have a much a higher impedance and will degrade the quality
factor. That’s the reason why hollow inductor are used to achieve high Q.
Furthermore, increasing the number of turns also increases all the capacitive
coupling. Simulation results with ASITIC are presented figure 2.9.

Figure 2.9: Q and L versus N .

15
2.4.3 Winding width (w)
Increasing the metal width lowers its resistance and seems therefore benefi-
cial, but this as two main negative effects. First it increases the capacitive
coupling with the substrate, and second, it increases the proximity effects
intensity.
There again, a compromise has to be done. Simulation results with ASITIC
are presented figure 2.10.

Figure 2.10: Q and L versus w.

2.4.4 Winding spacing (s)

The minimal winding spacing is optimal as long as the inter-winding capaci-
tive coupling does not become predominant. Simulation results with ASITIC
are presented figure 2.11.

2.4.5 Layers used

In order to minimize the couplings with the substrate only top level metals
are used to design inductors. There are two main ways to use multiple layers
to design an inductor:

16
 Figure 2.11: Q and L versus s.

• Either n identical inductors can be stacked and joined in series. In

this case, making the assumption that the coupling coefficient can be
equated to 1 (which is almost realistic), the inductance value will in-
crease by a n2 factor and the series resistance value will increase by a
n factor, leading to a global n factor increase of the quality factor.

• Or n identical inductors can be stacked and shunted together (with

multiple vias). This leads to drop of a n1 factor of the series resistance
and to a n factor increase of the quality factor as well.

The major drawback of the series connection is the high inter-winding ca-
pacitance that lowers the self resonance frequency lowering the maximum
frequency of operation of the device, while the shunt connection only moves
the inductor closer to the substrate.

17
Chapter 3

Integrated LC filter

3.1 Back to basics

A simple inductance(L)-capacitance(C) filter can be described by two num-
bers : its center frequency (or pulsation, respectively f0 and ω0 ) and its
quality factor (Q0 ).
The center frequency of the filter is equal to :
1
f0 = √
2π LC
At that frequency, the impedance of the capacitor is the opposite of the one
of the inductor and the filter’s impedance reaches a maximum.
The quality factor describes reflects how lossy the filter is and can be defined
as :
Estore
Q0 = 2π
Ediss
where Estore is the energy stored per cycle whereas Ediss is the energy dissi-
pated per cycle. If the losses of the filter (mainly due to the inductor) are in
a prime approach modeled by a parallel resistor RL , then the quality factor
can be calculated as Q0 = ωR0LL = ω0 RC and its impedance is :

s/C
Z0 =
s2 + s Qω00 + ω0 2

where s = jω. In order to exhibit passband filter properties the input of the
device must be in current and the output in voltage. The influence of the
quality factor on the frequency response can be seen in figure 3.1.

18
 Figure 3.1: Filter’s impedance for Q = 1 and Q = 100.

3.2 Quality factor enhancement circuit

In order to compensate the losses introduced by the integrated inductor
(which Q is not higher than 6 in that technology) to achieve a filter Q of 30,
we have to use a positive feedback device.
There are many different ways to do that (in [4] mutual magnetic coupling
is for instance used), but we have chosen one of the most simple one, using
only a transistor differential pair (named 1 and 2) and a biasing transistor
(named 3) acting as a current source. The whole circuit behaves as a neg-
ative resistance. This choice was made because the low number of active
devices will allow to achieve low noise contribution at the cost of few free
parameters. It is integrated in parallel to the LC tank as shown in figure 3.2
(making here the assumption that the inductor losses are taken into account
by the resistor RL in parallel of the tank, and that no capacitive coupling is
to consider). The structure of the negative resistance is presented in figure
3.3.
The impedance of the negative resistance for small signals can be written as :
2 2
ZN egR = − =−
gm − gds gmef f

This is true as long as the operation point corresponds to saturation for

19
Figure 3.2: The positive feedback system in the filter.

Figure 3.3: Structure of the negative resistance.

20
transistors 1 and 2 i.e. as long as :
VT H
VDS > VGS − VT H ⇔ Vswing <
2
where Vswing = [vp − vn ]max .
The transfer function of the system can be written as :

vout sGm1 /C
H(s) = = 2
vin s + s Qωenh
0
+ ω0 2

Q0
where Qenh = 1−RL gmef f
is the enhanced quality factor of the filter and Q0 =
RL
ω0 L
= ω0 RL C is the quality factor of the filter alone.

3.3 2nd order structure

We have chosen to use a differential structure. It lowers the sensitivity to the
supply noise and enhances the linearity performances of the filter (because
the even-order harmonics are strongly rejected). The structure can be seen
figure 3.4.

Figure 3.4: Differential topology of the filter.

21
 Parameter Value
Geometry Octagonal, symetric
Metal layers Alucap-m6-m5, shunted
External Radius 100µm
Number of turns 4
Metal width 10µm
Metal spacing 2µm
Frequency of analysis 2.4GHz
L 2.32nH
Q 6.35
RL 5.25Ω
CSub 97.0f F
RSub 87.8Ω

Table 3.1: Inductor’s parameters.

3.4 Design procedure based on the quality

factor
We followed a gradual method to design the filter and its negative resistance.
Two main reasons made us begin with simple models of the inductor. First
it allowed us get used to the simulation environment (ELDO RF) without
having to worry about side-effects produced by more complex circuits. And
second, it helped us to understand various effects of the inductor’s non-
idealities.
ASITIC simulations resulted in the choice of an inductor. Its geometric and
narrow-band model parameters are given in table 3.1.
The first things for us to choose were the biasing voltages. The nominal
supply voltage in this technology is VDD = 1.20V . We chose that the drain
voltage of the biasing resistor should be 0.60V so that the VDS of the 3
transistor is equal to 0.6V . We have also chosen to set the length of the
transistor at 0.15µm. We haven’t chosen the smallest gate length possible
(O.13µm) in order to minimize mismatch impact. Indeed, due to several
physical stochastic effects, any electrical parameter of a transistor is described
by a normal Gaussian distribution function. For the parameter X it gives :
(X−X)2
P (X) ∝ e− σ

22
where X is X mean value and σ is the dispersion factor (99.73% of the dice
are present in the range X − 3σ and X + 3σ). It is written in the DRM that :
1
σ∝√
WL
where W is the transistor’s width and L its length. So choosing a larger
length leads to smaller mismatch dispersion.

3.4.1 Simple RLC network

The first model we used was a parallel RLC tank (see figure 3.4). This means
we neglected all capacitive coupling and suppose all the losses can be simpli-
fied into a parallel resistor.
The first thing to do is to determine the gmef f of the differential pair tran-
sistors needed to achieve Q = 30 :
1 1
gmef f = −
RL ω0 QL
Here ω0 = 2π ∗ 2.442 109 rad.s−1 , RL = 238Ω and L = 2.32nH, leading to
gmef f = 3.20mA.V −1 .
All the voltage biasing being known, we then run a simulation with ELDO
RF to determine what is the transistors’ width W to achieve this value. We
find :
W1 = W2 = 6.06µm

Once this is done we can calculate by simulation the biasing current needed
by the differential pair :
Ibias = ID1 + ID2 = 2 ∗ 6.21e−4 = 1.24mA

To finish with, we size the transistor 3 so that its drain current (under a 0.6V
gate-source voltage biasing) equals Ibias :
W3 = 8.84µm

3.4.2 RLC with R and C substrate parasitics

This model is the same as the former except that each port of the inductor
is connected to the ground by CSub and RSub in series. This has two effects
(see figure 3.5, green curve):

23
 • Capacitively loads the tank which lowers the center frequency of the
filter.
• Increases the losses which lowers the quality factor of the filter.
They can be compensated separately : tuning the capacitor value C of the
tank to obtain the correct center frequency (see figure 3.5, red curve), and
tuning the negative resistance value in order to achieve the right Q (see figure
3.5, blue curve).

Figure 3.5: Compensation of the effects of CSub and RSub .

The small signal equivalent circuit of a tank is shown figure 3.6. The
impedance of the compensated one is easily calculated as :
s/C
Z= 1 α2 CSub 1
LC
+ s
( 1
C RL
+ 1
RSub 1+α2
− gmef f ) + s2 (1 + C 1+α2
)

24
 RL RSub
L C
CSub

Figure 3.6: LC tank with CSub and RSub equivalent circuit.

where s = jω and α = ωRSub CSub . We see that the losses are now frequency
dependent while the compensation scheme is not. Therefore, we will com-
pensate the losses at the center frequency of the filter and a small (as long as
RSub is not too small) in-band ripple may appear in the frequency response
(we do this by replacing α by α0 = ω0 RSub CSub in the lossy term in s at the
denominator).
If we make the assumption that α2 < 1 (that can be equated with the fact
that the frequency of operation is smaller than the self resonance frequency
fSRES of the inductor, which is reasonable) then the impedance simplifies to
:
s/(C + CSub )
Z(ω ∼ ω0 ) ' α20
1
L(C+CSub )
+ C+Cs Sub ( R1L + RSub − gmef f ) + s2
which can be rewritten as :
s/(C + CSub )
Z'
ω02 + s Qωenh
0
+ s2

1 ω0 (C+CSub )
by assuming ω0 = √ and Qenh = 1
+ω 2 2 .
L(C+CSub ) RL 0 RSub CSub −gmef f

3.4.3 Automatic sizing procedure with CAIRO+

CAIRO+
CAIRO+ is a software developed at ASIM-LIP6 laboratory (see [13]). Its
purpose is to provide a language for designing generators of analog functions,
that can be easily ported to new set of specifications and new technology
processes.
The CAIRO+ language supports the four steps of a design flow based on
net-list and layout templates. This language is aimed to help the designer to
capture his knowledge, thus creating a library of layout-aware analog func-
tions. It is based on C++ language. The design flow relevant to CAIRO is
the following :
• net-list and layout template capture,

25
 • design space exploration (managing electrical constraints)

• shape function computation (managing geometrical constraints)

• layout generation (place and route)

CAIRO allows creating complex hierarchical analog function generators by

using existing generators of simpler functions. It is an answer to the problem
of Analog and Mixed IPs.

The sizing procedure

From the previous analysis we can deduce :
1
C= − CSub
Lω02

and
1 1
gmef f = + ω02 RSub CSub
2
−
RL Lω0 Qenh
The CAIRO+ procedure returns the tank capacitor value to get the correct
center frequency and the widths of the negative resistance transistors to get
the required Q from the biasing voltages and the inductor’s parameters.

3.5 Noise and linearity performances simula-

tion
We made noise and linearity simulations with ELDO RF in order to know
the filter’s performances. To do that, we connect at the input two sinusoidal
current sources with the same magnitude and of frequency f1 = 2.442GHz
and f2 = 2.443GHz (we simulate here two Bluetooth channels, which are
actually separated by 1MHz).
The results are presented figure 3.7. The x-axis represents the magnitude
of the input current and the y-axis the magnitude at the output voltage (both
of them are expressed in dB).
1dB
The blue curve represents dB(vout @f1or2 ). dBin is reached when the
output magnitude at f1or2 is 1dB under what it should have been if the
circuit was linear.
Due to the non-linearity of the filter, we observe at the output two inter
modulation (IM3) products at

fIM 1 = 2 ∗ f1 − f2 = 2.441GHz

26
and
fIM 2 = 2 ∗ f2 − f1 = 2.444GHz
(hence they disturb adjacent channels). In fact inter modulation products
exist for each linear combination of f1 and f2 , but the others have much too
low magnitudes to be observed. The purple curve is dB(vout @fIM 1orIM 2 ).
spurious
dBin is reached when the output magnitude at fIM 1orIM 2 equals the
noise magnitude.
Due to active circuits and the lossy inductor, the device generates noise
(red curve, and as it is mainly due to the biasing its almost independent of
the input signal). The output signal will be detectable only if its level is over
min
the noise level, which defines a minimal input magnitude dBin .

Figure 3.7: Noise and linearity performances of the filter.

From the peculiar dBin values we have defined, we can deduce two well
known figures of merit :

27
 min spurious 1dB
Parameter dBin dBin dBin SF DR 1dB − DR
Value (dB) −141 −93 −83 48 58
Intensity (A) 8.910−8 2.210−5 7.110−5 − −

Table 3.2: Filter’s performances.

• The spurious free dynamic range :

spurious min
SF DR = dBin − dBin

• The 1-dB dynamic range :

1dB min
1dB − DR = dBin − dBin

We point out the fact that the non linear behaviour of the filter can be
related with the leaving of the saturation region for the transistors of the
differential pair. Indeed, a sinusoidal current of amplitude Iin at the center
frequency of the filter produces a voltage swing equal to :
2Iin Qenh
Vswing = 2Iin Z(ω0 ) =
ω0 C

If we consider Iin = 7.110−5 A (1dB-compression point) this leads to :

Vswing = 0.15V

Now, saturation implies :

VT H 0.34
Vswing < ' = 0.17V
2 2
This issue could be overcame by using capacitive dividers in the feedback
path (i.e. to connect the transistor 1 drain to the transistor 2 gate and vice
versa -as in a Colpitts oscillator-). This would capacitively load the tank
(which would be to take into account when choosing C) and the negative
resistance should also be re-sized, but the saturation condition would allow
larger voltage swing.
The plot of the output power spectrum for a single tone input at 2.442GHz
(see figure 3.8) shows the strong even harmonics rejection due to the differ-
ential topology.

28
Figure 3.8: Even harmonics rejection due to differential topology.

29
Chapter 4

RF LC Σ-∆ Modulator

4.1 Basic principle

Σ-∆ modulators are used as Analog-to-Digital Converters. One of their ad-
vantage is to release the constraints on the ADC by using over sampling
frequency and quantization noise shaping. They allow to achieve extremely
high resolutions and are inherently programmable.

4.1.1 Oversampling
When an analog signal is converted to a digital signal quantization noise ap-
pears. This is due to the fact that the analog signal values are infinite and
continuous while the digital signal can only take a limited number of discrete
values. Consider the output spectrum of a N-bits ADC with a sampling
frequency fS (above Nyquist frequency) and a sine wave input signal. The
quantization noise spreads from DC to f2S with a flat average value. Increas-
ing fS by an oversampling factor k will cause that noise spread from DC to
k∗fS
2
(total quantization noise power being kept constant) lowering its aver-
age value. If the ADC is followed by a lowpass filter (usually a decimation
filter) with a f2S cut off frequency, the Signal-to-Noise Ratio (SNR) will hence
increase. To be more quantitative, each factor-of-4 oversampling increases
the SNR by 6dB, and each 6dB increase is equivalent to gaining one bit of
resolution.

4.1.2 Noise shaping

But oversampling is not the only mean used in Σ-∆ modulators to achieve
high SNR. The noise spectrum is shaped so that the in band noise levels is
even lower. The structure of such a modulator is shown figure 4.1. The loop

30
filter Hc (s) can either be a low pass or a band pass filter, depending on the
the output signal frequency desired. It is responsible for the noise shaping
and the filter’s type influence on the Noise Transfer Function (NTF) can be
seen fig 4.2.

Figure 4.1: Continous time Σ-∆ modulator.

Figure 4.2: NTF of a modulator based on a lowpass and a bandpass filter.

4.2 Simulation results

We put the active LC filter into a Σ-∆ modulator ideal model and compare
the simulation results with the one of the same structure where the filter is

31
modeled by its theoretical transfer function. The main performance figure of
the modulator are the SNR and the dynamic range.
The simulations are made with ELDO and using the BSIM3v3 transistor
model for ST 0.13µm. The input is a sine wave near the center frequency
of the filter (2.453GHz). The output power spectrum is calculated by FFT
from 16384 samples of the output. On a Spark computer the calculation of
one value of the SNR at a given input amplitude took 8 minutes for the ideal
filter and 20 minutes for the actual one. The results can be seen figure 4.3,
and show that the noise and linearity limitations of the actual filter do not
constitute a limitation regarding the modulator performances.

Figure 4.3: SNR as a function of input amplitude.

32
Chapter 5

Conclusions

In eleven weeks we managed to understand the difficulties induced by the

use of integrated inductors to realize a LC filter. We obtained by simulation
with ASITIC an optimized layout for the 0.13µm CMOS ST technology. We
designed a compensation structure for the filter, determined its performances
by ELDO simulation and did an automatic sizing procedure using CAIRO+.
We put that filter into a Σ-∆ modulator ideal model and compared the
simulation results obtained with the ones of the ideal filter. The achieved
performances of the actual filter have proved to be similar to the expected
ones.
Still, the SNR levels obtained with a 2nd order filter (45dB at best) are
not sufficient to meet the Bluetooth specifications (a 50dB SNR is at least
required). Simulation shows that one solution to this problem is to increase
the filter’s order which would enhance the noise shaping and hence the SNR.
We have been considering designing a 4th order LC filter by the mean of on
chip magnetic coupling of two 2nd order filter (as in [3]), but this could not
be done because of lack of time.
Besides, in a first time we determined the quality factor of the filter so
that its bandwidth matches with the Bluetooth one. This was a partial
mistake because as the filter is in a loop, the overall Signal Transfer Function
(STF) of the modulator does not reduce to the filter’s one. In fact the filter’s
quality factor mostly impacts the NTF. Studying this should allow to change
the Q = 30 imperative into a Q > Qmin design rule.

33
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35