RNS INSTITUTE OF TECHNOLOGY

Channasandra, Bengaluru - 560 098

DEPARTMENT OF CSE (Data Science)

Logic Design and Computer Organization (BCS302)

Module-4
 MODULE-4
Basic Structure of Computers, Instructions and
Programs
4.1 FUNCTIONAL UNITS
A computer consists of five functionally independent main parts:
 Input
 Memory
 Arithmetic logic unit
 Output
 Control units
• The input unit accepts the coded information from human operators, from electromechanical
devices such as keyboards, or from other computers over digital communication lines
• The information received is either stored in the computer’s memory for later reference or
immediately used by the arithmetic and logic circuitry to perform the desired operations.
• The results are sent back to the outside world through the output unit
• All these actions are coordinated by the control unit

It is convenient to categorize the information handled by the computer as either data or instructions
Instructions or machine instructions are explicit commands that
• Govern the transfer of information within a computer as well as between the computer and its
I/O devices.
• Specify the arithmetic and logic operations to be performed.

Fig 4.1 Functional Units of a Processor

 4.1.1. Input Units
o Input units allow computers to accept coded information.
o Keyboard is the most common input device → keys are converted into binary codes and sent to the
processor.
Other input devices include:
 Touchpad, mouse, joystick, trackball → mainly used for graphic input.
 Microphones → capture audio, convert to digital codes.
 Cameras → capture video, convert to digital codes.
 Digital communication (e.g. Internet) allows input from other computers and database servers.

4.1.2 Memory Unit

The main function of the memory unit is to Stores programs and data.
Two types of storage:
1. Primary Memory (Main Memory)
2. Secondary Storage
Primary Memory (Main Memory)
 Fast memory operating at electronic speeds.
 Programs must be loaded here for execution.
 Made of semiconductor storage cells → each stores 1 bit.
 Cells are grouped into words (typical word length: 16, 32, or 64 bits).
 Each word has a unique address, starting from 0.
 Accessed by specifying the address and using a control command.
 Random Access Memory (RAM) allows quick access to any word in fixed time, independent of
location.
 Memory access time: few nanoseconds to about 100 ns.
Cache Memory
 A smaller, faster RAM near or on the processor chip.
 Holds program sections and associated data for quick access.
 Improves instruction execution rate.
 Instructions and data are copied from main memory to cache during execution.
 Frequently used instructions/data (e.g. in loops) are fetched faster when available in cache.
Secondary Storage
 Used for large amounts of data and programs.
 Cheaper and permanent storage, unlike primary memory.
 Information is retained even when power is off.
 Access time is slower than primary memory.
Examples: Magnetic disks, Optical disks (DVD, CD), Flash memory devices
4.1.3 Arithmetic and Logic Unit
Most computer operations are executed in the arithmetic and logic unit (ALU) of the processor. Any

arithmetic or logic operation, such as addition, subtraction, multiplication, Division and Comparison of
numbers

 Operands (data) are brought from memory into the processor → operation is performed by the
ALU.
 Example: Two numbers from memory are added in the ALU → result stored back in memory or
used immediately.

 Registers are High-speed storage elements inside the processor.

 Each register holds one word of data.
 Access time to registers is faster than cache memory.
 Used to store operands temporarily during computation.

4.1.4 Output Unit

 The output unit sends processed results from the computer to the outside world.
 Example: Printer → produces hard copies of text or graphics.
Types:
 Laser printers (photocopying technique)

 Inkjet printers (ink streams)

 Speed: 20 or more pages per minute, but slower than processor speed.
 Some devices perform both input and output functions:
o Graphic displays → show text/graphics and receive touch input.

o Such devices are often called Input/Output (I/O) units due to their dual role.

4.1.5 Control Unit

 Control Unit Coordinates operations between memory, ALU, and I/O units.
 Acts as the nerve center of the computer:
 Sends control signals.
 Monitors states of other units.
 Manages I/O transfers using program instructions:
 Identifies devices.
 Controls data transfer timing.
 Generates timing signals for data transfers and synchronization.
 Controls data flow between memory and processor.
 Though logically a separate unit, control circuits are physically distributed throughout the computer.
 Uses a large set of control lines (wires) for communication and synchronization.
The operation of a computer can be summarized as follows:
 The computer receives programs and data through the input unit and stores them in memory.
 The stored data is fetched by the ALU under program control for processing.
 The processed data is sent out through the output unit.
 All operations are controlled by the control unit

4.2 BASIC OPERATIONAL CONCEPTS:

With a neat diagram, analyze the basic operational concepts of a computer. List the operating
steps.

The program to be executed is stored in memory. Instructions are accessed from memory to the
processor one by one and executed.
STEPS FOR INSTRUCTION EXECUTION
Consider the following instruction
Ex: 1 Add LOCA, R0

This instruction is in the form of the following instruction format

Opcode Source, Destination
Where Add is the operation code, LOCA is the Memory operand and R0 is Register operand
This instruction adds the contents of memory location LOCA with the contents of Register R0
and the result is stored in R0 Register.
The symbolic representation of this instruction is
R0 [LOCA] + [R0]
The contents of memory location LOCA and Register R0 before and after the execution of this
instruction is as follows:
Before instruction execution After instruction execution
LOCA = 23H LOCA = 23H
R0 = 22H R0 = 45H

Ex:2 Add R1, R2, R3

This instruction is in the form of the following instruction format
Opcode, Source-1, Source-2, Destination
Where R1 is Source Operand-1, R2 is the Source Operand-2 and R3 is the Destination. This
instruction adds the contents of Register R1 with the contents of R2 and the result is placed in
R3 Register.
The symbolic representation of this instruction is
 R3 [R1] + [R2]
The contents of Registers R1,R2,R3 before and after the execution of this instruction is as
follows.

Before instruction execution. After instruction execution

R1 = 24H R1 = 24H
R2 = 34H R2 = 34H
R3 = 38H R3 = 58H

The steps for instruction execution is as follows

• Fetch the instruction from memory into the IR.
• Decode the instruction
• Access the First Register Operand R1
• Access the Second Register Operand R2
• Perform the operation according to the Operation Code.
• Store the result into the Destination Register R3.

4.2.1 CONNECTION BETWEEN MEMORY AND PROCESSOR

With a neat diagram, explain the bus structure of computer and its components

The connection between Memory and Processor is as shown in the figure.

The Processor consists of different types of registers.
• MAR (Memory Address Register)
• MDR (Memory Data Register)
• Control Unit
• PC (Program Counter)
• General Purpose Registers
• IR (Instruction Register)
• ALU (Arithmetic and Logic Unit)
 Fig 4.2 Connection between Processor and memory

The functions of these components are as follows

MAR – Memory Address Register
• It establishes communication between Memory and Processor
• It stores the address of the Memory Location as shown in the figure.
MAR
Memory
5000h 5000 23h
5001 43h
5002 78h
5003 65h
MDR – Memory Data Register
 It also establishes communication between Memory and the Processor.
 It stores the contents of the memory location (data or operand), written into or read from
memory as shown in the figure.

MDR
Memory
23h 5000
23h
43h 5001
78h 5002
65h 5003
CONTROL UNIT
 It controls the data transfer operations between memory and the processor.
 It controls the data transfer operations between I/O and processor.
 It generates control signals for Memory and I/O device

PC (PROGRAM COUNTER)
 It is a special purpose register used to hold the address of the next instruction to be
executed.
 The contents of PC are incremented by 1 or 2 or 4, during the execution of current
instruction.
 The contents of PC are incremented by 1 for 8 bit CPU, 2 for 16 bit CPU and for 4 for 32
bit CPU.

GENERAL PURPOSE REGISTER / REGISTER ARRAY

The structure of register file is as shown in the figure

R0
R1
R2
.
Rn-1

 It consists of set of registers.

 A register is defined as group of flip flops. Each flip flop is designed to store 1 bit
of data.
 It is a storage element.
 It is used to store the data temporarily during the execution of the program(eg: result).
 It can be used as a pointer to Memory.
 The Register size depends on the processing speed of the CPU
 EX: Register size = 8 bits for 8 bit CPU

IR (INSTRUCTION REGISTER)

It holds the instruction to be executed. It notifies the control unit, which

generates timing signals that controls various operations in the execution of
that instruction.

ALU (ARITHMETIC and LOGIC UNIT)

It performs arithmetic and logical operations on given data.
Steps for reading the instruction.
PC contents are transferred to MAR and read signal is sent to memory by control unit. The data
from memory location is read and sent to MDR.
The content of MDR is moved to IR.
[PC]  MAR Memory  MDR  IR
CU ( read signal)
4.3 BUS STRUCTURE
Bus is defined as set of parallel wires used for data communication between different parts of
computer. Each wire carries 1 bit of data. There are 3 types of buses, namely
1. Address bus
2. Data bus and
3. Control bus.
Address bus :
 It is unidirectional.
 The processor (CPU) sends the address of an I/O device or Memory device by means of
this bus.
Data bus
 It is a bidirectional bus.
 The CPU sends data from Memory to CPU and vice versa as well as from I/O to
CPU and vice versa by means of this bus.
Control bus:
This bus carries control signals for Memory and I/O devices. It generates control signals for
Memory namely MEMRD and MEMWR and control signals for I/O devices namely IORD and
IOWR.
The structure of single bus organization is as shown in the figure.

Fig: 4.3 Single Bus structure

 The I/O devices, Memory and CPU are connected to this bus is as shown in the figure.
 It establishes communication between two devices, at a time.
Features of Single bus organization are
 Less Expensive
 Flexible to connect I/O devices.
 Poor performance due to single bus.
There is a variation in the devices connected to this bus in terms of speed of operation. Few
 devices like keyboard, are very slow. Devices like optical disk are faster. Memory and processor
are faster, but all these devices uses the same bus.

Hence to provide the synchronization between two devices, a buffer register is attached to each
device. It holds the data temporarily during the data transfer between two device.

4.4 PERFORMANCE
List the factors affecting the performance of Computer and discuss the methods to improve the
performance of the processor

 The performance of a Computer System is based on hardware design of the processor

and the instruction set of the processors.
 To obtain high performance of computer system it is necessary to reduce the execution
time of the processor.
 Execution time: It is defined as total time required executing one complete program.
 The processing time of a program includes time taken to read inputs, display outputs,
system services, execution time etc.
 The performance of the processor is inversely proportional to execution time of the
processor.
More performance = Less Execution
time. Less Performance = More
Execution time.

The Performance of the Computer System is based on the following factors

1. Cache Memory
2. Processor clock
3. Basic Performance Equation
4. Instructions
5. Compiler

4.4.1 CACHE MEMORY: It is defined as a fast access memory located in between CPU and
Memory. It is part of the processor as shown in the fig
 Fig 4.4 : Processor Cache
The processor needs more time to read the data and instructions from main memory because
main memory is away from the processor as shown in the figure. Hence it slowdown the
performance of the system.
The processor needs less time to read the data and instructions from Cache Memory because it is
part of the processor. Hence it improves the performance of the system.

4.4.2 PROCESSOR CLOCK:

The processor circuits are controlled by timing signals called as Clock. It defines constant time
intervals and are called as Clock Cycles. To execute one instruction there are 3 basic steps
namely
1. Fetch

2. Decode
3. Execute.
The processor uses one clock cycle to perform one operation as shown in the
figure Clock Cycle → T1 T2 T3
Instruction → Fetch Decode Execute
The performance of the processor depends on the length of the clock cycle. To obtain
high performance reduce the length of the clock cycle. Let ‘ P ’ be the number of clock cycles
generated by the Processor and ‘ R ‘ be the Clock rate .

The Clock rate is inversely proportional to the number of clock cycles.

i.e R = 1/P.
Cycles/second is measured in Hertz (Hz). Eg: 500MHz, 1.25GHz.

Two ways to increase the clock rate –

 Improve the IC technology by making the logical circuit work faster, so that the time
taken for the basic steps reduces.
 Reduce the clock period, P.
4.4.3 BASIC PERFORMANCE EQUATION
Discuss the performance metrics of Computer. Explain SPEC Rating of
a computer.
Let ‘ T ‘ be total time required to execute the program.
Let ‘N ‘ be the number of instructions contained in the program.
Let ‘ S ‘ be the average number of steps required to one
instruction.
Let ‘ R’ be number of clock cycles per second generated by the processor to execute one
program.
Processor Execution Time is given by
T=N*S/R
This equation is called as Basic Performance Equation.

For the programmer the value of T is important. To obtain high performance it is necessary to
reduce the values of N & S and increase the value of R
Performance of a computer can also be measured by using benchmark programs.
SPEC (System Performance Evaluation Corporation) is an non-profitable organization, that
measures performance of computer using SPEC rating. The organization publishes the
application programs and also time taken to execute these programs in standard systems.

𝑆𝑃𝐸𝐶 𝑅𝑢𝑛𝑛𝑖𝑛𝑔
=
𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑓 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 𝐶𝑜𝑚𝑝𝑢𝑡𝑒𝑟
𝑡𝑖𝑚𝑒 𝑜𝑓 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 𝑢𝑛𝑑𝑒𝑟 𝑡𝑒𝑠𝑡

4.4.4 Clock Rate

1. Improve the integrated-circuit (IC) technology to make the circuits faster, which reduces the
time required to complete a basic step.
 This allows clock period P to be reduced and Clock rate R to be increased.
2. Reducing the amount of processing done in 1 basic step also makes it possible to reduce the clock
period P.

4.4.5 Performance Measurement

 Processor execution time T is difficult to compute.
 Measure computer performance using benchmark programs.
 Performance measure is the time it takes to execute a benchmark program.
 Benchmark programs are standardized programs like games, compiler, database application,
intensive programs in astro physics and quantum chemistry.
 System Performance Evaluation Corporation (SPEC) is an non-profitable organization, that
measures performance of computer using SPEC rating.
 It selects and publishes representative application programs for different application domains,
 together with test results for many commercially available computers.
 In each case program is Compiled for the computer under test, and the running time on real
computer is measured.
 The same is also compiled and run on one computer selected as reference.

• If SPEC rating = 50
• Then the computer under test runs 50 times faster than reference computer.
• The test is repeated for all the programs in the SPEC suite! And geometric mean of the
results is computed.
• SPECi = rating for program i in the suite
n = number of programs in the suite

4.5 MEMORY LOCATIONS AND ADDRESSES

• Memory is a storage device. It is used to store character operands, data operands and
instructions.
• It consists of number of semiconductor cells and each cell holds 1 bit of information. A
group of 8 bits is called as byte and a group of 16 or 32 or 64 bits is called as word.
What is word length? Explain with neat diagram memory organization of the computer.
World length = 16 for 16 bit CPU and World length = 32 for 32 bit CPU. Word length is
defined as number of bits in a word.
 Memory is organized in terms of bytes or words.
 The organization of memory for 32 bit processor is as shown in the fig4.5

Fig: 4.5
The contents of memory location can be accessed for read and write operation. The memory is
accessed either by specifying address of the memory location or by name of the memory location.
Address space: It is defined as number of bytes accessible to CPU and it depends on the number
of address lines.
4.5.1 BYTE ADDRESSABILITY
Each byte of the memory are addressed, this addressing used in most computers are called byte
addressability. Hence Byte Addressability is the process of assignment of address to successive
bytes of the memory. The successive bytes have the addresses 1, 2, 3, 4….............2n-1. The
memory is accessed in words.

In a 32 bit machine, each word is 32 bit and the successive addresses are 0,4,8,12,… and so on.

Address 32 – bit word

0000 0th byte 1st byte 2nd byte 3rd byte

0004 4th byte 5th byte 6th byte 7th byte
0008 8th byte 9th byte 10th byte 11th byte
0012 12th byte 13th byte 14th byte 15th byte
….. ….. ….. ….. …..
n-3 n-3th byte n-2th byte n-1th byte nth byte

4.5.2 BIG ENDIAN and LITTLE ENDIAN ASSIGNMENT

Analyze Big Endian and Little Endian methods of byte addressing with relevant example.

Two ways in which a word is stored in memory.

1. Big endian
2. Little endian

BIG ENDIAN ASSIGNMENT

In this technique lower byte of data is assigned to higher address of the memory and higher byte
of data is assigned to lower address of the memory
The structure of memory to represent 32 bit number for big endian assignment is as shown in the
above figure.

LITTLE ENDIAN ASSIGNMENT

In this technique lower byte of data is assigned to lower address of the memory and higher byte of
data is assigned to higher address of the memory.
The structure of memory to represent 32 bit number for little endian assignment is as shown in the
fig.

Eg – store a word “JOHNSENA” in memory starting from word 1000, using Big Endian and
Little endian.
Bigendian -
1000 J O H N
1000 1001 1002 1003
1004 S E N A
1004 1005 1006 1007

Little endian -
1000 J O H N
1003 1002 1001 1000
1004 S E N A
1007 1006 1005 1004

4.5.3 WORD ALLIGNMENT

The structure of memory for 16 bit CPU, 32 bit CPU and 64 bit CPU are as shown in the figures 1,2
and 3 respectively

For 16 bit CPU For 32 bit CPU For 64 bit CPU

5000 34H 5000 34H 5000 34H
5002 65H 5004 65H 5008 65H
5004 86H 5008 86H 5016 86H
5006 93H 5012 93H 5024 93H
5008 45H 5016 45H 5032 45H

It is process of assignment of addresses of two successive words and this address is the number of
bytes in the word is called as Word alignment.

4.5.4 Accessing Characters , Numbers and Character Strings

The character occupies 1 byte of memory and hence byte address for memory.
The numbers occupies 2 bytes of memory and hence word address for
numbers.
Character strings of variable length are handled by:
 Giving the address of the byte with the first character.
 Successive byte locations contain the following characters.
Two methods to indicate the length of a string:
1. Use a special control character (like “end of string”) as the last character.
2. Store the length of the string (in bytes) in a memory location or processor
register.

4.6 MEMORY OPERATION

 Both program instructions and data operands are stored in memory.
 The processor moves instructions and data between memory and itself during execution.
 Two basic memory operations:
1. Load (Read or Fetch) – Transfers a copy of data from memory to the processor without
altering memory contents.
2. Store (Write) – Transfers data from the processor to memory, replacing the previous
content.

Load Operation
 Transfers data from a memory location to the processor.
 Memory contents stay unchanged.
 Processor sends the memory address → memory reads and sends data.

Store Operation
 Transfers data from the processor to a memory location.
 Overwrites existing data at that location.
 Processor sends address and data → memory writes the data.
Data Transfer Details
  One word or one byte can be transferred in a single operation.
 Processor registers hold the source or destination data.
 Bytes are usually placed in the low-order (rightmost) position of the register during
transfer.

4.7 Instructions and Instruction Sequencing

A computer must support four types of operations:

1. Data transfer between memory and processor registers.
2. Arithmetic and logic operations on data.
3. Program sequencing and control (managing the order of execution).
4. I/O transfers (input and output operations).

4.7.1 Register transfer Notation

 Register transfer notation is used to describe how information is transferred between different
locations in a computer.
 Possible locations include:
 Memory locations
 Processor registers
 I/O registers
 Each location is identified by a symbolic name representing its hardware address:
 Example memory names: LOC, PLACE, A, VAR2.
 Example processor register names: R0, R5.
 Example I/O register names: DATAIN, OUTSTATUS.
 Contents of a location are shown by placing square brackets around its name:
 Example:
R1 ← [LOC] → contents of memory location LOC are transferred to processor register R1.
 Example of addition operation:
R3 ← [R1] + [R2]
→ adds contents of R1 and R2, and stores the result in R3.
 In RTN:
 The right-hand side denotes the value being transferred.
 The left-hand side denotes the destination location where the value is stored, overwriting
any previous data.

4.7.2 ASSEMBLY LANGUAGE NOTATION

Assembly language is a type of notation used to represent machine instructions and programs.
 The instruction "Move LOC, R1" transfers the contents from memory location LOC to
 processor register R1. The contents of LOC are unchanged, and the old contents of R1 are
overwritten.
 The instruction "Add R1, R2, R3" adds the contents of processor registers R1 and R2 and
places the sum in register R3.

4.7.3 BASIC INSTRUCTION TYPES

Explain with examples various instruction types

There are 3 types basic instructions namely

1. Three address instruction format
2. Two address instruction format
3. One address instruction format

Consider the arithmetic expression Z = A + B, Where A,B,Z are the Memory locations.
Steps for evaluation
1. Access the first memory operand whose symbolic name is given by A.
2. Access the second memory operand whose symbolic name is given by B.
3. Perform the addition operation between two memory operands.
4. Store the result into the 3rd memory location Z.
5. The mathematical representation is Z ←[A] + [B].
a) Three address instruction format : Its format is as follows
opcode Source-1 Source-2 destination

Destination ← [source-1] + [source-2]

Ex: ADD A, B, Z
Z ← [A] + [B]

a) Two address instruction format : Its format is as follows

opcode Source Source/destination

Destination ← [source] + [destination]

The sequence of two address m/c instructions to evaluate the arithmetic expression
Z ← A + B are as follows
MOV A, R0
MOV B, R1
ADD R0, R1
MOV R1, Z

b) One address instruction format : Its format is as follows

opcode operand

Ex1: LOAD B
This instruction copies the contents of memory location whose symbolic name is given
by ‘B’ into the Accumulator as shown in the figure.
 The mathematical representation of this instruction is as follows
ACC ← [B]

Accumulator Memory

Ex2: STORE B
This instruction copies the contents of Accumulator into memory location whose
symbolic name is given by ‘B’ as shown in the figure. The mathematical representation is as
follows
B ← [ACC].
Memory
Accumulator

Ex3: ADD B
 This instruction adds the contents of Accumulator with the contents of Memory
location ‘B’ and result is stored in Accumulator.
 The mathematical representation of this instruction is as
follows ACC ←[ACC]+ [B]

4.7.4 INSTRUCTION EXECUTION & STRAIGHT-LINE SEQUENCING

In a computer system, programs are stored in memory as a sequence of instructions. Each

instruction usually occupies 4 bytes, and successive instructions are placed in successive word
locations. For example, consider the task C ← [A] + [B], which requires three instructions stored
at addresses i, i + 4, and i + 8. The data values for A, B, and C are also stored separately in
memory.
The execution of instructions is controlled by a special register called the Program Counter
(PC), which always holds the address of the next instruction to be executed. At the beginning of
program execution, the PC is loaded with the address of the first instruction (i). After each
instruction is executed, the PC is automatically incremented by 4 to point to the next instruction.
This step-by-step execution of instructions in order of increasing addresses is called straight-line
sequencing. For instance, after the instruction at i + 8 is executed, the PC will hold i + 12, which
is the address of the next program segment.
The execution of each instruction follows a two-phase cycle:
 1. Instruction Fetch – The instruction is fetched from memory at the address contained in the
PC and placed into the Instruction Register (IR).
2. Instruction Execute – The instruction in the IR is decoded and executed. The processor
may read data from memory or registers, perform arithmetic or logic operations, and store
results back in memory or registers.
In the example program (Figure 4.6 ):
The first instruction moves the contents of memory location A into register R0.
The second instruction adds the contents of memory location B to register R0.
The third instruction stores the result from R0 into memory location C.
Thus, using the PC, IR, and the fetch–execute cycle, the computer systematically carries out the
program step by step, achieving the task C ← [A] + [B].

Fig 4.6: A Program for c =[A]+[B]

4.7.5 BRANCHING
Suppose a list of ‘N’ numbers have to be added. Instead of adding one after the other, the
add statement can be put in a loop. The loop is a straight-line of instructions executed as many
times as needed.
 Fig 4.7: Using a loop to add n numbers

The ‘N’ value is copied to R1 and R1 is decremented by 1 each time in loop. In the loop find the
value of next element and add it with Ro.
In conditional branch instruction, the loop continues by coming out of sequence only if
the condition is true. Here the PC value is set to ‘LLOP’ if the condition is true.

Branch > 0 LOOP // if >0 go to LOOP

The PC value is set to LOOP, if the previous statement value is >0 ie. after decrementing R1
value is greater than 0.

If R1 value is not greater than 0, the PC value is incremented in a mormal sequential way and the
next instruction is executed.
4.7.6 CONDITION CODES
 The processor consists of series of flip-flops to store the status information after ALU
operation.
 It keeps track of the results of various operations, for subsequent usage.
 The series of flip-flip-flops used to store the status and control information of the
processor is called as “Condition Code Register”. It defines 4 flags. The format of condition
code register is as follows

C V Z N

N (NEGATIVE) Flag:
• It is designed to differentiate between positive and negative result.
• It is set 1 if the result is negative, and set to 0 if result is positive.

Z (ZERO) Flag:
It is set to 1 when the result of an ALU operation is found to zero, otherwise it is cleared.

V (OVER FLOW) Flag:

In case of 2s Complement number system n-bit number is capable of representing a range of
numbers and is given by -2n-1 to +2n-1. . The Over-Flow flag is set to 1 if the result is found to be
out of this range.

C (CARRY) Flag :
This flag is set to 1 if there is a carry from addition or borrow from subtraction, otherwise it is
cleared.

4.8 Addressing Modes

What is addressing mode? Explain all types of addressing modes with suitable examples.

The various formats of representing operand in an instruction or location of an operand is called

as “Addressing Mode”. The different types of Addressing Modes are

a) Register Addressing
b) Direct Addressing
c) Immediate Addressing
d) Indirect Addressing
e) Index Addressing
f) Relative Addressing
g) Auto Increment Addressing
h) Auto Decrement Addressing

a. REGISTER ADDRESSING:
In this mode operands are stored in the registers of CPU. The name of the register is directly
specified in the instruction.
Ex: MOVE R1,R2 Where R1 and R2 are the Source and Destination registers respectively. This
instruction transfers 32 bits of data from R1
register into R2 register. This instruction does not
refer memory for operands. The operands are
directly available in the registers.
 b. DIRECT ADDRESSING
It is also called as Absolute Addressing Mode. In this addressing mode operands are stored in the
memory locations. The name of the memory location is directly specified in the instruction.

Ex: MOVE LOCA, R1 : Where LOCA is the memory location and R1 is the Register.

This instruction transfers 32 bits of data from memory location X into the General Purpose
Register R1.

c. IMMEDIATE ADDRESSING
In this Addressing Mode operands are directly specified in the instruction. The source field is
used to represent the operands. The operands are represented by # (hash) sign.

Ex: MOVE #23, R0

d. INDIRECT ADDRESSING
In this Addressing Mode effective address of an operand is stored in the memory location or
General-Purpose Register.

The memory locations or GPRs are used as the memory pointers.

Memory pointer: It stores the address of the memory location.

There are two types Indirect Addressing

i) Indirect through GPRs

ii) Indirect through memory location
 i) Indirect Addressing Mode through GPRs
In this Addressing Mode the effective address of an operand is stored in the one of the General

Purpose Register of the CPU.

Ex: ADD (R1), R0 ; Where R1 and R0 are GPRs

This instruction adds the data from the memory location whose address is stored in R1 with the
contents of R0 Register and the result is stored in R0 register as shown in the fig.

The diagrammatic representation of this addressing mode is as shown in the

fig.

Fig 4.8 Through General purpose register

ii) Indirect Addressing Mode through Memory Location.

In this Addressing Mode, effective address of an operand is stored in the memory

location. Ex: ADD (X), R0

This instruction adds the data from the memory location whose address is stored in ‘X’
memory location with the contents of R0 and result is stored in R0 register.
 The diagrammatic representation of this addressing mode is as shown in the fig.

Fig 4.9 Through Memory location

e. INDEX ADDRESSING MODE

In this addressing mode, the effective address of an operand is computed by adding constant
value with the contents of Index Register and any one of the General Purpose Register namely
R0 to Rn-1 can be used as the Index Register. The constant value is directly specified in the
instruction.
The symbolic representations of this mode are as follows

1.
X (Ri) where X is the Constant value and Rj is the GPR.
It can be represented as
EA of an operand = X + (Ri )
2.
(Ri , RJ) Where Ri and Rj are the General Purpose Registers used to store
addresses of an operand and constant value respectively. It can be represented as
The EA of an operand is given by
EA = (Ri) + (Rj)
3.
X (Ri , Rj) Where X is the constant value and RI and RJ are the General Purpose Registers
used to store the addresses of the [Link] can be represented as
The EA of an operand is given
by EA = (Ri) + (Rj) + X
There are two types of Index Addressing Modes

i) Offset is given as constant.

ii) Offset is in Index Register.
 Logic Design and Computer Organization

Note : Offset : It is the difference between the starting effective address of the memory
location and the effective address of the operand fetched from memory.

i) Offset is given as constant

Ex: ADD 20(R1), R2

The EA of an operand is given by
EA = 20 + [R1]

This instruction adds the data from the memory location whose address is given by [1000
+
[R1] with the contents of R2 and result is placed in R2 register.

The diagrammatic representation of this mode is as shown in the fig.

This instruction adds the contents of memory location whose EA is the sum of contents of
R1 with 20 and with the contents of R2 and result is placed in R2 register. The
diagrammatic representation of this mode is as shown in the fig.

Fig 4.10 offset is given as a constant

ii) Offset is in Index Register
Ex: ADD 1000(R1) , R2 R1 holds the offset address of an
operand. The EA of an operand is given by
EA = 1000 + [R1]
 Logic Design and Computer Organization

Fig 4.11 offset in the index register

f. RELATIVE ADDRESSING MODE:

In this Addressing Mode EA of an operand is computed by the Index Addressing Mode.
This Addressing Mode uses PC (Program Counter)to store the EA of the next instruction
instead of GPR.

The symbolic representation of this mode is X (PC).Where X is the offset value and PC
is the Program Counter to store the address of the next instruction to be executed.

It can be represented as
EA of an operand = X + (PC).
This Addressing Mode is useful to calculate the EA of the target memory location.

g. AUTO INCREMENT ADDRESSING MODE

In this Addressing Mode , EA of an operand is stored in the one of the GPR s of the CPU.
This Addressing Mode increment the contents of memory register by 4 memory locations
after operand access.
The symbolic representation is
(RI)+ Where Ri is the one of the
GPR. Ex: MOVE (R1)+ , R2

This instruction transfer’s data from the memory location whose address is stored in R 1
into R3 register and then it increments the contents of R1 by 4 memory locations.
 Logic Design and Computer Organization

h. AUTO DECREMENT ADDRESSING MODE

In this Addressing Mode , EA of an operand is stored in the one of the GPR s of the CPU.
This Addressing Mode decrements the contents of memory register by 4 memory
locations and then transfers the data to destination.

The symbolic representation is

-(RI) Where Ri is the one of
the GPR. Ex: MOVE -
(R1) , R2
This instruction first decrements the contents of R1 by 4 memory locations and then
transfer’s data of that location to destination register.