CMOS TECHNOLOGY – COMPLETE NOTES FOR
VLSI DESIGN
1. Introduction to CMOS
CMOS (Complementary Metal Oxide Semiconductor) technology is the most widely used technology in
modern digital integrated circuits. It is used in microprocessors, microcontrollers, memory devices, and
system-on-chip (SoC) designs due to its low power consumption, high noise immunity, and high packing
density.
CMOS uses two types of MOSFETs: - NMOS (n-channel MOSFET) - PMOS (p-channel MOSFET)
These transistors are arranged in a complementary manner so that ideally no direct current flows from
supply to ground in steady state.
2. MOSFET Basics
A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) consists of four terminals: - Gate (G) -
Drain (D) - Source (S) - Body (B or Substrate)
The gate is isolated from the channel by a thin oxide layer, which results in very high input impedance.
2.1 NMOS Operation
In NMOS, when the gate-to-source voltage (VGS) exceeds the threshold voltage (VTH), an inversion layer
of electrons is formed, allowing current to flow from drain to source.
2.2 PMOS Operation
In PMOS, when VGS is more negative than the threshold voltage, a hole inversion layer is formed,
allowing current conduction.
3. CMOS Inverter
The CMOS inverter is the fundamental building block of all digital circuits.
3.1 Structure
A CMOS inverter consists of: - One PMOS transistor connected to VDD - One NMOS transistor connected
to GND
Both gates are connected together as input, and both drains are connected together as output.
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3.2 Working
• Input = LOW → PMOS ON, NMOS OFF → Output = HIGH
• Input = HIGH → PMOS OFF, NMOS ON → Output = LOW
3.3 Advantages
• Very low static power consumption
• High noise margin
• Full voltage swing
4. CMOS Fabrication Process
The CMOS fabrication process involves several steps:
1. Wafer preparation
2. Oxidation
3. Photolithography
4. Etching
5. Doping (Ion implantation)
6. Deposition of metal layers
7. Passivation
Both NMOS and PMOS devices are fabricated on the same silicon substrate using twin-well or triple-well
processes.
5. CMOS Logic Gates
Using CMOS inverter principles, various logic gates can be designed.
5.1 NAND Gate
• Parallel NMOS network
• Series PMOS network
5.2 NOR Gate
• Series NMOS network
• Parallel PMOS network
NAND and NOR gates are preferred because they are efficient and easy to fabricate.
6. Power Dissipation in CMOS
CMOS power dissipation consists of:
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6.1 Dynamic Power
Occurs due to charging and discharging of load capacitance.
P_dynamic = α · C_L · VDD² · f
Where: - α = switching activity factor - C_L = load capacitance - f = frequency
6.2 Static Power
Caused by leakage currents such as subthreshold leakage and gate oxide leakage.
7. CMOS Noise Margin
Noise margin is the measure of a circuit’s tolerance to noise.
• NMH = VOH(min) − VIH(min)
• NML = VIL(max) − VOL(max)
CMOS circuits provide large noise margins compared to other logic families.
8. Advantages of CMOS Technology
• Low power consumption
• High integration density
• High reliability
• Wide operating voltage range
• Low heat generation
9. Disadvantages of CMOS Technology
• Sensitive to electrostatic discharge (ESD)
• More complex fabrication process
• Performance degrades at very high frequencies
10. Applications of CMOS
• Microprocessors and microcontrollers
• Memory devices (RAM, ROM, Flash)
• Digital signal processors (DSP)
• Mobile phones and IoT devices
• VLSI and ULSI systems
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11. CMOS Scaling and Moore’s Law
CMOS scaling refers to reducing transistor dimensions to improve performance and density.
Challenges in deep submicron technology: - Short channel effects - Leakage currents - Power density
issues
Advanced solutions include FinFETs and GAAFETs.
12. Conclusion
CMOS technology forms the backbone of modern electronics. Its low power consumption, scalability,
and robustness make it the preferred choice for digital IC design. Continuous advancements in
fabrication and device architecture ensure CMOS remains relevant for future technologies.
13. References
1. Douglas A. Pucknell – Basic VLSI Design
2. Neil H. E. Weste – CMOS VLSI Design
3. Rabaey – Digital Integrated Circuits