Computer System Architecture

UNIT – V
Microprocessor

Microprocessor - 8085 Architecture

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed
by Intel in 1977 using NMOS technology. The architecture of 8085 microprocessor mainly
includes the timing & control unit, Arithmetic and logic unit, decoder, instruction register,
interrupt control, a register array, serial input/output control. The most important part of the
microprocessor is the central processing unit.

It has the following configuration −

 8-bit data bus
 16-bit address bus, which can address upto 64KB
 A 16-bit program counter
 A 16-bit stack pointer
 Six 8-bit registers arranged in pairs: BC, DE, HL
 Requires +5V supply to operate at 3.2 MHZ single phase clock

It is used in washing machines, microwave ovens, mobile phones, etc.

Operations of 8085 Microprocessor

The main operation of ALU is arithmetic as well as logical which includes addition, increment,
subtraction, decrement, logical operations like AND, OR, Ex-OR, complement, evaluation, left shift
or right shift. Both the temporary registers as well as accumulators are utilized for holding the
information throughout in the operations then the outcome will be stored within the accumulator.
The different flags are arranged or rearrange based on the outcome of the operation.
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8085 Microprocessor – Functional Units

8085 consists of the following functional units −
1. Accumulator - It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE
operations. It is connected to internal data bus & ALU.

2. Arithmetic and logic unit - As the name suggests, it performs arithmetic and logical operations
like Addition, Subtraction, AND, OR, etc. on 8-bit data.

3. General purpose registers - There are 6 general purpose registers in 8085 processor, i.e. B, C, D,
E, H & L. Each register can hold 8-bit data.
These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E
& H-L.
4. Program counter - It is a 16-bit register used to store the memory address location of the next
instruction to be executed. Microprocessor increments the program whenever an instruction is
being executed, so that the program counter points to the memory address of the next instruction
that is going to be executed.

5. Stack pointer - It is also a 16-bit register works like stack, which is always
incremented/decremented by 2 during push & pop operations.

6. Temporary register - It is an 8-bit register, which holds the temporary data of arithmetic and
logical operations.
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7. Flag register - It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.
These are the set of 5 flip-flops −
 Sign (S)
 Zero (Z)
 Auxiliary Carry (AC)
 Parity (P)
 Carry (C)

Its bit position is shown in the following table −

D7 D6 D5 D4 D3 D2 D1 D0

S Z AC P CY

8. Instruction register and decoder - It is an 8-bit register. When an instruction is fetched from
memory then it is stored in the Instruction register. Instruction decoder decodes the information
present in the Instruction register.

9. Timing and control unit - It provides timing and control signal to the microprocessor to perform
operations. Following are the timing and control signals, which control external and internal
circuits −
 Control Signals: READY, RD’, WR’, ALE
 Status Signals: S0, S1, IO/M’
 DMA Signals: HOLD, HLDA
 RESET Signals: RESET IN, RESET OUT

10. Interrupt control - As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs, the
microprocessor shifts the control from the main program to process the incoming request. After
the request is completed, the control goes back to the main program.
There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

11. Serial Input/output control - It controls the serial data communication by using these two
instructions: SID (Serial input data) and SOD (Serial output data).

12. Address buffer and address-data buffer - The content stored in the stack pointer and program
counter is loaded into the address buffer and address-data buffer to communicate with the CPU.
The memory and I/O chips are connected to these buses; the CPU can exchange the desired data
with the memory and I/O chips.

13. Address bus and data bus - Data bus carries the data to be stored. It is bidirectional, whereas
address bus carries the location to where it should be stored and it is unidirectional. It is used to
transfer the data & Address I/O devices.
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8085 Pin Configuration

The following image depicts the pin diagram of 8085 Microprocessor −

The pins of a 8085 microprocessor can be classified into seven groups −

1. Address bus - A15-A8, it carries the most significant 8-bits of memory/IO address.

2. Data bus - AD7-AD0, it carries the least significant 8-bit address and data bus.

3. Control and status signals - These signals are used to identify the nature of operation. There
are 3 control signal and 3 status signals.
Three control signals are RD, WR & ALE.
 RD − This signal indicates that the selected IO or memory device is to be read and is ready
for accepting data available on the data bus.
 WR − This signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
 ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes down
it indicates data.

Three status signals are IO/M, S0 & S1.

4. IO/M - This signal is used to differentiate between IO and Memory operations, i.e. when it is
high indicates IO operation and when it is low then it indicates memory operation.
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5. S1 & S0 - These signals are used to identify the type of current operation.
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6. Power supply - There are 2 power supply signals − VCC & VSS. VCC indicates +5v power
supply and VSS indicates ground signal.

7. Clock signals - There are 3 clock signals, i.e. X1, X2, CLK OUT.
 X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
 CLK OUT − This signal is used as the system clock for devices connected with the
microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated by external devices to request the microprocessor to perform a
task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will
discuss interrupts in detail in interrupts section.
 INTA − It is an interrupt acknowledgment signal.
 RESET IN − This signal is used to reset the microprocessor by setting the program counter
to zero.
 RESET OUT − This signal is used to reset all the connected devices when the
microprocessor is reset.
 READY − This signal indicates that the device is ready to send or receive data. If READY
is low, then the CPU has to wait for READY to go high.
 HOLD − This signal indicates that another master is requesting the use of the address and
data buses.
 HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD request
and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD
signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.
 SOD (Serial output data line) − The output SOD is set/reset as specified by the SIM
instruction.
 SID (Serial input data line) − The data on this line is loaded into accumulator whenever a
RIM instruction is executed.
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Timing Diagrams of 8085

 Instruction cycle: this term is defined as the number of steps required by the cpu to complete the
entire process i.e. Fetching and execution of one instruction. The fetch and execute cycles are
carried out in synchronization with the clock.
 Machine cycle: It is the time required by the microprocessor to complete the operation of
accessing the memory devices or I/O devices. In machine cycle various operations like opcode
fetch, memory read, memory write, I/O read, I/O write are performed.
 T-state: Each clock cycle is called as T-states.

Rules to identify number of machine cycles in an instruction:

 If an addressing mode is direct, immediate or implicit then No. of machine cycles = No. of
bytes.
 If the addressing mode is indirect then No. of machine cycles = No. of bytes + 1. Add +1 to the
No. of machine cycles if it is memory read/write operation.
 If the operand is 8-bit or 16-bit address then, No. of machine cycles = No. of bytes +1.
 These rules are applicable to 80% of the instructions of 8085.

Machine cycles of 8085

The 8085 microprocessor has 5 (seven) basic machine cycles. They are
 Opcode fetch cycle (4T)
 Memory read cycle (3 T)
 Memory write cycle (3 T)
 I/O read cycle (3 T)
 I/O write cycle (3 T)

1. Opcode fetch: The microprocessor requires instructions to perform any particular action. In
order to perform these actions microprocessor utilizes Opcode which is a part of an instruction
which provides detail (i.e. which operation µp needs to perform) to microprocessor.
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 Each instruction of the processor has one byte opcode.

 The opcodes are stored in memory. So, the processor executes the opcode fetch machine
cycle to fetch the opcode from memory.
 Hence, every instruction starts with opcode fetch machine cycle.
 The time taken by the processor to execute the opcode fetch cycle is 4T.
 In this time, the first, 3 T-states are used for fetching the opcode from memory and the
remaining T-states are used for internal operations by the processor.

2. Memory Read Machine Cycle of 8085:

 The memory read machine cycle is executed by the processor to read a data byte from
memory.
 The processor takes 3T states to execute this cycle.

The instructions which have more than one byte word size will use the machine cycle after the
opcode fetch machine cycle.
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3. Memory Write Machine Cycle of 8085

 The memory write machine cycle is executed by the processor to write a data byte in a
memory location.
 The processor takes, 3T states to execute this machine cycle.

4. I/O Read Cycle of 8085:

 The I/O Read cycle is executed by the processor to read a data byte from I/O port or from
the peripheral, which is I/O, mapped in the system.
 The processor takes 3T states to execute this machine cycle.
 The IN instruction uses this machine cycle during the execution.

5. IO Write:
 It is used to writ one byte into IO device.
 It requires 3 T-States.
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Instruction Set of 8085

Instruction and Data Format of 8085

Each Instruction and Data Format of 8085 microprocessor has specific information fields. These
information fields of instructions are called elements of instruction. These are :
 Operation code : The operation code field in the instruction specifies the operation to be
performed. The operation is specified by binary code, hence the name operation code or
simply opcode. For example, for 8085 processor operation code for ADD B instruction is
80H.
 Source / destination operand : The source/destination operand field directly specifies the
source/destination operand for the instruction. In 8085, the instruction MOV A,B has B
register contents as a source operand and A register contents as a destination operand
because this instruction copies the contents of register B to register A.
 Source operand address : We know that the operation specified by the instruction may
require one or more operands. The source operand may be in the 8085 register or in the
memory. Many times the instruction specifies the address of the source operand so that
operand(s) can be accessed and operated by the 8085 according to the instruction.

Instruction Formats:
The 8085A instruction set consists of one, two and three byte instructions. The first byte is always
the opcode; in two-byte instructions the second byte is usually data; in three byte instructions the
last two bytes present address or 16-bit data.
1. One byte instruction:

For Example : MOV A, B whose opcode is 78H which is one byte. This Instruction and Data
Format of 8085 copies the contents of B register in A register.

2. Two byte instruction:

For Example : MVI B, 02H. The opcode for this instruction is 06H and is always followed by a
byte data (02H in this case). This instruction is a two byte instruction which copies immediate
data into B register.

3. Three byte instruction:

For Example : JMP 6200H. The opcode for this instruction is C3H and is always followed by
16 bit address (6200H in this case). This instruction is a three byte instruction which loads 16
bit address into program counter.
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Data Formats:
The operand is an another name for data. It may appear in different forms :
 Addresses
 Numbers/Logical data and
 Characters
1. Addresses : The address is a 16-bit unsigned integer ,number used to refer a memory location.

2. Numbers/Data : The 8085 supports following numeric data types.

 Signed Integer : A signed integer number is either a positive number or a negative
number. In 8085, 8-bits are assigned for signed integer, in which most significant bit is
used for sign and remaining seven bits are used for Sign bit 0 indicates positive number
whereas sign bit 1 indicates negative number.

 Unsigned Integer : The 8085 microprocessor supports 8-bit unsigned integer.

 BCD : The term BCD number stands for binary coded decimal number. It uses ten digits
from 0 through 9. The 8-bit register of 8085 can store two digit BCD

3. Characters : The 8085 uses ASCII code to represent characters. It is a 7-bit alphanumeric code
that represents decimal numbers, English alphabets, and other special characters.

Status Flags:
There is a set of five flip-flops which indicate status (condition) arising after the execution of
arithmetic and logic instructions. These are:
 Carry Flag (CS)
 Parity Flag (P)
 Auxiliary Carry Flags (AC)
 Zero Flags (Z)
 Sign Flags (S)

Symbols and Abbreviations:

The symbol and abbreviations which have been used while explaining Intel 8085 instructions are as
follows:

Symbol/Abbreviations Meaning

Addr 16-bit address of the memory location.

Data 8-bit data

data 16 16-bit data

r, r1, r2 One of the registers A, B, C, D, E, H or L

A, B, C, D, H, L 8-bit register

A Accumulator
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H-L Register pair H-L

B-C Register pair B-C

D-E Register pair D-E

PSW Program Status Word

M Memory whose address is in H-L pair

H Appearing at the end of the group of digits specifies

hexadecimal, e.g. 2500H

Rp One of the register pairs.

Rh The high order register of a register pair

Rl The low order register of a register pair

PC 16 bit program counter, PCH is high order 8 bits and PCL low
order 8 bits of register PC.

CS Carry Status

[] The contents of the register identified within bracket

[ [] ] The content of the memory location whose address is in the

register pair identified within brackets

^ AND operation

∨ OR operation

⊕ or ∀ Exclusive OR

← Move data in the direction of arrow

⇔ Exchange contents
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Intel 8085 Instructions

An instruction of a computer is a command given to the computer to perform a specified operation
on given data. In microprocessor, the instruction set is the collection of the instructions that the
microprocessor is designed to execute.
The programmer writes a program in assembly language using these instructions. These instructions
have been classified into the following groups:
1. Data Transfer Group - Instructions which are used to transfer the data from a register to
another register from memory to register or register to memory come under this group.
Examples are: MOV, MVI, LXI, LDA, STA etc. When an instruction of data transfer group is
executed, data is transferred from the source to the destination without altering the contents of
the source. For example, when MOV A, B is executed the content of the register B is copied
into the register A, and the content of register B remains unaltered. Similarly, when LDA 2500
is executed the content of the memory location 2500 is loaded into the accumulator. But the
content of the memory location 2500 remains unaltered.

Instruction Description
MOV r1, r2 (Move Data; Move the content of the one register to another). [r1] <--
[r2]

MOV r, m (Move the content of memory register). r <-- [M]

MOV M, r. (Move the content of register to memory). M <-- [r]

MVI r, data. (Move immediate data to register). [r] <-- data.

MVI M, data. (Move immediate data to memory). M <-- data.

LXI rp, data 16. (Load register pair immediate). [rp] <-- data 16 bits, [rh] <-- 8 LSBs of
data.
LDA addr. (Load Accumulator direct). [A] <-- [addr].

STA addr. (Store accumulator direct). [addr] <-- [A].

LHLD addr. (Load H-L pair direct). [L] <-- [addr], [H] <-- [addr+1].

SHLD addr. (Store H-L pair direct) [addr] <-- [L], [addr+1] <-- [H].

LDAX rp. (LOAD accumulator indirect) [A] <-- [[rp]]

STAX rp. (Store accumulator indirect) [[rp]] <-- [A].
XCHG. (Exchange the contents of H-L with D-E pair) [H-L] <--> [D-E].

2. Arithmetic Group - The instructions of this group perform arithmetic operations such as
addition, subtraction; increment or decrement of the content of a register or memory. Examples
are: ADD, SUB, INR, DAD etc.
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Instruction Description
ADD r. (Add register to accumulator) [A] <-- [A] + [r].
ADD M. (Add memory to accumulator) [A] <-- [A] + [[H-L]].
ADC r. (Add register with carry to accumulator). [A] <-- [A] + [r] + [CS].
ADC M. (Add memory with carry to accumulator) [A] <-- [A] + [[H-L]] [CS].
ADI data (Add immediate data to accumulator) [A] <-- [A] + data.
ACI data (Add with carry immediate data to accumulator). [A] <-- [A] + data +
[CS].
DAD rp. (Add register paid to H-L pair). [H-L] <-- [H-L] + [rp].
SUB r. (Subtract register from accumulator). [A] <-- [A] – [r].

SUB M. (Subtract memory from accumulator). [A] <-- [A] – [[H-L]].

SBB r. (Subtract register from accumulator with borrow). [A] <-- [A] – [r] –
[CS].
SBB M. (Subtract memory from accumulator with borrow). [A] <-- [A] – [[H-L]]
– [CS].
SUI data. (Subtract immediate data from accumulator) [A] <-- [A] – data.
SBI data. (Subtract immediate data from accumulator with borrow). [A] <-- [A] –
data – [CS].
INR r (Increment register content) [r] <-- [r] +1.
INR M. (Increment memory content) [[H-L]] <-- [[H-L]] + 1.
DCR M. (Decrement memory content) [[H-L]] <-- [[H-L]] – 1.
INX rp. (Increment register pair) [rp] <-- [rp] – 1.
DCX rp (Decrement register pair) [rp] <-- [rp] -1.
DAA (Decimal adjust accumulator) .

3. Logical Group - The Instructions under this group perform logical operation such as AND,
OR, compare, rotate etc. Examples are: ANA, XRA, ORA, CMP, and RAL etc.
Instruction Description
ANA r. (AND register with accumulator) [A] <-- [A] ^ [r].
ANA M. (AND memory with accumulator). [A] <-- [A] ^ [[H-L]].
ANI data. (AND immediate data with accumulator) [A] <-- [A] ^ data.
ORA r. (OR register with accumulator) [A] <-- [A] v [r].
ORA M. (OR memory with accumulator) [A] <-- [A] v [[H-L]]
ORI data. (OR immediate data with accumulator) [A] <-- [A] v data.
XRA r. (EXCLUSIVE – OR register with accumulator) [A] <-- [A] v [r]
XRA M. (EXCLUSIVE-OR memory with accumulator) [A] <-- [A] v [[H-
L]]
XRI data. (EXCLUSIVE-OR immediate data with accumulator) [A] <-- [A]
CMA. (Complement the accumulator) [A] <-- [A]
CMC. (Complement the carry status) [CS] <-- [CS]
STC. (Set carry status) [CS] <-- 1.
CMP r. (Compare register with accumulator) [A] – [r]
CMP M. (Compare memory with accumulator) [A] – [[H-L]]
CPI data. (Compare immediate data with accumulator) [A] – data.
RLC (Rotate accumulator left) [An+1] <-- [An], [A0] <-- [A7],[CS] <--
[A7].
RRC. (Rotate accumulator right) [A7] <-- [A0], [CS] <-- [A0], [An] <--
[An+1].
RAL. (Rotate accumulator left through carry) [An+1] <-- [An], [CS] <--
[A7], [A0] <-- [CS].
RAR. (Rotate accumulator right through carry) [An] <-- [An+1], [CS]
<-- [A0], [A7] <-- [CS]
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4. Branch Control Group - This group includes the instructions for conditional and
unconditional jump, subroutine call and return, and restart. Examples are: JMP, JC, JZ, CALL,
CZ, RST etc.
Instruction Description
JMP addr (label). (Unconditional jump: jump to the instruction specified by the address).
[PC] <-- Label
JZ addr (label). (Jump if the result is
zero)
JNZ addr (label) (Jump if the result is not
zero)
JC addr (label). (Jump if there is a carry)
Conditional Jump JNC addr (label). (Jump if there is no
addr (label): 7 states carry)
are required for the JP addr (label). (Jump if the result is
execution of the plus)
instruction. JM addr (label). (Jump if the result is
minus)
JPE addr (label) (Jump if even parity)

JPO addr (label) (Jump if odd parity)

CALL addr (label) (Unconditional CALL: call the subroutine identified by the operand)
RET (Return from subroutine)
RST n (Restart) Restart is a one-word CALL instruction. The content of the
program counter is saved in the stack. The program jumps to the
instruction starting at restart location.

5. Stack, I/O and Machine Control Group - This group includes the instructions for
input/output ports, stack and machine control. Examples are: IN, OUT, PUSH, POP, and HLT
etc.
Instruction Description
IN port-address. (Input to accumulator from I/O port) [A] <-- [Port]
OUT port-address (Output from accumulator to I/O port) [Port] <-- [A]
PUSH rp (Push the content of register pair to stack)
PUSH PSW (PUSH Processor Status Word)
POP rp (Pop the content of register pair, which was saved, from the stack)
POP PSW (Pop Processor Status Word)
HLT (Halt)
XTHL (Exchange stack-top with H-L)
SPHL (Move the contents of H-L pair to stack pointer)
EI (Enable Interrupts)
DI (Disable Interrupts)
SIM (Set Interrupt Masks)
RIM (Read Interrupt Masks)
NOP (No Operation)
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8086 Microprocessor

Intel 8086
 Intel 8086 microprocessor is the enhanced version of Intel 8085 microprocessor. It was
designed by Intel in 1976.
 The 8086 microprocessor is a16-bit, N-channel, HMOS microprocessor. Where the
HMOS is used for "High-speed Metal Oxide Semiconductor".
 Intel 8086 is built on a single semiconductor chip and packaged in a 40-pin IC package.
The type of package is DIP (Dual Inline Package).
 Intel 8086 uses 20 address lines and 16 data- lines. It can directly address up to 220 = 1
Mbyte of memory.
 It consists of a powerful instruction set, which provides operation like division and
multiplication very quickly.
 8086 is designed to operate in two modes, i.e., Minimum and Maximum mode.

Difference between 8085 and 8086 Microprocessor

Architecture of 8086
The following diagram depicts the architecture of a 8086 Microprocessor −
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Fig. 1: Block Diagram of Intel 8086

The 8086 CPU is divided into two independent functional units:

 Bus Interface Unit (BIU)
 Execution Unit (EU)

Features of 8086 Microprocessor:

 Intel 8086 was launched in 1978.

 It was the first 16-bit microprocessor.
 This microprocessor had major improvement over the execution speed of 8085.
 It is available as 40-pin Dual-Inline-Package (DIP).
 It is available in three versions:
o 8086 (5 MHz)
o 8086-2 (8 MHz)
o 8086-1 (10 MHz)
 It consists of 29,000 transistors.

1. Bus Interface Unit (BIU) - The function of BIU is to:

 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
 Instruction Queue
o To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory.
o All six bytes are then held in first in first out 6 byte register called instruction
queue.
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o Then all bytes have to be given to EU one by one.

o This pre fetching operation of BIU may be in parallel with execution operation of
EU, which improves the speed execution of the instruction.

2. Execution Unit (EU) - The functions of execution unit are:

 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
The EU contains the control circuitry to perform various internal operations. A decoder in EU
decodes the instruction fetched memory to generate different internal or external control signals
required to perform the operation. EU has 16-bit ALU, which can perform arithmetic and logical
operations on 8-bit as well as 16-bit.
Functional parts of 8086 microprocessors:
2.1 General Purpose Registers of 8086 - These registers can be used as 8-bit registers individually
or can be used as 16-bit in pair to have AX, BX, CX, and DX.
 AX Register: AX register is also known as accumulator register that stores operands for
arithmetic operation like divided, rotate.
 BX Register: This register is mainly used as a base register. It holds the starting base
location of a memory region within a data segment.
 CX Register: It is defined as a counter. It is primarily used in loop instruction to store
loop counter.
 DX Register: DX register is used to contain I/O port address for I/O instruction.

2.2 Segment Registers - Additional registers called segment registers generate memory address
when combined with other in the microprocessor. In 8086 microprocessor, memory is divided
into 4 segments as follow:
 Code Segment (CS): The CS register is used for addressing a memory location in the
Code Segment of the memory, where the executable program is stored.
 Data Segment (DS): The DS contains most data used by program. Data are accessed in
the Data Segment by an offset address or the content of other register that holds the
offset address.
 Stack Segment (SS): SS defined the area of memory used for the stack.
 Extra Segment (ES): ES is additional data segment that is used by some of the string to
hold the destination data.

Fig.: Memory Segments of 8086

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2.3 Flag Registers of 8086 - Flag register in EU is of 16-bit and is shown in below fig.:

Fig.: Flag Register of 8086

Flags Register determines the current state of the processor. They are modified automatically
by CPU after mathematical operations, this allows to determine the type of the result, and to
determine conditions to transfer control to other parts of the program. 8086 has 9 flags and they
are divided into two categories:
 Conditional Flags
 Control Flags

2.3.1 Conditional Flags - Conditional flags represent result of last arithmetic or logical
instruction executed. Conditional flags are as follows:
 Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
 Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from
lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry
given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally
by the processor to perform Binary to BCD conversion.
 Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
of the result contains even number of 1’s, the Parity Flag is set and for odd number of
1’s, the Parity Flag is reset.
 Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
 Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set.
 Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.

2.3.2 Control Flags - Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:
 Trap Flag (TP):
o It is used for single step control.
o It allows user to execute one instruction of a program at a time for debugging.
o When trap flag is set, program can be run in single step mode.
 Interrupt Flag (IF):
o It is an interrupt enable/disable flag.
o If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
o It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
 Direction Flag (DF):
o It is used in string operation.
o If it is set, string bytes are accessed from higher memory address to lower
memory address.
Computer System Architecture

o When it is reset, the string bytes are accessed from lower memory address to
higher memory address.
Computer System Architecture

Machine Language Instruction

Instructions are classified on the basis of functions they perform. They are categorized into the
following main types:
The 8086 microprocessor supports 8 types of instructions −
 Data Transfer Instructions
 Arithmetic Instructions
 Bit Manipulation Instructions
 String Instructions
 Program Execution Transfer Instructions (Branch & Loop Instructions)
 Processor Control Instructions
 Iteration Control Instructions
 Interrupt Instructions

1. Data Transfer instruction - All the instructions which perform data movement come under
this category. The source data may be a register, memory location, port etc. the destination may
be a register, memory location or port. The following instructions come under this category:

Category Instruction Description

MOV Used to copy the byte or word from the provided source
to the provided destination.
PPUSH Used to put a word at the top of the stack.
POP Used to get a word from the top of the stack to the
Instruction to provided location.
transfer a word PUSHA Used to put all the registers into the stack.
POPA Used to get words from the stack to all registers.
XCHG Used to exchange the data from two locations.
XLAT Used to translate a byte in AL using a table in the
memory.
IN Used to read a byte or word from the provided port to the
Instructions for
accumulator.
input and output
OUT Used to send out a byte or word from the accumulator to
port transfer
the provided port.
LEA Used to load the address of operand into the provided
register.
Instructions to
LDS Used to load DS register and other provided register from
transfer the
the memory
address
LES Used to load ES register and other provided register from
the memory.
LAHF Used to load AH with the low byte of the flag register.
Instructions to SAHF Used to store AH register to low byte of the flag register.
transfer flag
PUSHF Used to copy the flag register at the top of the stack.
registers
POPF Used to copy a word at the top of the stack to the flag
register.
Computer System Architecture

2. Arithmetic Instructions - These instructions are used to perform arithmetic operations like
addition, subtraction, multiplication, division, etc.
Following is the list of instructions under this group –
Category Instruction Description
ADD Used to add the provided byte to byte/word to word.
ADC Used to add with carry.
Instructions to INC Used to increment the provided byte/word by 1.
perform addition AAA Used to adjust ASCII after addition.
DAA Used to adjust the decimal after the addition/subtraction
operation.
SUB Used to subtract the byte from byte/word from word.

SBB Used to perform subtraction with borrow.

Instructions to DEC Used to decrement the provided byte/word by 1.
perform NPG Used to negate each bit of the provided byte/word and
subtraction add 1/2’s complement.
CMP Used to compare 2 provided byte/word.
AAS Used to adjust ASCII codes after subtraction.
DAS Used to adjust decimal after subtraction.
Instruction to MUL Used to multiply unsigned byte by byte/word by word.
perform IMUL Used to multiply signed byte by byte/word by word.
multiplication AAM Used to adjust ASCII codes after multiplication.
DIV Used to divide the unsigned word by byte or unsigned
double word by word.
IDIV Used to divide the signed word by byte or signed double
word by word.
Instructions to AAD Used to adjust ASCII codes after division.
perform division
CBW Used to fill the upper byte of the word with the copies of
sign bit of the lower byte.
CWD Used to fill the upper word of the double word with the
sign bit of the lower word.

3. Bit Manipulation Instructions - These instructions are used to perform operations where data
bits are involved, i.e. operations like logical, shift, etc.
Following is the list of instructions under this group –
Category Instruction Description
NOT Used to invert each bit of a byte or word.
AND Used for adding each bit in a byte/word with the
corresponding bit in another byte/word.
OR Used to multiply each bit in a byte/word with the
Instructions to
corresponding bit in another byte/word.
perform logical
XOR Used to perform Exclusive-OR operation over each bit in
operation
a byte/word with the corresponding bit in another
byte/word.
TEST Used to add operands to update flags, without affecting
operands.
SHL/SAL Used to shift bits of a byte/word towards left and put
zero(S) in LSBs.
Instructions to
SHR Used to shift bits of a byte/word towards the right and put
perform shift
zero(S) in MSBs.
operations
SAR Used to shift bits of a byte/word towards the right and
copy the old MSB into the new MSB.
Computer System Architecture

ROL Used to rotate bits of byte/word towards the left, i.e.

MSB to LSB and to Carry Flag [CF].
ROR Used to rotate bits of byte/word towards the right, i.e.
Instructions to
LSB to MSB and to Carry Flag [CF].
perform rotate
RCR Used to rotate bits of byte/word towards the right, i.e.
operations
LSB to CF and CF to MSB.
RCL Used to rotate bits of byte/word towards the left, i.e.
MSB to CF and CF to LSB.

4. String Instructions - String is a group of bytes/words and their memory is always allocated in
a sequential order.
Following is the list of instructions under this group –
Instruction Description
REP Used to repeat the given instruction till CX ≠ 0.
REPE/REPZ Used to repeat the given instruction until CX = 0 or zero flag ZF =
1.
REPNE/REPNZ Used to repeat the given instruction until CX = 0 or zero flag ZF =
1.
MOVS/MOVSB/MOV Used to move the byte/word from one string to another.
SW
COMS/COMPSB/CO Used to compare two string bytes/words.
MPSW
INS/INSB/INSW Used as an input string/byte/word from the I/O port to the provided
memory location.
OUTS/OUTSB/OUTS Used as an output string/byte/word from the provided memory
W location to the I/O port.
SCAS/SCASB/SCASW Used to scan a string and compare its byte with a byte in AL or
string word with a word in AX.
LODS/LODSB/LODS Used to store the string byte into AL or string word into AX.
W

5. Processor Control Instructions - These instructions are used to control the processor action
by setting/resetting the flag values.
Following are the instructions under this group –
Instruction Description
STC Used to set carry flag CF to 1
CLC Used to clear/reset carry flag CF to 0
CMC Used to put complement at the state of carry flag CF.
STD Used to set the direction flag DF to 1
CLD Used to clear/reset the direction flag DF to 0
STI Used to set the interrupt enable flag to 1, i.e., enable INTR input.
CLI Used to clear the interrupt enable flag to 0, i.e., disable INTR input.
Computer System Architecture

6. Iteration Control Instructions - These instructions are used to execute the given instructions
for number of times. Following is the list of instructions under this group –
Instruction Description
LOOP Used to loop a group of instructions until the condition satisfies, i.e., CX
=0
LOOPE/LOOPZ Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0
LOOPNE/LOOPNZ Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0
JCXZ Used to jump to the provided address if CX = 0

7. Program Execution Transfer Instructions (Branch and Loop Instructions) - These

instructions are used to transfer/branch the instructions during an execution. It includes the
following instructions –
Category Instruction Description
Instructions to CALL Used to call a procedure and save their return address to
transfer the the stack.
instruction during RET Used to return from the procedure to the main program.
an execution JMP Used to jump to the provided address to proceed to the
without any next instruction.
condition
JA/JNBE Used to jump if above/not below/equal instruction
satisfies.
JAE/JNB Used to jump if above/not below instruction satisfies.
JBE/JNA Used to jump if below/equal/ not above instruction
satisfies.
JC Used to jump if carry flag CF = 1
JE/JZ Used to jump if equal/zero flag ZF = 1
JG/JNLE Used to jump if greater/not less than/equal instruction
satisfies.
Instructions to JGE/JNL Used to jump if greater than/equal/not less than instruction
transfer the satisfies.
instruction during
JL/JNGE Used to jump if less than/not greater than/equal instruction
an execution with
satisfies.
some conditions
JLE/JNG Used to jump if less than/equal/if not greater than
instruction satisfies.
JNC Used to jump if no carry flag (CF = 0)
JNE/JNZ Used to jump if not equal/zero flag ZF = 0
JNO Used to jump if no overflow flag OF = 0
JNP/JPO Used to jump if not parity/parity odd PF = 0
JNS Used to jump if not sign SF = 0
JO Used to jump if overflow flag OF = 1
JP/JPE Used to jump if parity/parity even PF = 1
JS Used to jump if sign flag SF = 1

8. Interrupt Instructions - These instructions are used to call the interrupt during program
execution.
Instruction Description
INT Used to interrupt the program during execution and calling service
specified.
INTO Used to interrupt the program during execution if OF = 1
Computer System Architecture

IRET Used to return from interrupt service to the main program

Computer System Architecture

BASIC 8086/8088

Though the architecture and instruction set of both 8086 and 8088 processors are same, still there
are differences between them.
Following is the table listing the differences between the 2 microprocessors:
S.
NO. 8086 MICROPROCESSOR 8088 MICROPROCESSOR

1 The data bus is of 16 bits. The data bus is of 8 bits.

It has 3 available clock speeds (5 MHz, 8 It has 3 available clock speeds (5 MHz, 8
2 MHz (8086-2) and 10 MHz (8086-1)). MHz)

The memory capacity is implemented as

3 The memory capacity is 512 kB. a single 1 MX 8 memory banks.

It has complemented memory control pin

4 It has memory control pin (M/IO) signal. (IO/M) signal of 8086.

5 It has Bank High Enable (BHE) signal. It has Status Signal (SSO).

It can read or write either 8-bit or 16-bit It can read only 8-bit word at the same
6 word at the same time. time.

Input/Output voltage level is measured at Input/Output voltage level is measured at

7 2.5 mA. 2.0 mA

It has 4 byte instruction queue as it can

8 It has 6 byte instruction queue. fetch only 1 byte at a time.

It draws a maximum supply current of 360 It draws a maximum supply current of

9 mA. 340 mA.