// Clock divider parameters.
Counters are triggered every THRES_divider'th clock
pulse.
// THRES_divider + 1 = [ramp time] * [clk freq] / THRES_vprog
// THRES_ramp_down variable is dummy
`define WIDTH_divider 4
`define THRES_divider 4'd2
`define THRES_divider_fast 4'd0
`define THRES_ramp_down 4'd0
// Output voltage parameters. Voltage is ramped up to THRES_vprog.
// WIDTH_vprog variable is dummy
`define WIDTH_vprog 6
`define THRES_ramp 5'd31
`define WIDTH_onehot 32
// Voltage hold time parameters. Voltage is held up for THRES_prog/erase trigger
pulses.
// THRES_prog/erase = [clk freq] * [hold time] / THRES_divider
`define WIDTH_hold 7
`define THRES_erase 8'd60
//`define THRES_prog 8'd119
// Delay time parameter. Assuming 100 KHz clock, that will mean 20 clock cycles
for 200us delay.
// DELAY_hold variable is dummy
`define DELAY_hold 3
`define DELAY_time 4'd9
`define DELAY_ready 5'd20
`timescale 1ns/100ps
module HVGENMINILV_DIGITAL_CONTROL(
input por,
input clk,
input start,
input timing_mode,
input hv_enable,
input read,
output [`WIDTH_onehot-1 : 0] onehot,
output lo,
output hi,
output reg [2:0] state,
output reg ready
);
// reg [1:0] start_d;
reg [`WIDTH_divider-1 : 0] divider;
reg [`WIDTH_hold-1 : 0] trigger_counter;
wire trigger;
// wire start_pulse;
reg start_pulse;
wire ramp_up_done;
wire hold_done;
wire ramp_down_done;
wire delayed_start;
wire delayed_ready;
wire counter_finished;
wire [3:0] hold_counter;
// Instantiate TIE CELL
assign hi = 1'b1;
assign lo = 1'b0;
// State machine state definitions
parameter IDLE = 3'd0;
parameter DELAY_START = 3'd1;
parameter RAMP_UP = 3'd2;
parameter HOLD = 3'd3;
parameter RAMP_DOWN = 3'd4;
parameter DELAY_READY = 3'd5;
// Detect rising edge on start input
always @ (posedge start or posedge por or negedge hv_enable or posedge
delayed_start) begin
if (por) start_pulse <= 0;
else if (~hv_enable) start_pulse <= 0;
else if (delayed_start) start_pulse <=0;
else if (state == IDLE) start_pulse <= 1;
else start_pulse <= 0;
end
// Clock divider
always @(posedge clk or posedge por or negedge hv_enable)
if (por) divider <= 0;
else if (~hv_enable) divider <= 0;
else if (state == IDLE) divider <= 0;
else if (trigger) divider <= 0;
else divider <= divider + 1;
assign trigger = (state == DELAY_START) ? (divider == `DELAY_time) :
(state == DELAY_READY) ? (1'b1) :
(state == RAMP_DOWN) ? (divider == `THRES_divider+1) :
(state == RAMP_UP) ? ((timing_mode == 1) ? (divider ==
(`THRES_divider_fast+2)) : (divider == `THRES_divider+2)) :
(divider == hold_counter);
// State machine
always @(posedge clk or posedge por or negedge hv_enable)
if (por) state <= IDLE;
else if (~hv_enable) state <= IDLE;
else case(state)
IDLE: state <= (start_pulse) ? DELAY_START : IDLE;
DELAY_START: state <= (delayed_start) ? RAMP_UP : DELAY_START;
RAMP_UP: state <= (ramp_up_done) ? HOLD : RAMP_UP;
HOLD: state <= (hold_done) ? RAMP_DOWN : HOLD;
RAMP_DOWN: state <= (ramp_down_done) ? DELAY_READY : RAMP_DOWN;
DELAY_READY: state <= (delayed_ready) ? IDLE : DELAY_READY;
default: state <= IDLE;
endcase
// Trigger Counter
always @(posedge clk or posedge por or negedge hv_enable)
if (por) trigger_counter <= 0;
else if (~hv_enable) trigger_counter <= 0;
else if (state == IDLE) trigger_counter <= 0;
else if (state == DELAY_START) trigger_counter <= 0;
else if (counter_finished && hold_done) trigger_counter <= 1;
else if (counter_finished) trigger_counter <= 1;
else begin
trigger_counter <= (trigger) ? (state == RAMP_DOWN ? trigger_counter +
1 : trigger_counter + 1) : trigger_counter;
if(trigger_counter < 16 && state == RAMP_DOWN) trigger_counter <=
trigger_counter + 3;
end
assign counter_finished = ((state == RAMP_UP) || (state == RAMP_DOWN)) ?
(trigger_counter >= `THRES_ramp) :
(state == DELAY_READY) ? trigger_counter >= `DELAY_ready :
(trigger_counter >= `THRES_erase);
assign ramp_up_done = (state == RAMP_UP) && counter_finished;
assign ramp_down_done = (state == RAMP_DOWN) && counter_finished;
assign hold_done = (state == HOLD) && counter_finished;
assign delayed_ready = (state == DELAY_READY) && counter_finished;
assign delayed_start = (state == DELAY_START) && trigger;
always @(posedge clk or posedge por or posedge start_pulse or negedge hv_enable)
if (por) ready <= 1;
else if (~hv_enable) ready <= 1;
else if (start_pulse) ready <= 0;
else if (state == IDLE) ready <= 1;
else ready <= ready;
assign onehot = (state == RAMP_UP) ? (1 << trigger_counter) :
(state == HOLD) ? (1 << 31) :
(state == RAMP_DOWN) ? (1 << (31 - trigger_counter)) :
(state == DELAY_START) ? (1 << 0) :
(state == DELAY_READY) ? (1 << 0) :
(read == 1'b1) ? (1 << 8) :
(state == IDLE) ? (1 << 0) :
0;
assign hold_counter = timing_mode ? `THRES_divider_fast + 2 : `THRES_divider+3;
endmodule