Memory System Design for a Microprocessor-
Based System
Problem Statement
A microprocessor system requires the following memory configuration: - 16
KB ROM for bootstrap loader (non-volatile, fast access) - 32 KB SRAM for
high-speed cache (≤ 70 ns access time) - 128 KB DRAM for main memory
(refresh required) - 256 KB FLASH for firmware storage (rewritable)
(a) Selection of Memory Devices
1. Bootstrap Loader Memory (16 KB ROM)
Device Type: EPROM / Mask ROM
Organization: 16K × 8
Example Device: 27C128 EPROM
Key Specifications: - Access Time: ~150 ns
- Power Consumption: Low
- Interface Type: Parallel address/data bus
- Non-volatile storage
Justification: The bootstrap program is permanent and rarely modified,
making EPROM or Mask ROM suitable due to non-volatility and reliable
operation.
2. High-Speed Cache Memory (32 KB SRAM)
Device Type: Static RAM (SRAM)
Organization: 32K × 8
Example Device: 62256 SRAM
Key Specifications: - Access Time: ≤ 70 ns
- Power Consumption: Moderate
- Interface Type: Simple parallel interface
- No refresh required
Justification: SRAM provides very fast access with simple control logic,
making it ideal for cache memory applications.
3. Main Memory (128 KB DRAM)
Device Type: Dynamic RAM (DRAM)
Organization: 64K × 8 (two chips)
Example Device: 4164 DRAM
Key Specifications: - Access Time: ~150 ns
- Power Consumption: Low per bit
- Interface Type: Multiplexed row/column address
- Refresh required
Justification: DRAM offers high memory density and low cost per bit,
making it suitable for large main memory despite refresh complexity.
4. Firmware Storage (256 KB FLASH)
Device Type: Flash Memory
Organization: 256K × 8
Example Device: 29F020 Flash
Key Specifications: - Access Time: ~90 ns
- Power Consumption: Low
- Interface Type: Parallel
- Electrically erasable and programmable
Justification: Flash memory allows firmware to be updated easily while
retaining non-volatile storage.
(b) Comparison of SRAM and DRAM
Parameter SRAM DRAM
Speed Very fast Slower
Cost per bit High Low
Density Low High
Interface Simple Complex
complexity
Power requirement Higher Lower
Refresh Not required Required
Typical use Cache Main memory
Conclusion: SRAM is preferred for speed-critical memory such as cache,
while DRAM is suitable for large-capacity main memory due to lower cost.
(c) DRAM Refresh Circuit Design
Given Data
Refresh cycles required: 128
Total refresh time: 2 ms
System clock: 8 MHz
Components: 8253 Timer, 74LS163 Counter
Refresh Interval Calculation
Refresh interval = 2 ms / 128 = 15.625 µs
8253 Timer Configuration
Input clock: 8 MHz
Required period: 15.625 µs
Count value = 8 MHz × 15.625 µs = 125
Mode Used: Mode 2 (Rate Generator)
The timer generates one refresh pulse every 15.625 µs.
Address Generation Using 74LS163
74LS163 is a 4-bit synchronous binary counter
Two counters cascaded to generate 7-bit row addresses (0–127)
Each refresh pulse increments the counter
Counter output connected to DRAM row address lines
Refresh Operation Sequence
1. 8253 generates a refresh pulse
2. Pulse increments the 74LS163 counter
3. Counter outputs the next row address
4. DRAM row is refreshed
5. After 128 counts, the counter resets
Block Diagram (Text Representation)
8 MHz Clock → 8253 Timer → Refresh Pulse → 74LS163 Counter → DRAM Row
Address Lines
Conclusion
The proposed memory configuration meets all system requirements. SRAM
provides high-speed cache performance, DRAM offers cost-effective main
memory, and ROM/Flash ensure reliable non-volatile storage. The refresh
circuit using the 8253 timer and 74LS163 counter efficiently satisfies DRAM
refresh requirements.