The Intel 80386 microprocessor, often known as the i386, was a popular

x86-based microprocessor. Its capacity to run in numerous modes, which

allowed varied levels of memory management and protection, as well as
backward compatibility with previous processors, was one of its primary
characteristics.

The 80386 Modes of Operation:

●​ Real Mode
●​ Protected Mode
●​ Virtual 8086 Modes
●​ System Management Mode
Each mode provided unique features and was designed for certain use cases,
such as running older applications, advanced memory management, and
system management duties. Understanding these operating modes is critical
for understanding the 80386 microprocessor's capabilities and limitations, as
well as how it was employed in early personal computers and servers.

Real Mode:

When the 80386 is turned on for the first time, the Real mode is its default
operating mode. Software created for the 8086 and 8088 processors will work
on the 80386 without needing to be modified because it is fully
backward-compatible with these older CPUs. The 80386 has a 20-bit address
space in Real mode, giving it access to 1MB of memory. The memory is
separated into 64K segments, and a 16-bit segment register can be used to
access each section. The processor uses segment-based memory addressing
while operating in this mode and is not given access to sophisticated memory
management and security functions. Real mode likewise has a constrained
set of instructions and does not support protected or virtual memory.

Protected Mode:

A 32-bit address space is available in protected mode, a sophisticated

operating mode that gives users access to up to 4GB of memory. Additionally,
it offers sophisticated memory management and security features including
segmentation and paging. Pages are fixed-size units of memory that can be
moved in and out of physical memory as needed. Paging enables this.
Memory can be separated into logical units called segments through
segmentation, which can be used to restrict access to particular memory
locations. The 80386 also has access to a number of privileged instructions
and registers in a protected mode that are not present in regular mode. The
protected mode also supports virtual memory which allows the system to use
more memory than the physical memory available by swapping memory
pages to and from the disk.

Virtual 8086 Modes:

The 80386 may operate numerous virtual environments that are compatible
with the 8086 simultaneously in virtual 8086 modes. Although they share the
same physical memory, each virtual environment has its own set of registers
and memory space. This mode enables the 80386 to mimic the actions of an
8086 processor, which is frequently used to run older applications on more
modern computers. The 80386 may move between many virtual environments
as needed thanks to the system for handling interrupts and exceptions that
are provided by virtual 8086 modes. The virtual 8086 mode allows for the
simultaneous operation of numerous virtual machines without interfering with
one another while simulating the behavior of a real 8086 CPU in a protected
virtual memory environment.
A more aggressive approach is to equip the processor with multiple processing units to
handle several instructions in parallel in each processing stage. With this arrangement,
several instructions start execution in the same clock cycle and the process is said to
use multiple issue. Such processors are capable of achieving an instruction execution
throughput of more than one instruction per cycle. They are known as 'Superscalar
Processors'.
In the above diagram, there is a processor with two execution units; one for integer and
one for floating point operations. The instruction fetch unit is capable of reading the
instructions at a time and storing them in the instruction queue. In each cycle, the
dispatch unit retrieves and decodes up to two instructions from the front of the queue.
If there is one integer, one floating point instruction and no hazards, both the
instructions are dispatched in the same clock cycle. ​
​
Advantages of Superscalar Architecture :

●​ The compiler can avoid many hazards through judicious selection and
ordering of instructions.
●​ The compiler should strive to interleave floating point and integer
instructions. This would enable the dispatch unit to keep both the integer and
floating point units busy most of the time.
●​ In general, high performance is achieved if the compiler is able to arrange
program instructions to take maximum advantage of the available hardware
units.

Disadvantages of Superscalar Architecture :

●​ In a Superscalar Processor, the detrimental effect on performance of various

hazards becomes even more pronounced.
●​ Due to this type of architecture, problem in scheduling can occur.

Mitigation of Control Hazards with Branch Prediction

Control hazards arise from branch (conditional jump) instructions, as the flow of the
program is unknown until the branch condition is evaluated, which happens later in the
pipeline. Branch prediction techniques attempt to guess the outcome (taken or not
taken) and the target address of a branch to speculatively continue fetching and
executing instructions, thereby avoiding pipeline stalls.
Key Techniques:

●​ Static Branch Prediction: Decisions are made at compile time based on simple
heuristics or compiler hints.
○​ Always Not Taken: Assumes the branch will not be taken and continues
sequential fetching. If the prediction is wrong, the speculatively fetched
instructions are flushed (converted to NOPs), and the correct path is
started.
○​ Backward Taken/Forward Not Taken: Assumes backward branches
(loops) are usually taken and forward branches are usually not taken. This
is a common and reasonably effective static approach.
●​ Dynamic Branch Prediction: Uses runtime information and history to adapt to
program behavior.
○​ Branch History Table (BHT): A table indexed by the instruction's address,
storing a history of recent branch outcomes (e.g., a 1-bit or 2-bit counter).
A 2-bit counter provides hysteresis, changing prediction only after two
consecutive mispredictions, which is useful for loop exits.
■​ Branch Target Buffer (BTB): A cache-like structure that stores the
predicted target address of a branch instruction. This allows the
fetch stage to immediately fetch from the target address on a
predicted taken branch, avoiding the delay of calculating the target
address.
■​ Two-Level Adaptive Predictors: Achieve high accuracy by using
both global/local branch history and per-branch counters to capture
complex branch patterns.
○​ Speculative Execution: Instructions along the predicted path are executed,
but their results are not committed (written to the register file or memory)
until the branch's actual outcome is known to be correct.
Mitigation of Data Hazards with Data Forwarding

Data hazards occur when an instruction depends on the result of a previous instruction
that has not yet been written back to the register file. Data forwarding (also known as
bypassing or operand forwarding) is a technique that routes the result of an instruction
directly to the functional unit (e.g., the ALU) of a dependent instruction as soon as the
result is available, without waiting for the Write-Back stage.

Key Concepts:

●​ Mechanism: Special hardware paths (wires) and multiplexers are added to the
pipeline. Control logic detects dependencies by comparing the destination
registers of instructions in later stages with the source registers of instructions in
earlier stages.
●​ How it Works: When a dependency is detected, the multiplexer at the input of the
relevant pipeline stage (typically the Execute stage) selects the forwarded data
(e.g., from the output of the ALU or Memory stage) instead of the stale data read
from the register file during the Decode stage.
●​ Example: For instructions ADD R1, R2, R3 followed by SUB R4, R1, R5, the result
for R1 is available at the end of the ADD instruction's Execute stage. Forwarding
allows this result to be sent directly to the SUB instruction's Execute stage in the
very next cycle, preventing a stall.

Limitations: Forwarding cannot solve all data hazards, notably load-to-use hazards. If
an instruction tries to use the result of a load instruction in the very next cycle, the data
from memory is not available early enough to be forwarded to the Execute stage of the
following instruction. In such cases, a one-cycle stall (bubble) is still required.
Flynn's Taxonomy classifies parallel systems based on instruction and data streams. It
provides a simple framework for understanding different approaches to parallel
processing, helping analyze potential parallelism in computer architectures.

The four categories - SISD, SIMD, MISD, and MIMD - represent varying levels of
parallelism. This classification guides the design of parallel algorithms and
architectures, influencing the development of programming models for parallel
computing.

●​ Flynn's Taxonomy classifies parallel computer architectures based on instruction

and data streams
●​ Proposed by Michael J. Flynn in 1966 to categorize concurrent systems
●​ Utilizes two key factors for classification
○​ Number of concurrent instruction streams
○​ Number of concurrent data streams
●​ Provides a framework for understanding different approaches to parallel
processing
 ●​ Helps in analyzing the potential parallelism in computer architectures
●​ Serves as a foundation for discussing parallel computing concepts

Four Categories of Flynn's Taxonomy

●​ Single Instruction Single Data (SISD)

○​ Represents traditional sequential computing
○​ One processor executes one instruction stream on one data stream
○​ Examples include early personal computers and simple microcontrollers
●​ Single Instruction Multiple Data (SIMD)
○​ Multiple processing elements perform the same operation on multiple data
points simultaneously
○​ Commonly used in vector processors and GPU architectures
○​ Effective for tasks with high data parallelism (image processing, scientific
simulations)
●​ Multiple Instruction Single Data (MISD)
○​ Theoretical category with limited practical applications
○​ Multiple instruction streams operate on a single data stream
○​ Potential use in fault-tolerant systems for error checking
●​ Multiple Instruction Multiple Data (MIMD)
○​ Multiple processors execute different instruction streams on different data
streams independently
○​ Most flexible and scalable parallel architecture
○​ Further classified into shared memory and distributed memory
architectures
○​ Examples include multi-core processors and computer clusters
SISD vs SIMD vs MISD vs MIMD

Key Characteristics and Differences

●​ SISD (Single Instruction Single Data)

○​ Sequential execution of instructions on a single data stream
○​ One control unit and one processing unit
○​ Simple to program and understand
○​ Limited by the speed of a single processor
○​ Examples include early desktop computers and simple embedded
systems
●​ SIMD (Single Instruction Multiple Data)
○​ One instruction applied to multiple data elements simultaneously
○​ Multiple processing elements controlled by a single control unit
○​ Exploits data-level parallelism
○​ Efficient for tasks with regular data structures (matrices, vectors)
○​ Examples include vector processors and GPUs
●​ MISD (Multiple Instruction Single Data)
○​ Multiple instructions applied to a single data stream
○​ Rarely implemented in practice
○​ Potential applications in fault-tolerant systems
○​ Theoretical model with limited real-world examples
●​ MIMD (Multiple Instruction Multiple Data)
○​ Multiple processors execute different instructions on different data
independently
○​ Most flexible and general-purpose parallel architecture
○​ Supports both task-level and data-level parallelism
○​ Includes shared memory and distributed memory variants
○​ Examples include multi-core processors and computer clusters
Performance and Scalability Considerations

●​ SISD
○​ Performance limited by single instruction execution
○​ No inherent parallelism, relies on instruction-level optimizations
○​ Scalability constrained by sequential nature
●​ SIMD
○​ High performance for data-parallel tasks
○​ Scalability depends on problem's ability to be vectorized
○​ May suffer from poor utilization on irregular data structures
●​ MISD
○​ Limited practical implementations affect performance analysis
○​ Potential for high redundancy and fault tolerance
○​ Scalability challenges due to single data stream bottleneck
●​ MIMD
○​ Highest flexibility and potential for scalability
○​ Performance can vary based on problem decomposition and load
balancing
○​ Scalability may be limited by communication and synchronization
overhead
●​ Hybrid architectures often combine multiple categories to optimize performance
●​ Choice of architecture depends on specific problem characteristics and
requirements

Real-world Examples of Parallel Systems

SISD and SIMD Systems

●​ SISD examples
 ○​ Traditional single-core processors (early Intel x86 CPUs)
○​ Simple microcontrollers in embedded systems (Arduino Uno)
○​ Basic calculators and early personal computers
●​ SIMD examples
○​ Vector processors (Cray-1 supercomputer)
○​ Graphics Processing Units (NVIDIA GeForce, AMD Radeon)
○​ Digital Signal Processors (DSPs) in audio equipment
○​ NEON SIMD architecture in ARM processors
○​ Intel's SSE (Streaming SIMD Extensions) and AVX (Advanced Vector
Extensions)

MISD and MIMD Systems

●​ MISD examples (rare in practice)

○​ Systolic arrays for matrix multiplication
○​ Some pipelined architectures in signal processing
○​ Theoretical fault-tolerant systems with redundant processing
●​ MIMD examples
○​ Multi-core processors (Intel Core i7, AMD Ryzen)
○​ Symmetric Multiprocessing (SMP) systems
○​ Distributed computing systems (Hadoop clusters)
○​ Grid computing networks (SETI@home project)
○​ Cloud computing infrastructures (Amazon EC2, Google Cloud)
○​ Massively parallel processors (MPPs) in supercomputers (IBM Blue Gene)