a simple Verilog code for a half adder using the data flow modeling style:(E)
module half_adder(a, b, sum, carry);
input a, b;
output sum, carry;
assign sum = a ^ b;
assign carry = a & b;
endmodule
Verilog code for a half adder using a gate-level model:(E)
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
wire xor_out,and_out;
xor(xor_out,a,b); //InstantiateXORgate
and(and_out,a,b); //InstantiateANDgate
assign sum=xor_out; //Assignoutputs
assign carry=and_out;
endmodule
Verilog code for a half adder using the behavioral modeling (if and else):(E)
module half_adder_behavioral_1(
input a,b,
output reg s,c
);
always@(a,b)
begin
if(a==b)
begin
s=0;
c=b;
end
else
begin
s=1;
c=0;
end
end
endmodule
Verilog code for a half adder using a behavioral model with a case statement:(E)
module half_adder(A, B, sum, carry);
input A, B;
output reg sum, carry;
always @(A or B)
begin
case ({A, B})
2'b00: begin sum = 0; carry = 0; end
2'b01: begin sum = 1; carry = 0; end
2'b10: begin sum = 1; carry = 0; end
2'b11: begin sum = 0; carry = 1; end
endcase
end
endmodule
[Link] code for a full adder using a dataflow model:(E)
module full_adder(A, B, Cin, Sum, Cout);
input A, B, Cin;
output Sum, Cout;
assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);
endmodule
// full adder (E): DATA FLOW
module full_adder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
reg sum, cout;
always @(a or b or cin)
begin
sum = a ^ b ^ cin; // s= a xor b xor cin
cout= (a & b) | (a & cin) | (b & cin); //cout= a.b+[Link]+cin.a
end
endmodule
Verilog Code for FullAdder Structural/GateLevel Modelling: EXECUTED
moduleFULL_ADDER_STRUCTURAL(
inputa,
inputb,
inputcin,
outputs,
outputcout,
wirep,q,r
);
xor(p,a,b);
and(r,a,b);
xor(s,p,cin);
and(q,p,cin);
or(cout,q,r);
endmodule
Verilog Code for Ful lAdder behavioral Modelling: EXECUTED
module full_adder_beh(A, B, C, sum, carry);
input A, B, C;
output reg sum, carry;
always @(A or B or C )
begin
case ({A, B,C})
2'b000: begin sum = 0; carry = 0; end
2'b001: begin sum = 1; carry = 0; end
2'b010: begin sum = 1; carry = 0; end
2'b011: begin sum = 0; carry = 1; end
2'b100: begin sum = 1; carry = 0; end
2'b101: begin sum = 0; carry = 1; end
2'b110: begin sum = 0; carry = 1; end
2'b111: begin sum = 1; carry = 1; end
endcase
end
endmodule
[Link] code for a half subtractor using gatelevel/structural model:(E)
module half_subtractor(a, b, borrow,difference);
input a, b;
output borrow,
output difference;
wire x
xor(difference, a, b);
not(x,a);
and(borrow, x,b);
endmodule
Verilog code for a half subtractor using a behavioral model using IF
statement:(E)
module half_subtractor(A, B, D, B_out);
input A, B;
output reg D, B_out;
always @(A or B)
begin
if(a==b)
begin
D=0;
B_out =0;
end
else
begin
D=1;
B_out =B;
end
end
endmodule
module half_subtractor(A, B, D, B_out);
input A, B;
output reg D, B_out;
always @(A or B)
begin
if (A == 0 && B == 0)
begin
D = 0; B_out = 0;
end
else if (A == 0 && B == 1)
begin
D = 1; B_out = 1;
end
else if (A == 1 && B == 0)
begin
D = 1; B_out = 0;
end
else begin D = 0; B_out = 0;
end
end
endmodule
Verilog code for a half subtractor using a behavioral model using CASE
statement:(E)
module half_subtractor(A, B, D, B_out);
input A, B;
output reg D, B_out;
always @(A or B)
begin
case ({A, B})
2'b00: begin D = 0; B_out = 0; end
2'b01: begin D = 1; B_out = 1; end
2'b10: begin D = 1; B_out = 0; end
2'b11: begin D = 0; B_out = 0; end
endcase
end
endmodule
Verilog code for a half subtractor using data flow model:
module half_subtractor(A, B, D, B_out); input A, B;
output D, B_out;
wire X, Y;
xor(X, A, B);
and(Y, A, ~B); or and(y, ~a,b)
assign D = X;
assign B_out = Y;
endmodule
Verilog code for a full subtractor using a dataflow model:
module full_subtractor(A, B, Bin, D, Bout);
input A, B, Bin;
output D, Bout;
assign D = A ^ B ^ Bin;
assign Bout = (A & ~B) | (~A & B) | (Bin & ~A) | (Bin & B);
endmodule
Verilog code for a full subtractor using a case statement:
module full_subtractor(A, B, Bin, D, Bout);
input A, B, Bin;
output reg D,
Bout;
always @(A or B or Bin)
begin
case ({A, B, Bin})
3'b000: begin D = 0; Bout = 0; end
3'b001: begin D = 1; Bout = 1; end
3'b010: begin D = 1; Bout = 0; end
3'b011: begin D = 0; Bout = 1; end
3'b100: begin D = 1; Bout = 0; end
3'b101: begin D = 0; Bout = 0; end
3'b110: begin D = 0; Bout = 1; end
3'b111: begin D = 1; Bout = 1; end
endcase
end
endmodule
Verilog code for a full subtractor using gate level
module full_subtractor(
input a,
input b,
input c,
output diff
output borr);
wire x,n2,z,n1,y;
xor s1(x,b,c);
not s3(n2,x);
not s4(n1,c);
and s5(y,n1,b);
xor s2(diff,a,x);
and s6(z,n2,a);
or (borr,y,z);
endmodule
Verilog Code for 4-1 MUX Structural/Gate Level
Modelling
module mux41str(i0,i1,i2,i3,s1,s0,y);
input i0,i1,i2,i3,s1,s0;
wire a,b,c,d;
output y;
and g1(a,i0,(~s1),(~s0));
and g2(b,i1,(~s1),s0);
and g3(c,i2,s1,(~s0));
and g4(d,i3,s1,s0);
or(y,a,b,c,d);
endmodule
4-1 Multiplexer (MUX) Dataflow Modelling(E):
module mux41df(i0,i1,i2,i3,s1,s0,y);
input i0,i1,i2,i3,s1,s0;
output y;
assign y = ((~s1)&(~s0)&i0)|((~s1)&s0&i1)|(s1&(~s0)&i2)|(s1&s0&i3);
endmodule
Verilog Code 4-1 Multiplexer Behavioral Model:(E)
module mux41beh1(i,s,y );
output y ;
input 3:0] i ;
input [1:0] s ;
reg y;
always @ (i,s)
begin
if (s[1]==0&s[0]==0) y = i[0];
else if (s[1]==0&s[0]==1) y = i[1];
else if (s[1]==1&s[0]==0) y = i[2];
else y = i[3];
end
endmodule
Verilog Code for 2 to 1 Multiplexer Dataflow Modelling
module mux21df(i0,i1,s,y);
input i0,i1,s;
output y;
assign y =(i0&(~s))|(i1&s);
endmodule
Verilog Code for 2 to 1 Multiplexer gate level Modelling
module mux21str1(i0,i1,s,y);
input i0,i1,s;
output y;
wire net1,net2,net3;
not g1(net1,s);
and g2(net2,i1,s);
and g3(net3,i0,net1);
or g4(y,net3,net2);
endmodule
Verilog code for a 2-to-1 multiplexer using behavioral model:
module mux2to1(A, B, S, Y);
input A, B;
input S;
output reg Y;
always @(A or B or S)
begin
if (S == 0)
begin
Y = A;
end
else begin Y = B; end
end
endmodule
Decoder24 data flow (E)
module decoder24df(a,b,d0,d1,d2,d3);
input a,b;
output d0,d1,d2,d3;
assign d0=(~a)&(~b);
assign d1=(~a)&(b);
assign d2=(a)&(~b);
assign d3=(a)&(b);
endmodule
Decoder24 gate level (E)
module decoder24str(a,b,d0,d1,d2,d3);
input a,b;
output d0,d1,d2,d3;
not (a_bar,a);
not (b_bar,b);
and (d0,a_bar,b_bar);
and (d1,a_bar,b);
and (d2,a,b_bar);
and (d3,a,b);
endmodule
2-to-4 decoder using a behavioral model with a case
condition:EXECUTED
module decoder2to4(A, E, Y);
input [1:0] A;
input E;
output reg [3:0] Y;
always @(A or E)
begin
case ({E, A})
3'b100: Y = 4'b0001;
3'b101: Y = 4'b0010;
3'b110: Y = 4'b0100;
3'b111: Y = 4'b1000;
default: Y = 4'b0000;
endcase
end
endmodule
//3x8 decoder dataflow modelling(E)
module decoder38df(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(~a)&(~b)&(~c);
assign d1=(~a)&(~b)&c;
assign d2=(~a)&(b)&(~c);
assign d3=(~a)&(b)&(c);
assign d4=(a)&(~b)&(~c);
assign d5=(a)&(~b)&(c);
assign d6=(a)&(b)&(~c);
assign d7=(a)&(b)&(c);
endmodule
//3x8 decoder GATE LEVEL modelling(E)
module decoder38str
module decoder38str(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
output d0,d1,d2,d3,d4,d5,d6,d7;
input a,b,c;
not (x,a); // x = a_bar
not (y,b); // y = b_bar
not (z,c); // z = c_bar
and (d0,x,y,z);
and (d1,x,y,c);
and (d2,x,b,z);
and (d3,x,b,c);
and (d4,a,y,z);
and (d5,a,y,c);
and (d6,a,b,z);
and (d7,a,b,c);
endmodule
Binary to Gray conversion :
Binary to Gray Code Converter Truth Table
Binary to Gray DATA FLOW MODEL
module Binary_to_Gray(b3,b2,b1,b0,g3,g2,g1,g0);
input b3,b2,b1,b0;
output g3,g2,g1,g0;
reg g3,g2,g1,g0;
always@(b3,b2,b1,b0)
begin
g3=b3;
g2=b3^b2;
g1=b2^b1;
g0=b1^b0;
end
endmodule
Verilog code for a binary to gray code converter using
a behavioral model WITH CASE CONDITION
module binary_to_gray(B, G);
input [3:0] B;
output reg [3:0] G;
always @(B) begin
case (B)
4'b0000: G = 4'b0000;
4'b0001: G = 4'b0001;
4'b0010: G = 4'b0011;
4'b0011: G = 4'b0010;
4'b0100: G = 4'b0110;
4'b0101: G = 4'b0111;
4'b0110: G = 4'b0101;
4'b0111: G = 4'b0100
4'b1000: G = 4'b1100;
4'b1001: G = 4'b1101;
4'b1010: G = 4'b1111;
4'b1011: G = 4'b1110;
4'b1100: G = 4'b1010;
4'b1101: G = 4'b1011;
4'b1110: G = 4'b1001;
4'b1111: G = 4'b1000;
endcase
end
endmodule
Verilog Code for Binary to Gray Structural/Gate Level
Modelling
module binary_to_gray(
input b1,
input b2,
input b3,
input b4,
output g1,
output g2,
output g3,
output g4
);
buf(g1,b1);
xor (g2,b1,b2),(g3,b2,b3),(g4,b3,b4);
endmodule
Gray to binary conversion :
Gray to Binary Code Converter Truth Table
Verilog Code for Gray to Binary Structural/Gate Level
Modelling
module gray_to_binary(
input g0,
input g1,
input g2,
input g3, [OR]
output b0,
output b1,
output b2,
output b3
);
buf(b0,g0);
xor(b1,g0,g1),(b2,g0,g1,g2),(b3,g0,g1,g2,g3);
endmodule
// gray code to binary code converter DATA FLOW
MODEL (E)
module gray_to_binary(b3,b2,b1,b0,g3,g2,g1,g0);
input g3,g2,g1,g0;
output b3,b2,b1,b0;
reg b3,b2,b1,b0;
always@(g3,g2,g1,g0)
begin
b3=g3;
b2=b3^g2;
b1=b2^g1;
b0=b1^g0;
end
endmodule
Verilog code for a gray to binary code converter using a
behavioral model:
module gray_to_binary(G, B);
input [3:0] G;
output reg [3:0] B;
always @(G) begin
case (G)
4'b0000: B = 4'b0000;
4'b0001: B = 4'b0001;
4'b0011: B = 4'b0010;
4'b0010: B = 4'b0011;
4'b0110: B = 4'b0100;
4'b0111: B = 4'b0101;
4'b0101: B = 4'b0110;
4'b0100: B = 4'b0111;
4'b1100: B = 4'b1000;
4'b1101: B = 4'b1001;
4'b1111: B = 4'b1010;
4'b1110: B = 4'b1011;
4'b1010: B = 4'b1100;
4'b1011: B = 4'b1101;
4'b1001: B = 4'b1110;
4'b1000: B = 4'b1111;
endcase
end
endmodule
Verilog code for a BCD to Excess-3 code converter using a
behavioral model:
module bcd_to_excess3(B, E);
input [3:0] B;
output reg [3:0] E;
always @(B) begin
case (B)
4'b0000: E = 4'b0011;
4'b0001: E = 4'b0100;
4'b0010: E = 4'b0101;
4'b0011: E = 4'b0110;
4'b0100: E = 4'b0111;
4'b0101: E = 4'b1000;
4'b0110: E = 4'b1001;
4'b0111: E = 4'b1010;
4'b1000: E = 4'b1011;
4'b1001: E = 4'b1100;
endcase
end
endmodule
// bcd to xs-3 code converter DATA FLOW(E) :
module bcd_to_xs3(b3,b2,b1,b0,e3,e2,e1,e0);
input b3,b2,b1,b0;
output e3,e2,e1,e0;
reg e3,e2,e1,e0;
always@(b3,b2,b1,b0)
begin
e3= (b3|(b2&(b1|b0)));
e2= ~(((~b0)&(~b1))^b2);
e1= ~(b1^b0);
e0= ~b0;
end
endmodule
// xs-3 to bcd code converter DATA FLOW(E)
module xs3_to_bcd(e3,e2,e1,e0,b3,b2,b1,b0);
input e3,e2,e1,e0;
output b3,b2,b1,b0;
reg b3,b2,b1,b0;
always@(e3,e2,e1,e0)
begin
b3= e3&(e2|(e1&e0));
b2= ~(e2^(e1&e0));
b1= e1^e0;
b0= ~e0;
end
endmodule
xs-3 to bcd code converter behavioural model as
PREPARE
like bcd to x-3 as shown above
// D flip-flop
Verilog Code for D Flip Flop Behavioral Modelling using If Else(E)
module d_ff(
output reg q,
input d,
input rst_n,
input clk
);
always @(posedge clk or negedge rst_n)
begin
if (!rst_n)
begin
q <= 0;
end
else
begin
q <= d;
end
end
endmodule
Verilog Code for D Flip Flop Dataflow Modelling
module DFF(
input d,
input en,
output q,
output qb
);
assign a = ( en & ( ~ d ));
assign b = ( en & d );
assign q = ~ ( a | qb );
assign qb = ~ ( b | q );
endmodule
SR FLIP FLOP:
SR LATCH USING NOR GATE
SR LATCH USING NAND GATE
SR_latch_gate level model (NOR):
module SR_latch_gate (input R, input S, output Q, output Qbar);
nor (Q, R, Qbar);
nor (Qbar, S, Q);
endmodule
SR_latch_dataflow model(NOR):
module SR_latch_dataflow (input R, input S, output Q, output Qbar);
assign #2 Q_i = Q;
assign #2 Qbar_i = Qbar;
assign #2 Q = ~ (R | Qbar);
assign #2 Qbar = ~ (S | Q);
endmodule
SR_latch_gate level model (NAND):
module SR_latch_gate (input R, input S, output Q, output Qbar);
nand (Q, R, Qbar);
nand (Qbar, S, Q);
endmodule
SR_latch_dataflow model(NAND):
module NAND_latch_datafloe (input S, input R, output Q, output Qbar);
assign #2 Q = ~(R & Qbar);
assign #2 Qbar = ~(S & Q);
endmodule
Verilog Code for T Flip Flop Behavioral Modelling using If
Else(E)
module T_flipflop(T, clk, q, qbar);
input T,clk;
output q, qbar;
reg q,qbar;
initial
begin
//q = 0; qbar = 1;
q = 1; qbar = 0;
end
always@(posedge clk)
begin
if(T == 0)
begin
q <= q;
qbar <= qbar;
end
else if(T == 1)
begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule
Verilog Code for JK Flip Flop Behavioral Modelling
using If Else (E):
module JK_flipflop(j,k,clk,q,qbar);
input j,k,clk;
output q,qbar;
reg q, qbar;
always@(posedge clk)
begin
if(j==1&k==0)
begin
q <= 1;
qbar <= 0;
end
else if(j==0 & k==1)
begin
q <= 0;
qbar <= 1;
end
else if(j==0 & k==0)
begin
q <= q;
qbar <= qbar;
end
else if(j==1 & k==1)
begin
q <= ~q;
qbar <= ~qbar;
end
end
endmodule
JK F/F DATA FLOW(E):
module jkff_dataflow(q, qbar, j, k, clk);
input j, k, clk;
output q, qbar;
assign q = (j & clk) | (~k & q);
assign qbar = ~q;
endmodule
Verilog code for a JK flip-flop using a gate-level
model(E)
module jkff_gate(q,qbar,clk,j,k);
input j,k,clk;
output q,qbar;
wire nand1_out; // output from nand1
wire nand2_out; // output from nand2
nand(nand1_out, j,clk,qbar);
nand(nand2_out, k,clk,q);
nand(q,qbar,nand1_out);
nand(qbar,q,nand2_out);
endmodule
Verilog code for a BCD counter(mod 10) that counts
through all combinations (0-9):(E)
module bcd_counter (
input clk,
input reset,
output reg [3:0] count);
always @(posedge clk) begin
if (reset) begin
count <= 4'b0000; //
initial state: 0
end else begin
if (count == 4'b1001) begin
count <= 4'b0000; //
wrap around from 9 to 0
end else begin
count <= count + 1; //
increment count
end
end
endendmodule
Verilog code for a BCD counter(mod 10) using case
statement (behavioural model) :(E)
module bcd_counter ( input clk,
input reset,
output reg [3:0] count);
always @(posedge clk) begin
if (reset) begin
count <= 4'b0000; // initial state: 0
end
else begin
case (count)
4'b0000: count <= 4'b0001;
4'b0001: count <= 4'b0010;
4'b0010: count <= 4'b0011;
4'b0011: count <= 4'b0100;
4'b0100: count <= 4'b0101;
4'b0101: count <= 4'b0110;
4'b0110: count <= 4'b0111;
4'b0111: count <= 4'b1000;
4'b1000: count <= 4'b1001;
4'b1001: count <= 4'b0000;
default: count <= 4'b0000;
endcase
end
end
endmodule
BCD COUNTER THAT SHOULD COUNT THE COUNT VALUES
ODD COUNT(1,3,5,7,9):(E)
module sync_bcd_counter (
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 4'b0001; // initial state: 1
end else begin
case (count)
4'b0001: count <= 4'b0011; // 1 -> 3
4'b0011: count <= 4'b0101; // 3 -> 5
4'b0101: count <= 4'b0111; // 5 -> 7
4'b0111: count <= 4'b1001; // 7 -> 9
4'b1001: count <= 4'b0001; // 9 -> 1
default: count <= 4'b0001; // default to 1
endcase
end
end
endmodule
3-Bit SYNC..Up Counter Verilog Code(E):
module counter(cnt,clk,rst);
input clk,rst;
output [2:0]cnt;
reg [2:0]cnt;
wire [2:0]next_cnt;
assign next_cnt = cnt + 1'b1; //JUST increment by 1
always @ (posedge clk or negedge rst)
begin
if(!rst)
begin
cnt <= 3'b0;
end
else
begin
cnt <= next_cnt;
end
end
endmodule
4-bit Up-Down Synchronous Counter(E)
module up_down_counter (
input clk,
input reset,
input up_down, // 1 for up, 0 for down
output reg [3:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 4'b0000; // initial state: 0
end else begin
if (up_down) begin
if (count == 4'b1111) begin
count <= 4'b0000; // wrap around from 15 to 0
end else begin
count <= count + 1; // increment count
end
end else begin
if (count == 4'b0000) begin
count <= 4'b1111; // wrap around from 0 to 15
end else begin
count <= count - 1; // decrement count
end
end
end
end
endmodule
Verilog code for an synchronous 4 bit up counte:(E)
module async_up_counter(
input clk,
input reset,
output reg [3:0] count);
always @(posedge clk or posedge reset)
begin
if (reset)
begin count <= 4'b0000;
end
else begin
count <= count + 1;
end
end
endmodule
Verilog code for an synchronous 4 bit DOWN counte:(E)
module async_up_counter(
input clk,
input reset,
output reg [3:0] count);
always @(posedge clk or posedge reset)
begin
if (reset)
begin count <= 4'b1111;
end
else begin
count <= count - 1;
end
end
endmodule
3-bit Up-Down(mod 8) Synchronous Counter(E)
module up_down_counter (
input clk,
input reset,
input up_down, // 1 for up, 0 for down
output reg [2:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 3'b000; // initial state: 0
end else begin
if (up_down) begin
if (count == 3'b111) begin
count <= 3'b000; // wrap around from 7to 0
end else begin
count <= count + 1; // increment count
end
end else begin
if (count == 3'b000) begin
count <= 3'b111; // wrap around from 0 to 7
end else begin
count <= count - 1; // decrement count
end
end
end
end
endmodule
Verilog code for a 4-bit ring counter:
module ring_counter( input clk, input reset,
output reg [3:0] count);
always @(posedge clk or posedge reset)
begin
if (reset)
begin count <= 4'b0001;
end
else begin
case (count)
4'b0001: count <= 4'b0010;
4'b0010: count <= 4'b0100;
4'b0100: count <= 4'b1000;
4'b1000: count <= 4'b0001;
default: count <= 4'b0001;
endcase
end
end
endmodule
4-bit Ripple Carry Counter in Verilog HDL(E)
module Ripple_Counter(q, clk, t, reset);
output [3:0]q;
input clk, t, reset;
T_FF tff0(q[0], clk, t, reset);
T_FF tff1(q[1], q[0], t, reset);
T_FF tff2(q[2], q[1], t, reset);
T_FF tff3(q[3], q[2], t, reset);
endmodule
///// T Flipflop ///////
module T_FF(q, clk, t, reset);
output q;
input clk, t, reset;
D_FF dff0(q, d, clk, reset);
xor n2(d, q, t);
Endmodule
/////// D Flipflop ////////
module D_FF(q, d, clk, reset);
output q;
reg q;
input d, clk, reset;
always@(posedge reset or negedge clk)
if(reset)
q = 1'b0;
else
q = d;
endmodule
D Flip Flop Truth Table for Reference:
clk rst d q
⇡ 1 x 0
⇡ 0 0 0
⇡ 0 1 1
Ripple Counter TEST BENCH PROGRAM(E):
`include "Ripple_Counter.v"
module Ripple_Counter_tb();
reg clk, t, reset;
wire [3:0]q;
Ripple_Counter g1(q, clk, t, reset);
initial begin
$dumpfile("Ripple_Counter_tb.vcd");
$dumpvars(0,Ripple_Counter_tb);
t = 1;
reset = 1;
#15 reset = 0;
#340 reset = 1;
#10 reset = 0;
$display("test complete");
end
initial clk = 0;
always #10 clk = ~clk;
initial #370 $finish;
endmodule