DIGITAL SYSTEM

DESIGN USING
VERILOG
MoDULE-4
INTRODUCTION TO VERILOG
 Topics Covered
•Introduction
to VERILOG: Structure of Verilog
Module, Operators, Data Types, Styles of description

•VERILOG Data Flow Description: Highlights of

Data Flow description, Structure of Data Flow
Description
 Introduction to VERILOG:
Structure of Verilog Module, Operators, Data Types,
Styles of description
 Why HDL?
What is Hardware description language (HDL):
HDL is a computer aided design (CAD) tool for the modern digital design and synthesis of digital
systems.
Need for HDL
The advancement in the semiconductor technology, the power and complexity of digital systems has
increased. Due to this, such digital systems cannot be realized using discrete integrated circuits (IC’s).
Complex digital systems can be realized using high-density programmable chips such as application
specific integrated circuits (ASIC’s) and field programmable gate arrays (FPGA’s).
To design such systems, we require sophisticated CAD tool such as HDL.
HDL is used by designer to describe the system in a computer language that is similar to other
software Language like C. Debugging the design is easy, since HDL package implement
simulators and test benches. The two widely used Hardware description languages are VHDL and
Verilog
 A Brief History of Verilog
• Evolution of Verilog

➢ In 1983, a company called Gateway design Automation developed a hardware- description

language for its newly introduced logic simulator Verilog XL
➢ Gateway was bought by cadence in 1989 & cadence made Verilog available as public domain.
➢ In December 1995, Verilog HDL became IEEE standard 1364-1995.
➢ The language presently is maintained by the Open Verilog international (OVI) organization.
➢ Verilog code structure is based on C software language.
 Structure of Verilog Module

• The Verilog module has a declaration and a body. In the declaration, name, input and outputs of the
modules are listed. The body shows the relationship between the input and the outputs with help of
signal assignment statements.
• The syntax of the Verilog module is shown below
module name of module(port_list);
// declaration:
input , output, reg, wire, parameter, inout;
functions, tasks;
// statements or body
Initial statement
always statement
module instantiation
continuous assignment
endmodule
The example program is halfadder

module halfadder (a,b,sum,carry);

input a;
input b;
output sum;
output carry;
assign sum=a ^b; // statement 1
assign carry=a &b; // statement2
end module
 Verilog ports
input: the port is only an input port. In any assignment statement, the port should appear only

on the right hand side of the assignment statement.(i.e., port is read.)

output: the port is an output port. In contrast to VHDL, the Verilog output port can appear on

either side of the assignment statement.

 inout: this port can be used as both an input and output. The inout port represents a

bidirectional bus.
 Operators
HDL has a extensive list of operators. Operator performs a wide variety of functions. Functions
classified

1. Logical operators such as and, or, nand, nor, xor, xnor and not

2. Relational operators: to express the relation between objects. The operators include
=, /=, <, <=, >and >=.

3. Arithmetic operators: such as +, -, * and division.

4. Shifts operators: To move the bits of an objects in a certain direction such as right
or left sll, srl, sla, sra, rol and ror .
Logical operators
Verilog logical operators
Verilog Arithmetic operators
 Data types
• The data or operands used in the language must have several types to match the need for describing
the hardware

There are different types of Verilog data types. Namely

1. Nets
2. Registers
3. Vectors
4. Integer
5. Real
6. Parameters
7. Array
Nets:
These are declared by the predefined word “wire”. Nets values are change continuously by
the circuits that are driving them. A wire represents a physical wire in a circuit and is used to
connect gates or modules. The value of a wire can be read, but not assigned to, in a function
or block. Verilog supports 4 values for nets.
Eg. Wire sum; // statement declares a net
by name sum.
Wire s1=1’b0; // this statement declares a
net by the name of s1; it is initial value 1 bit
with
value 0.
Registers: Vectors:
Registers store values until they are updated. These are multiple bits. A reg or net can be
They are data storage elements. Declared by
declared as a vector. Vectors are declared by
the predefined word “reg” Verilog supports
4 values for registers. As shown in above brackets [ ].
table.
Eg: reg sum_total; // declares a register by the Eg. Wire [3:0] a=4’b1010;
name sum_total. Reg [7:0] total =8’d12;
Integer: Real:
Real (floating point) numbers are
declared by the predefined word “integer”.
declared with the predefined word “real”.
Integers are general-purpose variables. For
Examples of real
synthesis they are used mainly loops-indices,
values are 2.4, 56.3 5e12.
parameters, and constants.

Eg. Integer no_bits;//The above Eg. Real weight; // the statement

statement declares no_bits as an integer. declares the register weight as real.
Parameters: Array:
there is no predefined word “array”.
It represents global constants. Registers and integers can be used as
Declared by the predefined word arrays.
“parameter” Parameter N=4;
Parameter M=3;
Eg. : Reg signed [M: 0] carry [0:N]
Reg [M: 0] b [0: N];
Module comp_genr (x, y, xgty, xlty, xeqy); Integer sum [0: N];
The above statement declares an array by the name sum. It has 5
Parameter N=3; elements, and each element
Input [n:0] x,y; is an integer type.
Output xgty, xlty, xeqy; array carry has 5 elements, and each elements is 4bits. They are in
2’S complement form
Wire [N:0] sum, xb; The array b has 5 elements, each element is 4 bits. The value of
each bit can be 0, 1, X or Z;
 Style (Types) of Descriptions

Behavioral Descriptions
This models the system as to how the outputs behave with inputs.
The definition of Behavioral Description is one where architecture (VHDL) or module
(Verilog) includes the predefined word process (VHDL) or always or initial (Verilog).
This description is considered pure behavioral if it does not contain any other features from
other styles.
 VHDL Behavioral Description
 Verilog Behavioral Description
 Style (Types) of Descriptions

Structural Descriptions
This model the system as components or gates, this description is defined by the presence of
the Keyword component in the architecture (VHDL) or gates construct such as “and”, “or”,
or “not” in the module (Verilog).
If the VHDL architecture or the Verilog module consists of only components or gates; this
style is coined as pure structural.
 VHDL structural Description
 Verilog structural Description
 Style (Types) of Descriptions

Dataflow Descriptions
It describes how the systems signals flow from the input to the output. The dataflow
statements are concurrent; their execution is controlled by events.
Usually, the description is done by writing the Boolean function of the outputs. It should not
include any of keywords that identify behavioral, structural, or switch level descriptions.
 VHDL dataflow Description
 Verilog dataflow Description
Switch level Descriptions
It is the lowest level of description. The system is described using switches or transistors. The Verilog
keywords nmos, pmos, cmos, tran, or tranifo describe the system. VHDL does not have built in switch level
primitives, we are constructing packages to include such primitives and attach them to the VHDL module.

Mixed-type Descriptions
It uses more than type. Here we may describe some parts of the system using one type and other parts using
another type. Example of Mixed-type Description using both dataflow and behavioral style is explained in
the listing.

Mixed-language Descriptions
It is newly added tool for HDL descriptions. The user can write a module in one language (VHDL or
Verilog) and invoke or import a construct (entity or module) written in the other language.
 VERILOG Data Flow Description:
Highlights of Data Flow description, Structure of Data
Flow Description
 Highlights of Data Flow description
Dataflow is a type of hardware description which shows how the signal flows from system
inputs to outputs. It uses signal assignment statements which are executed concurrently
when an event occurs on the signals on the right side of the statement.

In HDL language, programming is carried out two standard methods.

1. Concurrent program execution: In 2. Sequential program execution: In this
this method of program execution, all method all the statements are executed
the statements within the program are sequentially in the order of their
executed simultaneously. appearance.
1. Concurrent program execution: 2. Sequential program execution:

An example of hardware that requires this method

The above gate network has two inputs A and B,
of program execution is a flip-flop. The data given
two outputs Y1 and Y2. The outputs will get
at D input will be transferred to the output only
evaluated simultaneously whenever an event occurs
after the rising or falling edge of the clock. All
on either of the inputs A or B or both, assuming
sequential circuits like flip-flops, counters, registers
the propagation delay of both the gates to be same.
require this method of program execution.

In order to describe the above hardware we need

concurrent program execution where the outputs
are updated whenever an event occurs on its
inputs, irrespective of the order of statements. All
combinational circuits need this style of execution
for accurate description of the hardware.
 Structure of Data-Flow Description

 A dataflow model specifies the functionality of the system without explicitly specifying its structure. It
specifies how the system’s signal flow from inputs to the outputs.
 The description is usually done by writing the Boolean functions of the outputs. The dataflow statements are
concurrent and their execution is controlled by events.
 EVENT: An event is a change in the value of a signal, such as a change from 0 to 1 or 1 to 0.
 Dataflow description is modeled using concurrent signal assignment statements (VHDL) and continuous
signal assignment statements (Verilog).
 VHDL dataflow description

Verilog dataflow description entity system is

Port ( I1, I2 : in bit ; O1, O2 : out bit) ;
module system ( I1, I2, O1,O2 ); end;
input I1, I2; architecture dtf of system is
output O1, O2; begin
assign O1 = I1 & I2; //st1 O1 <= I1 and I2 ; --st1
assign O2 = I1 ^ I2; //st2 O2 <= I1 xor I2 ; --st2
end module end dtf

Above example shows HDL code, describing a system using dataflow description. The entity (module) name is system. I1 and
I2 are the two inputs and O1 and O2 are the two outputs. St1 and st2 are signal assignment statements which assigns value to
the outputs O1 and O2.
SIGNAL DECLARATION:

Input and output signals are declared in the entity (module) as ports.
Intermediate Signals (other than input and output signals) are declared using the predefined
word signal in VHDL and wire in Verilog as shown in the below example. In Verilog
signals are declared using reg when the value of the signal needs to be stored.

signal s1, s2 : bit; --VHDL

wire s1, s2; // Verilog
SIGNAL ASSIGNMENT STATEMENTS:

A signal assignment statement is used to assign a value to a signal. The left hand side of the
statement should be declared as a signal. The right hand side can be a signal, a variable, or a
constant. ‘<=’ is a signal assignment operator in VHDL and in verilog predefined word
assign is used.
Execution of signal assignment statement has two phases. In the above example of system, assume that an event
at T0 occurs on either signal I1 or I2. This event changes the value of I1 from 0 to 1 and also the value of I2
from 0 to 1.
1. Calculation: The value of O1 is calculated using the current values of I1 and I2 at time T0.
The value 1 and 1=1 is calculated. This is not yet assigned to O1.
2. Assignment: The calculated value 1 is assigned to O1 after a delay time. The delay time can
be implicitly or explicitly specified. If no delay time is specified, the HDL uses a default,
small delay of Δ (delta) seconds.
Continuous signal assignment statements:
A continuous assignment statement is the most basic statement in Verilog dataflow modeling. It is used to
drive a value onto a net or assigns a value to a net. It uses the keyword assign. It has the following form,

assign LHS_target = RHS_Expression;

Example: wire[3:0] Z, preset, clr;

assign Z = preset & clr;
The target of the continuous assignment is Z and the right hand expression is (preset & clr).
The continuous assignment statement executes whenever an event occurs on an operand on the
right hand side of the expression, it is evaluated and assigned to the target.
 CONSTANT DECLARATION AND ASSIGNMENT STATEMENTS:

The value of a constant is constant within the segment of the program where it is visible.

Ex: constant period:

time period ; //verilog
To assign a value to the constant we use assignment operator := in VHDL or = in verilog.

Ex: Period = 100; //verilog

The above example assigns a value of 100 nanoseconds to the constant period which was declared above. In
verilog there are no explicit units of time. 100 means 100 simulation screen time units. The declaration and
assignment can be combined in one statement as:

time period = 100 ; //verilog

ASSIGNING A DELAY TIME TO THE SIGNAL-ASSIGNMENT STATEMENT

To assign a delay time to a signal-assignment statement, we use the predefined word after # (delay time) in
Verilog.

assign #10 s1 = sel and b; //Verilog for 10 screen units delay

Note: In Verilog, we cannot specify the units of delay time. The delay is in simulation screen
unit time.
Example 2.2: 2×1 Multiplexer with Active Low Enable
Truth table
Logic diagram
Logic symbol
Verilog code
Simulation waveform