Unit 4

Design for Testability

 Outline
❑ Testing
– Logic Verification
– Silicon Debug
– Manufacturing Test
❑ Fault Models
❑ Observability and Controllability
❑ Design for Test
– Ad hoc
– Scan
– BIST

12: Design for Testability CMOS VLSI Design 4th Ed. 2

 Testing
❑ Testing is one of the most expensive parts of chips.
Three main categories
– Functionality tests or logic verification, are run
before tape out(sending a verified chip design to
Semiconductor Foundry) to verify the functionality
of the circuit
– Silicon debug run on the first batch of chips that
return from fabrication. They can be much more
extensive than the logic verification tests
– Manufacturing tests verify that every transistor,
gate, and storage element in the chip functions
correctly
12: Design for Testability CMOS VLSI Design 4th Ed. 3
 Logic Verification
❑ Does the chip simulate correctly?
– Usually done at HDL level
– Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
❑ Ex: 32-bit adder
– Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers
❑ Good tests require ingenuity

12: Design for Testability CMOS VLSI Design 4th Ed. 4

 Silicon Debug
❑ Test the first chips back from fabrication
– If you are lucky, they work the first time
– If not…
❑ Logic bugs vs. electrical failures
– Most chip failures are logic bugs from inadequate
simulation
– Some are electrical failures
• Crosstalk
• Dynamic nodes: leakage, charge sharing
• Ratio failures
– A few are tool or methodology failures (e.g. Design Rule
Check, DRC)
❑ Fix the bugs and fabricate a corrected chip
12: Design for Testability CMOS VLSI Design 4th Ed. 5
 Manufacturing Test
❑ A speck of dust on a wafer is sufficient to kill chip
❑ Yield of any chip is < 100%
– Must test chips after manufacturing before
delivery to customers to only ship good parts
❑ Manufacturing testers are
very expensive
– Minimize time on tester
– Careful selection of
test vectors

12: Design for Testability CMOS VLSI Design 4th Ed. 6

 Manufacturing Failures

SEM images courtesy Intel Corporation

12: Design for Testability CMOS VLSI Design 4th Ed. 7

 Fault
❑ Yield of a particular IC is the number of good die
divided by the total number of die per wafer
❑ Complexity of the manufacturing process, not all die
on a wafer function correctly. Reasons
– Dust particles and small imperfections in starting
material or photomasking can result in bridged
connections or missing features.
❑ These imperfections result in what is termed a
fault.

12: Design for Testability CMOS VLSI Design 4th Ed. 8

 Testing Levels
❑ Wafer level
❑ Packaged chip level
❑ Board level
❑ System level
❑ Field level

12: Design for Testability CMOS VLSI Design 4th Ed. 9

 Testing Costs
❑ Testing is one of the most expensive parts of chips
– Logic verification accounts for > 50% of design
effort for many chips
– Debug time after fabrication has enormous
opportunity cost
– Shipping defective parts can sink a company

❑ Example: Intel FDIV bug (1994)

– Logic error not caught until > 1M units shipped
– Recall cost $450M (!!!)

12: Design for Testability CMOS VLSI Design 4th Ed. 10

 Testing Costs
❑ Wafer $0.01–$0.10
❑ Packaged chip $0.10–$1
❑ Board $1–$10
❑ System $10–$100
❑ Field $100–$1000

12: Design for Testability CMOS VLSI Design 4th Ed. 11

 Fault Models
❑ How does a chip fail?
– Usually failures are shorts between two
conductors or opens in a conductor
– This can cause very complicated behavior
❑ Thus, existence of good and bad parts, it is
necessary to propose a fault model; i.e., a model for
how faults occur and their impact on circuits.
❑ Popular Models
– A simpler model: Stuck-At Assume all failures
cause nodes to be “stuck-at” 0 or 1, i.e. shorted to
GND or VDD
12: Design for Testability CMOS VLSI Design 4th Ed. 12
 Fault Models
– Not quite true, but works well in practice
❑ (Stuck-At 0, S-A-0) or stuck at one (Stuck-At-l, S-A-
l). This model dates from board-level designs, where
it was determined to be adequate for modeling
faults.
❑ These faults most frequently occur due to gate oxide
shorts (the nMOS gate to GND or the pMOS gate to
V ) or metal-to-metal shorts.
DD

12: Design for Testability CMOS VLSI Design 4th Ed. 13

 Short Circuit and Open Circuit Faults

❑ Bridging or shorted faults

❑ If nMOS transistor A is stuck open, This can cause

very complicated behavior it is possible for a fault to
convert a combinational into sequential.

12: Design for Testability CMOS VLSI Design 4th Ed. 14

Observability & Controllability
❑ Observability: Degree to which you can observe that
node at the outputs of an integrated circuit (i.e., the
pins).
❑ Given the limited number of nodes that can be
directly observed, it is the aim of good chip
designers to have easily observed gate outputs.
❑ Ideally, you should be able to observe directly or
with moderate indirection (i.e., you may have to wait
a few cycles) every gate output within an integrated
circuit.

12: Design for Testability CMOS VLSI Design 4th Ed. 15

Observability & Controllability
❑ Controllability: ease of forcing a node to 0 or 1 by
driving input pins of the chip

❑ Combinational logic is usually easy to observe and

control
❑ Finite state machines can be very difficult, requiring
many cycles to enter desired state
– Especially if state transition diagram is not known
to the test engineer

12: Design for Testability CMOS VLSI Design 4th Ed. 16

 Test Pattern Generation
❑ Manufacturing test ideally would check every node
in the circuit to prove it is not stuck.
❑ Apply the smallest sequence of test vectors
necessary to prove each node is not stuck.

❑ Good observability and controllability reduces

number of test vectors required for manufacturing
test.
– Reduces the cost of testing
– Motivates design-for-test

12: Design for Testability CMOS VLSI Design 4th Ed. 17

 Design for Test
❑ Design the chip to increase observability and
controllability

❑ If each register could be observed and controlled,

test problem reduces to testing combinational logic
between registers.

❑ Better yet, logic blocks could enter test mode where

they generate test patterns and report the results
automatically.

12: Design for Testability CMOS VLSI Design 4th Ed. 18

 Design for Test
❑ Three main approaches to what is commonly called
Design for Testability (DFT). These may be
categorized as follows:
– Ad hoc testing
– Scan-based approaches
– Built-in self-test (BIST)

12: Design for Testability CMOS VLSI Design 4th Ed. 19

 Ad hoc testing
❑ Collections of ideas aimed at reducing the
combinational explosion of testing. Possible
approaches are
– Partitioning large sequential circuits
– Adding test points
– Adding multiplexers
– Providing for easy state reset

12: Design for Testability CMOS VLSI Design 4th Ed. 20

 Scan Design
❑ In designs with scan, the registers operate in one of
two modes.
❑ In normal mode, they behave as expected.
❑ In scan mode, they are connected to form a giant
shift register called a scan chain spanning the whole
chip. By applying N clock pulses in scan mode, all N
bits of state in the system can be shifted out and
new N bits of state can be shifted in.
❑ Therefore, scan mode gives easy observability and
controllability of every register in the system.

12: Design for Testability CMOS VLSI Design 4th Ed. 21

 Scan
CLK
❑ Convert each flip-flop to a scan register SCAN
– Only costs one extra multiplexer

Flop
SI Q
D
❑ Normal mode: flip-flops behave as usual
❑ Scan mode: flip-flops behave as shift register
scan-in

❑ Contents of flops
Flop

Flop

Flop
can be scanned Flop

Flop

Flop
Logic Logic
inputs Cloud Cloud outputs

out and new

Flop

Flop

Flop
values scanned
Flop

Flop

Flop
in scanout

12: Design for Testability CMOS VLSI Design 4th Ed. 22

 Built-in Self-test
❑ Built-in self-test lets blocks test themselves
– Generate pseudo-random inputs to comb. logic
– Combine outputs into a syndrome i.e. checking
number of 1’s in its output for all possible inputs
– With high probability, block is fault-free if it
produces the expected syndrome

12: Design for Testability CMOS VLSI Design 4th Ed. 23