Processor

Memory HW
core

DSP Memory A/D

core HW &
Shared D/A
Bridge
Memory
IP
HW
Memory
I/O
Video RAM
IP IP
I/O
 Dedicated
Performance and Power Savings

Hardware
Reconfigurable
Hardware
Application-
Specific
Processors
Domain-
Specific
Processors

General-
Purpose
Processors

Flexibility
RAM
Prog
ADDR RAM ROM
Port0 Port2 ADDR
Reg
Reg

B Reg ACC SPTR BUF

TMP2 TMP1 INC

SFRs
PSW ALU PC
Timers
Control IR DPTR

Port1 Port3
31 28 27 26 25 24 21 20 19 16 15 12 11 0

Cond 00 I OpCode S Rn Rd Operand 2

µ

ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{-S}
x: family
y: memory management/protection unit
z: cache
T: Thumb 16-bit decoder
D: JTAG debug
M: fast multiplier
I: EmbeddedICE macrocell
E: enhanced instructions (for DSP, assumes TDMI)
J: Jazelle
F: vector floating-point unit
S: synthesizable version
µ

µ
µ
µ
Custom
Logic

Nios
ALU
 Inst.
External TinyRISC
Data
SDRAM Core Processor
32 Cache
16

External Context
RC
SDRAM DMA
32 Array 256 Memory
Cont. (2x8x16x32)
64 (8x8)
64 Frame Buffer
(2x2x64x64)
64
32
 A[31:0] control
address register

P incrementer
C

register PC
bank
instruction
decode
A multiply &
L
U control
A B
b
u b b
s u barrel u
s shifter s

ALU

data out register data in register

D[31:0]
1 fetch decode execute

2 fetch decode execute

3 fetch decode execute

in struction

time
1 fetchADD decode execute

2 fetch STR decode calc. addr. data xfer

3 fetchADD decode execute

4 fetchADD decode execute

5 fetchADD decode execute

instruction
time
 next
pc +4
I-cache fetch
pc + 4

pc + 8 I decode
r15 instruction
decode
register read
immediate
fields
LDM/ mul
STM post-
index reg
+4 shift
pre-index shift
forwarding execute
ALU
mux paths
B, BL
MOV pc
SUBS pc
byte repl.

D-cache buffer/
load/store data
address
rot/sgn ex
LDR pc

register write write-back

 address register address register

increment increment
Rd PC Rd PC
registers registers
Rn Rm Rn

mult mult

as ins. as ins.

as instruction as instruction
[7:0]

data out data in i. pipe data out data in i. pipe

(a) register – register operations (b) register – immediate operations

 address register address register

increment increment
PC Rn PC
registers registers
Rn Rd

mult mult

lsl #0 shifter

= A / A+ B / A- B =A+B/ A-B
[1 1:0]

data out data in i. pipe byte? data in i. pipe

(a) 1st cycle - compute address (b) 2nd cycle - store data & auto-index
 address register address register

increment increment
R14
registers registers
PC PC

mult mult

lsl #2 shifter

= A+ B =A
[23:0]

data out data in i. pipe data out data in i. pipe

(a) 1st cycle - compute branch target (b) 2nd cycle - save return address
r0 usable in user mode
r1
r2
r3 system modes only
r4
r5
r6
r7
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq
r11 r11_fiq
r12_fiq r13_irq r13_und
r12 r13_svc r13_abt r14_und
r13 r13_fiq r14_abt r14_irq
r14_fiq r14_svc
r14
r15 (PC)

SPSR_abt SPSR_irq SPSR_und

CPSR SPSR_fiq SPSR_svc

fiq svc abort irq undefined

user mode mode mode mode mode mode
31 28 27 8 7 6 5 4 0

N Z C V unused I F T mode

CPSR[4 :0 ] M o de Us e R e g i s t e rs
10000 Us er No rm al us er co de us er
10001 FIQ Pro ces s in g fas t in terrup ts _ fi q
10010 IRQ Pro ces s in g s tan dard in terrup ts _ irq
10011 SVC Pro ces s in g s o ft ware i n terrup t s (SWIs ) _svc
10111 Ab o rt Pro ces s in g memo ry fault s _ ab t
11011 Un def Han dl in g un defin ed in s tructi o n t rap s _ un d
11111 Sy s tem Run n in g p ri v ileg ed o p erat in g s y s t em tas k s us er
Ex c e p t i o n M o de V e c t o r a ddre s s

Res et SVC 0x00000000

Undefi ned i ns tructi o n UND 0x00000004

So ftware i nterrupt (SWI) SVC 0x00000008

Prefetch abo rt (i ns tructi o n fetch memo ry faul t) Abo rt 0x0000000C

Data abo rt (data acces s memo ry faul t) Abo rt 0x00000010

IRQ (no rmal i nterrupt) IRQ 0x00000018

FIQ (fas t i nterrupt) FIQ 0x0000001C

 bit 31 bit 0 bit 31 bit 0

23 22 21 20 20 21 22 23

19 18 17 16 16 17 18 19
word16 word16
15 14 13 12 12 13 14 15
half-word14 half-word12 half-word12 half-word14
11 10 9 8 8 9 10 11
word8 word8
7 6 5 4 byte 4 5 6 7 byte
byte6 half-word4 address byte5 half-word6
address
3 2 1 0 0 1 2 3
byte3 byte2 byte1 byte0 byte0 byte1 byte2 byte3

(a) Little-endian memory (b) Big-endian memory

organization organization
 top of memory
stack
stack pointer (sp)
stack limit (sl)
stack low-water mark

unused

top of heap
heap

top of application
static data

application’s image
code
application load address
• ADD r0, r1, r2 ; r0 := r1+r2

• ADD r0, r1, #2 ; r0 := r1+2

• ADD, ADC: add (w. carry)

• SUB, SBC: subtract (w. carry)
• RSB, RSC: reverse subtract (w. carry)
• MUL, MLA: multiply (and accumulate)

• AND, ORR, EOR

• BIC: bit clear

• LSL, LSR: logical shift left/right

• ASL, ASR: arithmetic shift left/right
• ROR: rotate right
• RRX: rotate right extended with C
• MOV r0, r2 ; r0 := r2
• MVN r0, r2 ; r0 := not r2

• CMP r1, r2 ; set cc (condition code) on r1 - r2

• CMN r1, r2 ; set cc on r1 + r2
• TST r1, r2 ; set cc on r1 and r2
• TEQ r1, r2 ; set cc on r1 xor r2
• cc: NZCV bits of CPSR
– LDR, LDRH, LDRB: load (half-word, byte)
– STR, STRH, STRB: store (half-word, byte)

• register-indirect: LDR r0,[r1]

• pre-indexing: LDR r0,[r1,#4] ; r0 := mem[r1+4]
auto-indexing: LDR r0,[r1,#4]!; r0 := mem[r1+4]
; r1 := r1+4
• post-indexing: LDR r0,[r1],#4 ; r0 := mem[r1]
; r1 := r1+4
• with second register: LDR r0,[r1,r2,LSL #2]

• ADR

ADR r1,TABLE1 ; r1 points to TABLE1

..
TABLE1 ..
x = (a + b) - c;

ADR r4,a ; get address for a

LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b, reusing r4
LDR r1,[r4] ; get value of b
ADD r3,r0,r1 ; compute a+b
ADR r4,c ; get address for c
LDR r2,[r4] ; get value of c
SUB r3,r3,r2 ; complete computation of x
ADR r4,x ; get address for x
STR r3,[r4] ; store value of x
 B LABEL
..
LABEL ..

MOV r0, #0
LOOP ..
ADD r0, r0, #1
CMP r0, #10
BNE LOOP
..

BL SUBR ; branch to SUBR

.. ; return to here
SUBR .. ; subroutine entry point
MOV pc, r14 ; return
–
•
CMP r0, #5
BEQ BYPASS ; if (r0 != 5) {
ADD r1, r1, r0 ; r1 := r1+r0-r2
SUB r1, r1, r2 ; }
BYPASS ..

CMP r0, #5 ; if (r0 != 5) {

ADDNE r1, r1, r0 ; r1 := r1+r0-r2
SUBNE r1, r1, r2 ; }
..
•
EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT,
LE
–
•
SWI
–
•
if (a > b) { x = 5; y = c + d; } else x = c - d;
•
; compute and test condition
ADR r4,a ; get address for a
LDR r0,[r4] ; get value of a
ADR r4,b ; get address for b
LDR r1,[r4] ; get value for b
CMP r0,r1 ; compare a < b
BLE fblock ; if a <= b, branch to false block
; true block
MOV r0,#5 ; generate value for x
ADR r4,x ; get address for x
STR r0,[r4] ; store x
ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value of d
ADD r0,r0,r1 ; compute c+d
ADR r4,y ; get address for y
STR r0,[r4] ; store y
B after ; branch around false block
; false block
fblock ADR r4,c ; get address for c
LDR r0,[r4] ; get value of c
ADR r4,d ; get address for d
LDR r1,[r4] ; get value for d
SUB r0,r0,r1 ; compute c-d
ADR r4,x ; get address for x
STR r0,[r4] ; store value of x
after ...
•
; true block
MOVGT r0,#5 ; generate value for x
ADRGT r4,x ; get address for x
STRGT r0,[r4] ; store x
ADRGT r4,c ; get address for c
LDRGT r0,[r4] ; get value of c
ADRGT r4,d ; get address for d
LDRGT r1,[r4] ; get value of d
ADDGT r0,r0,r1 ; compute c+d
ADRGT r4,y ; get address for y
STRGT r0,[r4] ; store y
; false block
ADRLE r4,c ; get address for c
LDRLE r0,[r4] ; get value of c
ADRLE r4,d ; get address for d
LDRLE r1,[r4] ; get value for d
SUBLE r0,r0,r1 ; compute c-d
ADRLE r4,x ; get address for x
STRLE r0,[r4] ; store value of x
–
•
switch (test) { case 0: … break; case 1: … }
•
ADR r2,test ; get address for test
LDR r0,[r2] ; load value for test
ADR r1,switchtab ; load address for switch table
LDR pc,[r1,r0,LSL #2] ; switch table jump
switchtab DCD case0
DCD case1
...
 AREA Hellow, CODE, READONLY ; declare code area
SWI_WriteC EQU &0 ; output character in r0
SWI_Exit EQU &11 ; finish program
ENTRY ; code entry point
START ADR r1, TEXT ; r1 -> "Hello World"
LOOP LDRB r0, [r1], #1 ; get the next byte
CMP r0, #0 ; check for text end
SWINE SWI_WriteC ; if not end print ..
BNE LOOP ; .. and loop back
SWI SWI_Exit ; end of execution
TEXT = "Hello World", &0a, &0d, 0
END ; end of program source
 user mode registers

STMIA r13,{r0-r14}^ ADR r0,NEXTPROC

MRS r0,SPSR LDR r13,[r0]
STMDB r13,{r0,r14} LDMDB r13,{r0,r14}
MSR SPSR_csxf,r0
LDMIA r13,{r0-r14}^
MOVS pc,r14

copy SPSR to CPSR

 31 28 27 0
cond

Opcode Mnemo ni c In t erpret at i o n St at us fl ag st at e for

[31 : 28] ex t ens i on execut i on
0000 EQ Equal / equals zero Zset
0001 NE Not equal Zclear
0010 CS/HS Carry set / unsigned higher or same C set
0011 CC/LO Carry clear / unsignedlower C clear
0100 MI Minus / negative Nset
0101 PL Plus / positive or zero Nclear
0110 VS Overflow Vset
0111 VC No overflow Vclear
1000 HI Unsignedhigher C set and Zclear
1001 LS Unsignedlower or same C clear or Zset
1010 GE Signedgreater than or equal Nequals V
1011 LT Signedless than Nis not equal to V
1100 GT Signedgreater than Zclear andNequals V
1101 LE Signedless than or equal Zset or Nis not equal to V
1110 AL Always any
1111 NV Never (do not use!) none
31 28 27 25 24 23 0
cond 101 L 24-bit signed word offset

(1) BX|BLX Rm
31 2827 6 5 4 3 0
cond 0001001011111111111100 L 1 Rm

(2) BLX label

31 2827 2524 23 0

1111 101 H 24-bit signed word offset

 31 28 27 26 25 24 21 20 19 16 15 12 11 0

cond 00 # opcode S Rn Rd operand 2

destination register
first operand register
set condition codes (0..255)x22n
arithmetic/logic function

25 11 8 7 0

1 #rot 8-bit immediate

ADD r3,r2,#1
; r3:=r2+1
immediate alignment
11 7 6 5 4 3 0

ADD r3,r2,r1,LSL #3 #shift Sh 0 Rm

; r3:=r2+r1x8
25 immediate shift length
0 shift type
second operand register
11 8 7 6 5 4 3 0

ADD r3,r2,r1, LSL r0 Rs 0 Sh 1 Rm

; r3:=r2+r1x2r0
register shift length
Op c o de Mnemo ni c M e an i n g Ef f e c t
[2 4 :2 1 ]
0000 AND Lo g ical bit-wis e AND Rd := Rn AND Op2
0001 EOR Lo g ical bit-wis e ex clus iv e OR Rd := Rn EOR Op2
0010 SUB Subtract Rd := Rn - Op2
0011 RSB Rev ers e s ubtract Rd := Op2 - Rn
0100 ADD Add Rd := Rn + Op2
0101 ADC Add with carry Rd := Rn + Op2 + C
0110 SBC Subtract with carry Rd := Rn - Op2 + C - 1
0111 RSC Rev ers e s ubtract with carry Rd := Op2 - Rn + C - 1
1000 TST Tes t Scc o n Rn AND Op2
1001 TEQ Tes t equiv alence Scc o n Rn EOR Op2
1010 CMP Co mpare Scc o n Rn - Op2
1011 CMN Co mpare neg ated Scc o n Rn + Op2
1100 ORR Lo g ical bit-wis e OR Rd := Rn OR Op2
1101 MOV Mo v e Rd := Op2
1110 BIC Bit clear Rd := Rn AND NOT Op2
1111 MVN Mo v e neg ated Rd := NOT Op2
31 28 27 25 24 23 22 21 20 19 16 15 0
cond 100 P U SW L Rn register list

base register
load/store
write-back (auto-index)
restore PSR and force user bit
up/down
pre-/post-index
 ROM0e

control

RAMwe3 RAMwe2 RAMwe1 RAMwe0

A[31:0]
various

RAMoe

A[n+2:2] A[n+2:2] A[n+2:2] A[n+2:2]

oe
oe

we

oe

we

oe

we

we
A[n:0]

A[n:0]

A[n:0]

A[n:0]
A[31:0]

ARM
SRAM SRAM SRAM SRAM
D[31:0] D[7:0] D[7:0] D[7:0] D[7:0]

D[31:0] D[31:24] D[23:16] D[15:8] D[7:0]

D[7:0] D[7:0] D[7:0] D[7:0]

ROM ROM ROM ROM

A[m:0]
A[m:0]

A[m:0]

A[m:0]
oe

oe

oe

oe
A[m+2:2] A[m+2:2] A[m+2:2] A[m+2:2]
 mas[0] mas[1]
A[0] A[1]

mclk

RAMwe0

RAMwe1

RAMwe2

RAMwe3

RAMoe
r/w

ROMoe

A[31]
 te st i/f ct rl
ARM on-chip
core/CPU RAM

external
bus
interface
AHB

br idge UART
DMA
controller

timer
APB

parallel i/f
in enable
I/O

core
in
logic

enable out

de vice ID reg
TDI
TDO
bypass reg
TMS
instruction reg

TCK

TAP
TRST controller
 System on chip

EmbeddedICE JTAG
controller port JTAG TAP EmbeddedICE

host data
system Embedded
ARM
trace
core
address macrocell

control

Trace port Trace

analyzer port
•

C source C libraries asm source

C compiler as sembler

.aof
object
libraries
linker

.axf debug

ARMsd
system model

development
ARMulator
board