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On-chip
CPU RAM
B UART Timer
High bandwidth R
External bus I
Low bandwidth
bus
Memory D
Interface G
E Keypad PIO
DMA
Bus
Master
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HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HCLK
HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HREADY
HCLK
HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HREADY
HWRITE
HWDATA[31:0]
HCLK
HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HREADY
HWRITE
HWDATA[31:0]
HCLK
HRESP[1:0] Response Description
00 OKAY Transaction Completed
01 ERROR Error Occurs
10 RETRY Transaction Not Completed
Master Must Retry
11 SPLIT Transaction Not Completed
Master Must Retry
Slave Informs Completion
ERROR/RETRY/SPLIT: two cycle response
HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HREADY
HWRITE
HWDATA[31:0]
HTRANS[1:0]
HBURST[2:0]
HSIZE[2:0]
HBURST[2:0] Type Description
000 SINGLE Single transfer
001 INCR Incrementing burst of unspecified length
010 WRAP4 4-beat wrapping burst
011 INCR4 4-beat incrementing burst
100 WRAP8 8-beat wrapping burst
101 INCR8 8-beat incrementing burst
110 WRAP16 16-beat wrapping burst
111 INCR16 16-beat incrementing burst
HTRANS[1:0] Type Description
00 IDLE No data transfer required
Requires zero wait state OKAY response
01 BUSY Same as IDLE between burst transfers
10 NONSEQ Single transfer or the first of a burst
Address/Control unrelated previous
to the previous transfer
11 SEQ Remaining transfers in a burst
Address/control related
to the previous transfer
HSIZE[2:0] Size Description
000 8 bits Byte
001 16 bits Halfword
010 32 bits Word
011 64 bits -
100 128 bits 4-word line
101 256 bits 8-word line
110 512 bits -
111 1024 bits -
Master#1 Master#2 Master#3
mux Arbiter
Decoder mux Which master
uses the bus ?
Slave#1 Slave#2 Slave#3
HADDR[31:0]
HRDATA[31:0]
HRESP[1:0]
HREADY
HWRITE
HWDATA[31:0]
HTRANS[1:0]
HBURST[2:0]
HSIZE[2:0]
HBUSREQx
HGRANTx
Arbiter
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Request Grant Address Data
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No need to be aligned
(data cycle can occur after address cycle)
Simultanenous use of read & write bus
Æ Bottleneck: address cycle
(one address bus, two (read/write) data buses
Acknowledge the second addess cycle
even though the data cycle of the first address cycle
is incomplete Æ fast acknowledgement of address cycle
Æ reduce address cycle pressure
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ADDRESS WRITE DATA
READ DATA RESPONSE
1. Master
issues address
ADDRESS WRITE DATA
2. Slave
returns data
READ DATA RESPONSE
1. Master 2. Master
issues address gives data
ADDRESS WRITE DATA
3. Slave
acknowledges
READ DATA RESPONSE
AVALID WVALID RVALID BVALID
ADDR WLAST RLAST BRESP
AWRITE WDATA RDATA BID
ALEN WSTRB RRESP BREADY
ASIZE WID RID
ABURST WREADY RREADY
ALOCK
ACACHE
APROT
AID
AREADY
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WID
WDATA
WSTRB
WLAST
WVALID
WREADY
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• A
Slave
A R #1
Master Isolate address
R
#1 timing
A
Slave
R #2
A A
Master Slave
#2 R R #3
A
Isolate poor Break long Slave
read data setup interconnect path R #4
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ADDRESS A11 A12 A13 A14 A21 A22 A23 A31
DATA D11 D12 D13 D14 D21 D22 D23 D31
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ADDRESS A11 A21 A31
DATA D11 D12 D13 D14 D21 D22 D23 D31
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ADDRESS A11 A21 A31
DATA D11 D12 D13 D14 D21 D22 D23 D31
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ADDRESS A11 A12 A13 A14 A21 A22 A23 A31
DATA D11 D12
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ADDRESS A11 A21 A31
DATA D21 D22 D23 D31 D11 D12 D13 D14
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ADDRESS A11 A21 A31
DATA D21 D22 D11 D23 D12 D31 D13 D14
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Master Bus
Bus Slave
Slave
Master
#1 Matrix
Matrix #1
#1
#1
Slave
Slave
#2
#2
Master
Master
#2
#2
Slave
Slave
#3
#3
Master
Master
#3 Slave
Slave
#3 #4
#4
Æ
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’
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ADDR
TRDY#
DATA
request
Sender#1 Sender#2 Sender#3
grant
Arbiter
Receiver#1 Receiver#2 Receiver#3
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Sender#1 Sender#2 Sender#3
mux Arbiter
Receiver#1 Receiver#2 Receiver#3
Master#1 Master#2 Master#3
mux Arbiter
HRDATA
Decoder mux HWDATA
Slave#1 Slave#2 Slave#3