Learning Outcomes:
At the end of the experiment, the student should be able to:
1. Develop VHDL programs for Combinational Circuit Binary Encoder and Decoder.
2. Construct an EPWave of a Binary Encoder and Decoder.
Discussion:
• Binary encoder has 2n input lines and n-bit output lines. It can be 4-to-2, 8-to-3,
and 16-to-4-line configurations. VHDL Code for 4-to-2 encoder can be designed
both in structural and behavioral modeling. Save and Run the Program.
• Block Diagram
• Schematic Diagram
• Truth Table of 4 to 2 Encoder
INPUT OUTPUT
A3 A2 A1 A0 B1 B0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
• The std_logic_vector type can be used for creating signal buses in VHDL. The
std_logic is the most used type in VHDL, and the std_logic_vector is the array
version of it.
• While the std_logic is great for modeling the value that can be carried by a single
wire, it’s not very practical for implementing collections of wires going to or from
components. The std_logic_vector is a composite type, which means that it’s a
collection of sub-elements. Signals or variables of the std_logic_vector type can
contain an arbitrary number of std_logic elements.
• The syntax for declaring std_logic_vector signals is:
signal <name> : std_logic_vector(<lsb> to <msb>) := <initial_value>;
or
signal <name> : std_logic_vector(<msb> downto <lsb>) := <initial_value>;
• where <name> is an arbitrary name for the signal and <initial_value> is an optional
initial value. The <lsb> is the index of the least significant bit, and <msb> is the
index of the most significant bit.
• The to or downto specifies the direction of the range of the bus, basically it’s
endianness. Although both work equally well, it’s most common for VHDL
designers to declare vectors using downto.
• The VHDL code for declaring a vector signal that can hold a byte:
signal MySlv : std_logic_vector(7 downto 0);
• The VHDL code for declaring a vector signal that can hold one bit:
signal MySlv : std_logic_vector(0 downto 0);
• The VHDL code for declaring a vector signal that can hold zero bits (an empty
range):
signal MySlv : std_logic_vector(-1 downto 0);
• Copy and paste the following code to the design area.
library IEEE;
use IEEE.std_logic_1164.all;
entity ENCODER_SOURCE is
Port (
I: in std_logic_vector (3 downto 0);
Y: out std_logic_vector (1 downto 0));
end ENCODER_SOURCE;
architecture dataflow of ENCODER_SOURCE is
begin
Y(0) <= I(1) or I(3);
Y(1) <= I(2) or I(3);
end dataflow;
• Copy and paste the given code below on the testbench area and save.
library IEEE;
use IEEE.std_logic_1164.all;
entity encoder_tb is
end entity;
architecture tb of encoder_tb is
component ENCODER_SOURCE is
Port (
I: in std_logic_vector (3 downto 0);
Y: out std_logic_vector (1 downto 0));
end component;
signal I: std_logic_vector (3 downto 0);
signal Y: std_logic_vector (1 downto 0);
begin
UUT: ENCODER_SOURCE port map(
I => I,
Y => Y);
stim: process
begin
I <= "0001";
wait for 20 ns;
I <= "0010";
wait for 20 ns;
I <= "0100";
wait for 20 ns;
I <= "1000";
wait for 20 ns;
wait;
end process;
end tb;
• Save and Run the Program.
Take note of the following coding errors:
• One possible mistake is incorrect spacing.
• Always log out of your EDAPlayground account after completing a program.
• Always alter the top entity's and title's names because the top entity's and title's
names must be the same. Furthermore, testbench names like SampleCode1 must
be the same as the top entity name.
• The design's name must be the same as the design's name after beginning
architecture (for example, Design or_
• There must be no spaces in the design's name.
• You must input all the codes, or an error will occur.
Activity:
1. Create the VHDL Module of the 2 to 4 Decoder.
2. Produce the EPWave of the 2 to 4 Decoder in the space provided.
3. Write the design code. (Separate page)
4. Screenshot of EPWave for Decoder. (Separate page)
Question:
1. What are your observations from using EDA Playground in describing the code for
Encoder and Decoder?
For the encoder, I realized how it takes multiple inputs and turns them into a smaller
set of outputs. It was cool to see how it chooses which input to prioritize, especially in a
priority encoder. It helped me get a clearer picture of how data is simplified in circuits.
The decoder was also interesting , it’s like the opposite of an encoder. It takes a small
number of inputs and activates a specific output. Seeing the waveforms update based
on the inputs really helped me understand how it works
1.
2.
3.
TESTBENCH
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder_tb is
end entity;
architecture test of decoder_tb is
-- Declare the component
component DECODER_2to4
Port (
A : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0)
);
end component;
-- Testbench signals
signal A : std_logic_vector(1 downto 0);
signal Y : std_logic_vector(3 downto 0);
begin
-- Instantiate the Decoder
UUT: DECODER_2to4 port map (
A => A,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
A <= "00";
wait for 20 ns;
A <= "01";
wait for 20 ns;
A <= "10";
wait for 20 ns;
A <= "11";
wait for 20 ns;
wait;
end process;
end test;
DESIGN
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity DECODER_2to4 is
Port (
A : in std_logic_vector(1 downto 0); -- 2-bit input
Y : out std_logic_vector(3 downto 0) -- 4-bit output
);
end DECODER_2to4;
architecture dataflow of DECODER_2to4 is
begin
-- Each output bit is high only when the input matches its index
Y(0) <= '1' when A = "00" else '0';
Y(1) <= '1' when A = "01" else '0';
Y(2) <= '1' when A = "10" else '0';
Y(3) <= '1' when A = "11" else '0';
end dataflow;
4.