SystemVerilog Concepts and Interview Questions
SystemVerilog Examples
--- SystemVerilog Data Types Example ---
logic [3:0] a; // 4-bit logic type
int b = 10; // Integer type
--- Tasks and Functions Example ---
task automatic display_hello();
$display("Hello from task!");
endtask
function int add(input int a, input int b);
add = a + b;
endfunction
--- Interface Example ---
interface simple_bus(input bit clk);
logic [7:0] data;
logic enable;
modport master (input clk, output data, enable);
modport slave (input clk, input data, enable);
endinterface
--- Arrays in SystemVerilog ---
// Dynamic Array
SystemVerilog Concepts and Interview Questions
int dyn_array[];
initial begin
dyn_array = new[5];
end
// Associative Array
int assoc_array[string];
initial begin
assoc_array["one"] = 1;
end
// Queue
int queue_array[$];
initial begin
queue_array.push_back(10);
end
50 Interview Questions and Answers
1. Q: What is the difference between 'logic' and 'reg' in SystemVerilog?
A: 'logic' is a 4-state data type used in place of 'reg' in SystemVerilog. 'reg' is legacy from Verilog. 'logic' provides
better compatibility with SystemVerilog enhancements.
2. Q: What is the use of 'bit' data type in SystemVerilog?
A: 'bit' is a 2-state data type (0 or 1), useful for modeling hardware where unknown (x) or high impedance (z) states
are not required.
SystemVerilog Concepts and Interview Questions
3. Q: Explain the difference between static and automatic tasks in SystemVerilog.
A: Static tasks share the same storage across calls. Automatic tasks create a new storage every time they are called,
allowing recursion and re-entrancy.
4. Q: When would you use a function instead of a task?
A: Use a function when a return value is required and there are no time-consuming operations like delays or event
control.
5. Q: What are the restrictions of functions in SystemVerilog?
A: Functions cannot contain time-consuming operations (like #delay, @events, or wait), and must have at least one
input argument.
6. Q: What is an interface in SystemVerilog?
A: An interface bundles related signals together, promoting cleaner module connections and reusability.
7. Q: How is a modport used in SystemVerilog?
A: Modports define different sets of access (input/output) for signals in an interface, allowing structured usage across
modules.
8. Q: What is the difference between a queue and a dynamic array?
A: Queues allow push/pop operations and automatically resize, whereas dynamic arrays must be resized manually.
9. Q: What is an associative array?
A: Associative arrays are indexed using arbitrary types like strings or integers. They are useful when index values are
SystemVerilog Concepts and Interview Questions
sparse or unknown in advance.
10. Q: How do you check if an index exists in an associative array?
A: Use 'exists()' method: if (assoc_array.exists(index)) ...
11. Q: How is a struct different from a class?
A: A struct is a collection of variables, usually used for grouping. A class supports OOP features like inheritance,
polymorphism.
12. Q: What is the default value of a 'logic' variable?
A: It is 'x' (unknown) by default.
13. Q: What is the purpose of 'typedef'?
A: 'typedef' allows the creation of user-defined data types, making code more readable and maintainable.
14. Q: Can a task return a value?
A: No, a task cannot return a value like a function. Use output arguments instead.
15. Q: Explain the use of 'rand' and 'randc'.
A: 'rand' generates random values. 'randc' generates random values in a cyclic manner without repetition until all
possibilities are exhausted.
16. Q: What is a covergroup?
A: A covergroup is used in functional coverage to measure which values or combinations have been exercised during
simulation.
SystemVerilog Concepts and Interview Questions
17. Q: What is the purpose of constraints in SystemVerilog?
A: Constraints control the generation of random values to meet specific criteria.
18. Q: What are static variables in tasks and functions?
A: Static variables retain their values between calls, unlike automatic ones.
19. Q: How do you declare a multi-dimensional array?
A: Example: int matrix[4][4]; declares a 2D array with 4x4 elements.
20. Q: What is the scope of a variable declared inside a task?
A: By default, it is static unless declared as 'automatic'.
21. Q: What are queues typically used for?
A: Used for FIFOs, dynamic buffering where size can grow/shrink.
22. Q: What is the default index of associative arrays?
A: Can be string, int, or any scalar type depending on declaration.
23. Q: What is the difference between packed and unpacked arrays?
A: Packed arrays are stored contiguously in memory. Unpacked arrays are not. Packed are used for bit-level
operations.
24. Q: How do you copy one dynamic array to another?
A: You can use assignment: array2 = array1;
SystemVerilog Concepts and Interview Questions
25. Q: How do you resize a dynamic array?
A: Use 'new[]' operator: arr = new[10];
26. Q: What is a class in SystemVerilog?
A: Class is a blueprint for objects, supports inheritance, encapsulation, polymorphism.
27. Q: What are virtual interfaces?
A: They provide a way to pass interfaces to classes and modules dynamically.
28. Q: Explain 'initial' and 'always' blocks.
A: 'initial' runs once at time 0, 'always' runs indefinitely whenever sensitivity triggers.
29. Q: What is the use of $display and $monitor?
A: $display shows values once, $monitor continuously prints on value change.
30. Q: How do you model a register using SystemVerilog?
A: Use 'logic [N:0] reg_name;' and clocked always_ff or always_comb block.
31. Q: Difference between always_ff and always_comb?
A: always_ff is used for sequential logic; always_comb for combinational. always_comb ensures no latches or race
conditions.
32. Q: What is the difference between 'parameter' and 'localparam'?
A: 'parameter' can be overridden. 'localparam' cannot be changed externally.
SystemVerilog Concepts and Interview Questions
33. Q: What is the use of 'generate' block?
A: Used for conditional and loop-based generation of hardware structures.
34. Q: How do you prevent latch inference in combinational logic?
A: Ensure all paths assign values; use default assignment at the beginning.
35. Q: What is a virtual class?
A: A class that cannot be instantiated. Used as a base for polymorphism.
36. Q: What are handles?
A: Handles are pointers to class objects in SystemVerilog.
37. Q: What does 'this' keyword do?
A: 'this' refers to the current class instance.
38. Q: Explain casting in SystemVerilog.
A: Used to convert between compatible data types or classes.
39. Q: What is a mailbox?
A: Mailboxes allow communication between threads, similar to a queue with blocking behavior.
40. Q: What is a semaphore?
A: Used for mutual exclusion; controls access to shared resources.
SystemVerilog Concepts and Interview Questions
41. Q: What is the difference between fork-join and fork-join_any?
A: 'fork-join' waits for all processes. 'fork-join_any' continues after any one finishes.
42. Q: What is the use of 'disable fork'?
A: It terminates all forked processes inside a fork-join block.
43. Q: What is the 'unique' and 'priority' keyword used in case statements?
A: 'unique' ensures one true case. 'priority' enforces top-to-bottom checking.
44. Q: How do you call a superclass method from a subclass?
A: Use 'super.method_name();'
45. Q: How do you override a method in SystemVerilog?
A: Declare the method as 'virtual' in the base class, and override in the subclass.
46. Q: What is the use of coverpoint?
A: Defines the data or events to be covered in coverage model.
47. Q: What is an enum and its benefit?
A: Enum creates named constants. Improves readability and debugging.
48. Q: What is an alias in SystemVerilog?
A: Alias creates alternate name for a signal. Useful for bus renaming or abstraction.
49. Q: What is the difference between a packed struct and unpacked struct?
SystemVerilog Concepts and Interview Questions
A: Packed structs are stored contiguously; unpacked are not. Packed can be used in bit-wise operations.