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TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017

TUSB320LAI, TUSB320HAI USB Type-C Configuration Channel Logic and Port Control
1 Features 3 Description
•
1 USB Type-C™ Specification 1.1 The TUSB320LA and TUSB320HA devices, hereafter
called TUSB320 unless otherwise noted, are Texas
• Backward Compatible with USB Type-C Instrument's third generation Type-C configuration
Specification 1.0 channel logic and port controller. The TUSB320
• Supports Up to 3 A of Current Advertisement and devices use the CC pins to determine port attach and
Detection detach, cable orientation, role detection, and port
• Mode Configuration control for Type-C current mode. The TUSB320
devices can be configured as a downstream facing
– Host Only – DFP (Source) port (DFP), upstream facing port (UFP) or a dual role
– Device Only – UFP (Sink) port (DRP) making them ideal for any application.
– Dual Role Port – DRP The TUSB320 devices have an alternate
– Supports both [Link] and [Link] configuration as a DFP or UFP according to the
• Channel Configuration (CC) Type-C specifications. The CC logic block monitors
the CC1 and CC2 pins for pullup or pulldown
– Attach of USB Port Detection resistances to determine when a USB port has been
– Cable Orientation Detection attached, the orientation of the cable, and the role
– Role Detection detected. The CC logic detects the Type-C current
mode as default, medium, or high depending on the
– Type-C Current Mode (Default, Medium, High) role detected. VBUS detection is implemented to
• VBUS Detection determine a successful attach in UFP and DRP
• I2C or GPIO Control modes.
• Supports up to 400 kHz I2C The devices operate over a wide supply range and
• Role Configuration Control Through I2C have low-power consumption. The TUSB320 is
available in two versions of enable: Active low enable
• Supply Voltage: 2.7 V to 5 V
called TUSB320LA and active high enable called
• Low Current Consumption TUSB320HA. The TUSB320 family of devices are
• Industrial Temperature Range of –40 to 85°C available in industrial temperature ranges.

2 Applications Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
• Host, Device, Dual Role Port Applications
TUSB320LAI X2QFN (12) 1.60 mm × 1.60 mm
• Mobile Phones
TUSB320HAI X2QFN (12) 1.60 mm × 1.60 mm
• Tablets and Notebooks
(1) For all available packages, see the orderable addendum at
• USB Peripherals the end of the data sheet.
Simplified Schematic
Sample Applications
VDD

VBUS
VBUS Detection

CC Logic CC1
For Mode
Configuration and
Detection CC2

I2C GPIO
Controller
GPIOs
GND

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017 [Link]

Table of Contents
1 Features .................................................................. 1 7.5 Register Maps ......................................................... 16
2 Applications ........................................................... 1 8 Application and Implementation ........................ 21
3 Description ............................................................. 1 8.1 Application Information............................................ 21
4 Revision History..................................................... 2 8.2 Typical Application .................................................. 21
8.3 Initialization Setup .................................................. 28
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 28
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 29
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 29
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 29
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 30
6.5 Electrical Characteristics........................................... 5 11.1 Related Links ........................................................ 30
6.6 Timing Requirements ................................................ 6 11.2 Receiving Notification of Documentation Updates 30
6.7 Switching Characteristics .......................................... 6 11.3 Community Resources.......................................... 30
7 Detailed Description .............................................. 8 11.4 Trademarks ........................................................... 30
7.1 Overview ................................................................... 8 11.5 Electrostatic Discharge Caution ............................ 30
7.2 Feature Description................................................... 9 11.6 Glossary ................................................................ 30
7.3 Device Functional Modes........................................ 13 12 Mechanical, Packaging, and Orderable
7.4 Programming........................................................... 15 Information ........................................................... 30

4 Revision History
Changes from Revision C (October 2016) to Revision D Page

• Changed RVBUS values From: MIN = 891, TYP = 900, MAX = 909 KΩ To: MIN = 855, TYP = 887, MAX = 920 KΩ ........... 6

Changes from Revision B (September 2016) to Revision C Page

• Changed text for Pin 7 in the Pin Functions table From: "default current mode detected (H); medium or high current
mode detected (L)." To: "Refer to Table 3 for more details." ................................................................................................ 3
• Changed text for Pin 8 in the Pin Functions table From: "default or medium current mode detected (H); high current
mode detected (L)." To: "Refer to Table 3 for more details." ................................................................................................ 3

Changes from Revision A (March 2016) to Revision B Page

• Changed pins CC1 and CC2 values From: MIN = –0.3 MAX = VDD + 0.3 To: MIN –0.3 MAX = 6 in the Absolute
Maximum Ratings ................................................................................................................................................................... 4

Changes from Original (October 2015) to Revision A Page

• Added Note 1 and 2 to the Pin Functions table...................................................................................................................... 3

• Changed the DESCRIPTION of pin EN_N pin in the Pin Functions table ............................................................................. 3
• Changed the DESCRIPTION of pin EN pin in the Pin Functions table.................................................................................. 3
• Changed the DESCRIPTION of pin VDD in the Pin Functions table ....................................................................................... 3
• Added Note 2 to the Electrical Characteristics table ............................................................................................................. 5
• Added Test Condition "See Figure 1" to VBUS_THR in the Electrical Characteristics ......................................................... 6
• Changed the last sentence of the Debug Accessory section............................................................................................... 12
• Added Note: "SW must make sure..." to the Description of INTERRUPT_STATUS in Table 9 ......................................... 18
• Added text to list item 2 in the TUSB320LA Initialization Procedure section ....................................................................... 28
• Added text to list item 2 in the TUSB320HA Initialization Procedure section ...................................................................... 28

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5 Pin Configuration and Functions

RWB Package RWB Package

12-Pin X2QFN 12-Pin X2QFN
TUSB320LA Top View TUSB320HA Top View

CC1
CC2

CC1
CC2
2 1 2 1
PORT 3 12 VDD PORT 3 12 VDD

VBUS_DET 4 11 EN_N VBUS_DET 4 11 EN

ADDR 5 10 ADDR 5 10 GND

GND

INT_N/OUT3 6 9 ID INT_N/OUT3 6 9 ID
7 8 7 8
SDA/OUT1

SCL/OUT2

SDA/OUT1

SCL/OUT2
Pin Functions
PIN
TYPE DESCRIPTION
NAME TUSB320LA TUSB320HA
CC1 1 1 I/O Type-C configuration channel signal 1
CC2 2 2 I/O Type-C configuration channel signal 2
Tri-level input pin to indicate port mode. The state of this pin is sampled when EN_N is
asserted low in the TUSB320L device, EN is asserted high in the TUSB320H device, and VDD
is active. This pin is also sampled following a I2C_SOFT_RESET.
PORT (1) 3 3 I
H - DFP (Pull-up to VDD if DFP mode is desired)
NC - DRP (Leave unconnected if DRP mode is desired)
L - UFP (Pull-down or tie to GND if UFP mode is desired)
5-V to 28-V VBUS input voltage. VBUS detection determines UFP attachment. One 900-kΩ
VBUS_DET (1) 4 4 I
external resistor required between system VBUS and VBUS_DET pin.
Tri-level input pin to indicate I2C address or GPIO mode:
H — I2C is enabled and I2C 7-bit address is 0x67.
ADDR (1) 5 5 I NC — GPIO mode (I2C is disabled)
L — I2C is enabled and I2C 7-bit address is 0x47.
ADDR pin should be pulled up to VDD if high configuration is desired
The INT_N/OUT3 is a dual-function pin. When used as the INT_N, the pin is an open drain
output in I2C control mode and is an active low interrupt signal for indicating changes in I2C
INT_N/OUT3 (1) 6 6 O
registers. When used as OUT3, the pin is in audio accessory detect in GPIO mode: no
detection (H), audio accessory connection detected (L).
The SDA/OUT1 is a dual-function pin. When I2C is enabled (ADDR pin is high or low), this pin
SDA/OUT1 (1) (2) 7 7 I/O is the I2C communication data signal. When in GPIO mode (ADDR pin is NC), this pin is an
open drain output for communicating Type-C current mode detect when the device is in UFP
mode: Refer to Table 3 for more details.
The SCL/OUT2 is a dual function pin. When I2C is enabled (ADDR pin is high or low), this pin
SCL/OUT2 (1) (2)
8 8 I/O is the I2C communication clock signal. When in GPIO mode (ADDR pin is NC), this pin is an
open drain output for communicating Type-C current mode detect when the device is in UFP
mode: Refer to Table 3 for more details.
Open drain output; asserted low when the CC pins detect device attachment when port is a
ID 9 9 O
source (DFP), or dual-role (DRP) acting as source (DFP).
GND 10 10 G Ground
Enable signal; active low. Pulled up to VDD internally to disable the TUSB320L device. If
EN_N 11 — I controlled externally, must be held low at least for 50 ms after VDD has reached its valid
voltage level.
Enable signal; active high. Pulled down to GND internally to disable the TUSB320H device. If
EN — 11 I controlled externally, must be held low at least for 50 ms after VDD has reached its valid
voltage level.
VDD 12 12 P Positive supply voltage. VDD must ramp within 25 ms or less

(1) When VDD is off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, OUT[3:1] pins) could back-drive the TUSB320 device if not
handled properly. When necessary to pull these pins up, it is recommended to pullup PORT, ADDR, and INT_N/OUT3 to the device VDD
supply. The VBUS_DET must be pulled up to VBUS through a 900-kΩ resistor.
(2) When using the 3.3 V supply for I2C, the end user must ensure that the VDD is 3 V and above. Otherwise the I2C may back power the
device.

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage VDD –0.3 6 V
PORT, ADDR, ID, EN_N, INT_N/OUT3 –0.3 VDD + 0.3
CC1, CC2 –0.3 6 V
Control pins
SDA/OUT1, SCL/OUT2 –0.3 VDD + 0.3
VBUS_DET , EN –0.3 4
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±3000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±1500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range 2.7 5 V
VBUS System VBUS voltage 4 5 28 V
TUSB320HAI and TUSB320LAI Operating free air temperature
TA –40 25 85 °C
range

6.4 Thermal Information

TUSB320
THERMAL METRIC (1) RWB (X2QFN) UNIT
12 PINS
RθJA Junction-to-ambient thermal resistance 169.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 68.1 °C/W
RθJB Junction-to-board thermal resistance 83.4 °C/W
ψJT Junction-to-top characterization parameter 2.2 °C/W
ψJB Junction-to-board characterization parameter 83.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and C Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
POWER CONSUMPTION
Current consumption in unattached mode when port is
unconnected and waiting for connection. [VDD = 4.5 V,
IUNATTACHED_UFP 70 µA
EN_N (TUSB320LA) = L, EN (TUSB320HA) = H, ADDR =
NC, PORT = L]
Current consumption in active mode. [VDD = 4.5 V, EN_N
IACTIVE_UFP (TUSB320LA) = L, EN (TUSB320HA) = H, ADDR = NC, 70 µA
PORT = L]
Leakage current when VDD is supplied, but the TUSB320
ISHUTDOWN device is not enabled. [VDD = 4.5 V, EN_N (TUSB320LA) = 0.04 µA
H, EN (TUSB320HA) = L]
CC1 AND CC2 PINS
RCC_DB Pulldown resistor when in dead-battery mode. 4.1 5.1 6.1 kΩ
RCC_D Pulldown resistor when in UFP or DRP mode. 4.6 5.1 5.6 kΩ
Voltage level range for detecting a DFP attach when
VUFP_CC_USB configured as a UFP and DFP is advertising default current 0.25 0.61 V
source capability.
Voltage level range for detecting a DFP attach when
VUFP_CC_MED configured as a UFP and DFP is advertising medium (1.5- 0.7 1.16 V
A) current source capability.
Voltage level range for detecting a DFP attach when
VUFP_CC_HIGH configured as a UFP and DFP is advertising high (3-A) 1.31 2.04 V
current source capability.
Voltage threshold for detecting a UFP attach when
VTH_DFP_CC_USB configured as a DFP and advertising default current source 1.51 1.6 1.64 V
capability.
Voltage threshold for detecting a UFP attach when
VTH_DFP_CC_MED configured as a DFP and advertising medium current (1.5- 1.51 1.6 1.64 V
A) source capability.
Voltage threshold for detecting a UFP attach when
VTH_DFP_CC_HIGH configured as a DFP and advertising high current (3.0-A) 2.46 2.6 2.74 V
source capability.
Default mode pullup current source when operating in DFP
ICC_DEFAULT_P 64 80 96 µA
or DRP mode.
Medium (1.5-A) mode pullup current source when
ICC_MED_P 166 180 194 µA
operating in DFP or DRP mode.
High (3-A) mode pullup current source when operating in
ICC_HIGH_P 304 330 356 µA
DFP or DRP mode. (1)
CONTROL PINS: PORT, ADDR, INT/OUT3, EN_N, EN, ID
Low-level control signal input voltage (PORT, ADDR,
VIL 0.4 V
EN_N, EN)
VIM Mid-level control signal input voltage (PORT, ADDR) 0.28 × VDD 0.56 × VDD V
High-level control signal input voltage (PORT, ADDR,
VIH VDD – 0.3 VDD V
EN_N)
High-Level control signal input voltage for EN for
VIH_EN 1.05 3.65 V
TUSB320HA
IIH High-level input current –20 20 µA
IIL Low-level input current –10 10 µA
VDD = 0 V; ID = 5
IID_LEAKAGE Current Leakage on ID pin 10 µA
V
REN_N Internal pullup resistance for EN_N for TUSB320LA 1.1 MΩ
REN Internal pulldown resistance for EN for TUSB320HA 500 kΩ
Rpu (2) Internal pullup resistance (PORT, ADDR) 588 kΩ
(2)
Rpd Internal pulldown resistance (PORT, ADDR) 1.1 MΩ
Low-level signal output voltage (open-drain) (INT_N/OUT3,
VOL IOL = –1.6 mA 0.4 V
ID)

(1) VDD must be 3.5 V or greater to advertise 3 A current.

(2) Internal pullup and pulldown for PORT and ADDR are removed after the device has sampled EN = high or EN_N = low.
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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
TEST
PARAMETER MIN TYP MAX UNIT
CONDITIONS
External pullup resistor on open drain IOs (INT_N/OUT3,
Rp_ODext 200 kΩ
ID)
Rp_TLext Tri-level input external pullup resistor (PORT, ADDR) 4.7 kΩ
I2C - SDA/OUT1, SCL/OUT2 CAN OPERATE FROM 1.8 V OR 3.3 V (±10%) (3)
VDD_I2C Supply range for I2C (SDA/OUT1, SCL/OUT2) 1.65 1.8 3.6 V
VIH High-level signal voltage 1.05 3.6 V
VIL Low-level signal voltage 0.4 V
VOL Low-level signal output voltage (open drain) IOL = –1.6 mA 0.4 V
VBUS_DET IO PINS (CONNECTED TO SYSTEM VBUS SIGNAL)
VBUS_THR VBUS threshold range See Figure 1 2.95 3.3 3.8 V
RVBUS External resistor between VBUS and VBUS_DET pin 855 887 920 KΩ
RVBUS_PD Internal pulldown resistance for VBUS_DET 95 KΩ
2
(3) When using 3.3 V for I C, customer must ensure VDD is above 3.0 V at all times.

6.6 Timing Requirements

MIN NOM MAX UNIT
2
I C (SDA, SCL)
tSU:DAT Data setup time 100 ns
tHD;DAT Data hold time 10 ns
tSU:STA Set-up time, SCL to start condition 0.6 µs
tHD:STA Hold time (repeated), start condition to SCL 0.6 µs
tSU:STO Set up time for stop condition 0.6 µs
tBUF Bus free time between a stop and start condition 1.3 µs
tVD;DAT Data valid time 0.9 µs
tVD;ACK Data valid acknowledge time 0.9 µs
fSCL SCL clock frequency; I2C mode for local I2C control 400 kHz
tr Rise time of both SDA and SCL signals 300 ns
tf Fall time of both SDA and SCL signals 300 ns
CBUS_100KHZ Total capacitive load for each bus line when operating at ≤ 100 kHz 400 pF
CBUS_400KHz Total capacitive load for each bus line when operating at 400 kHz 100 pF

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power on default of CC1 and CC2 voltage debounce DEBOUCE
tCCCB_DEFAULT 168 ms
time register = 2'b00
tVBUS_DB Debounce of VBUS_DET pin after valid VBUS_THR 2 ms
Power-on default of percentage of time DRP DRP_DUTY_CYCLE
tDRP_DUTY_CYCLE 30%
advertises DFP during a tDRP register = 2'b00
The period during which the TUSB320HA or the
tDRP TUSB320LA in DFP mode completes a DFP to UFP 50 75 100 ms
and back advertisement.
Time from TUSB320LA EN_N low or TUSB320HA EN
tI2C_EN 100 ms
high and VDD active to I2C access available
tSOFT_RESET Soft reset duration 26 49 95 ms

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VBUS

VBUS_THR

TVBUS_DB

0V

Figure 1. VBUS Detect and Debounce

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7 Detailed Description

7.1 Overview
The USB Type-C ecosystem operates around a small form factor connector and cable that is flippable and
reversible. Because of the nature of the connector, a scheme is required to determine the connector orientation.
Additional schemes are required to determine when a USB port is attached and what the acting role of the USB
port (DFP, UFP, DRP) is, as well as to communicate Type-C current capabilities. These schemes are
implemented over the CC pins according to the USB Type-C pecification. The TUSB320 devices provide
Configuration Channel (CC) logic for determining USB port attach and detach, role detection, cable orientation,
and Type-C current mode. The TUSB320 devices also contains several features such as mode configuration and
low standby current which make these devices ideal for source or sinks in USB2.0 applications.

VDD
ADDR
3-State Buffer
PORT

CC1

Connection and
Digital Controller cable detection
CTRL_EN_N
CTRL_INT

VBUS_ON

CC2
CTRL_ID

CTRL_INT

CTRL_ID

SDA/OUT1 I2C CSR

VBUS_ON

SCL/OUT2

Open Drain
Output
CTRL_EN VBUS Detection
EN_N EN_N Logic
INT/OUT3
GND

ID

SYS_VBUS
VBUS_DET

900 K ±1%

Copyright © 2016, Texas Instruments Incorporated

Figure 2. Functional Block Diagram of TUSB320

7.1.1 Cables, Adapters, and Direct Connect Devices

Type-C specification defines several cables, plugs, and receptacles to be used to attach ports. The TUSB320
devices support all cables, receptacles, and plugs. The TUSB320 devices do not support any USB Type-C
feature which requires USB power delivery communication over CC lines like e-marking or alternate mode.

[Link] USB Type-C Receptacles and Plugs

Below is list of Type-C receptacles and plugs supported by the TUSB320 devices:
• USB Type-C receptacle for USB2.0 platforms and devices

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Overview (continued)
• USB full-featured Type-C plug
• USB2.0 Type-C plug

[Link] USB Type-C Cables

Below is a list of Type-C cables types supported by the TUSB320 devices:
• USB full-featured Type-C cable
• USB2.0 Type-C cable with USB2.0 plug
• Captive cable on remote device with either a USB full-featured plug or USB2.0 plug

[Link] Legacy Cables and Adapters

The TUSB320 devices support legacy cable adapters as defined by the Type-C specification. The cable adapter
must correspond to the mode configuration of a TUSB320 device.
Figure 3 displays the TUSB320 Legacy Adapter Implementation Circuit.

To System VBUS detection

VBUS

900 kΩ ± 1%
Rp (56k ± 5%)
VBUS_DET

TUSB320
CC CC

Legacy Host Adapter Rd (5.1k ± 10%)

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Figure 3. Legacy Adapter Implementation Circuit

[Link] Direct Connect Devices

The TUSB320 devices support the attaching and detaching of a direct-connect device.

[Link] Audio Adapters

Additionally, the TUSB320 devices support audio adapters for audio accessory mode, including:
• Passive Audio Adapter
• Charge Through Audio Adapter

7.2 Feature Description

7.2.1 Port Role Configuration
The TUSB320 devices can be configured as a downstream facing port (DFP), upstream facing port (UFP), or
dual-role port (DRP) using the tri-level PORT pin. The PORT pin should be pulled high to VDD using a pullup
resistance, low to GND or left as floated on the PCB to achieve the desired mode. This flexibility allows a
TUSB320 device to be used in a variety of applications. A TUSB320 device samples the PORT pin after reset
and maintains the desired mode until the TUSB320 device is reset again. The port role can also be selected
through I2C registers. Table 1 lists the supported features in each mode:

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Feature Description (continued)

Table 1. Supported Features for the TUSB320 Device by Mode
PORT PIN
HIGH LOW NC
SUPPORTED (DFP ONLY) (UFP ONLY) (DRP)
FEATURES
Port attach and
Yes Yes Yes
detach
Cable orientation
Yes Yes Yes
(through I2C)
Current advertisement Yes - Yes (DFP)
Current detection - Yes Yes (UFP)
Accessory modes
Yes Yes Yes
(audio and debug)
[Link] - - Yes
[Link] - - Yes
Active cable detection Yes - Yes (DFP)
I2C / GPIO Yes Yes Yes
Legacy cables Yes Yes Yes
VBUS detection - Yes Yes (UFP)

[Link] Downstream Facing Port (DFP) - Source

The TUSB320 device can be configured as a DFP-only by pulling the PORT pin high through a resistance to VDD
or by changing the MODE_SELECT register. In DFP-only mode, the TUSB320 device constantly presents Rps
on both CC. In DFP-only mode, the TUSB320 device initially advertises default USB Type-C current. The Type-C
current can be adjusted through I2C if the system requires to increase the amount advertised. The TUSB320
device adjusts the Rps to match the desired Type-C current advertisement. In GPIO mode, the TUSB320 device
only advertises default Type-C current.
When configured as a DFP, the TUSB320 device can operate with older USB Type-C 1.0 devices except for a
USB Type-C 1.0 DRP device. A USB Type-C 1.1 compliant DFP can not connect to a Type-C 1.0 DRP. Because
the TUSB320 device is compliant to Type-C 1.1, the TUSB320 device can not operate with a USB Type-C 1.0
DRP device. This limitation is a result of a backwards compatibility problem between USB Type-C 1.1 DFP and a
USB Type-C 1.0 DRP.

[Link] Upstream Facing Port (UFP) - Sink

The TUSB320 device can be configured as a UFP only by pulling the PORT pin low to GND. In UFP mode, the
TUSB320 device constantly presents pulldown resistors (Rd) on both CC pins. The TUSB320 device monitors
the CC pins for the voltage level corresponding to the Type-C mode current advertisement by the connected
DFP. The TUSB320 device debounces the CC pins and wait for VBUS detection before successfully attaching. As
a UFP, the TUSB320 device detects and communicates the advertised current level of the DFP to the system
through the OUT1 and OUT2 GPIOs (if in GPIO mode) or through the I2C CURRENT_MODE_DETECT register
one time in the [Link] state.

[Link] Dual Role Port (DRP)

The TUSB320 device can be configured to operate as a DRP when the PORT pin is left floated on the PCB. In
DRP mode, the TUSB320 device toggles between operating as a DFP and a UFP. When functioning as a DFP in
DRP mode, the TUSB320 device complies with all operations as defined for a DFP according to the Type-C
specification. When presenting as a UFP in DRP mode, the TUSB320 device operates as defined for a UFP
according to the Type-C specification.

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The TUSB320 supports two optional Type-C DRP features called [Link] and [Link]. Products supporting
dual-role functionality may have a requirement to be a source (DFP) or a sink (UFP) when connected to another
dual-role capable product. For example, a dual-role capable notebook can be a source when connected to a
tablet, or a cell phone can be a sink when connected to a notebook or tablet. When standard DRP products
(products which don’t support either [Link] or [Link]) are connected together, the role (UFP or DFP)
outcome is not predetermined. These two optional DRP features provide a means for dual-role capable products
to connect to another dual-role capable product in the role desired. [Link] and [Link] are only available
when TUSB320 is configured in I2C mode. When operating in GPIO mode, the TUSB320 will always operate as
a standard DRP.
The [Link] feature of the TUSB320 device provides a means for a DRP product to connect as a DFP when
connected to another DRP product that doesn’t implement [Link]. When two products which implement
[Link] are connected together, the role outcome of either UFP or DFP is the same as a standard DRP.
[Link] is enabled by changing I2C register SOURCE_PREF to 2’b11. Once this register is changed to 2’b11,
the TUSB320 will always attempt to connect as a DFP when attached to another DRP capable device.
The [Link] feature of the TUSB320 device provides a method for a DRP product to connect as a UFP when
connected to another DRP product that doesn’t implement [Link]. When two products which implement
[Link] are connected together, the role outcome of either UFP or DFP is the same as a standard DRP.
[Link] is enabled by changing I2C register SOURCE_PREF to 2’b01. Once this register is changed to 2’b01,
the TUSB320 will always attempt to connect as a UFP when attached to another DRP capable device.

7.2.2 Type-C Current Mode

When a valid cable detection and attach have been completed, the DFP has the option to advertise the level of
Type-C current a UFP can sink. The default current advertisement for the TUSB320 device is max of 500 mA (for
USB2.0) or max of 900 mA (for USB3.1). If a higher level of current is available, the I2C registers can be written
to provide medium current at 1.5 A or high current at 3 A. When the CURRENT_MODE_ADVERTISE register
has been written to advertise higher than default current, the DFP adjusts the Rps for the specified current level.
If a DFP advertises 3 A, system designer must ensure that the VDD of the TUSB320 device is 3.5 V or greater.
Table 2 lists the Type-C current advertisements in GPIO an I2C modes.

Table 2. Type-C Current Advertisement for GPIO and I2C Modes

GPIO MODE (ADDR PIN IN NC) I2C MODE (ADDR PIN H, L)
TYPE-C CURRENT
UFP (PORT PIN L) DFP (PORT PIN H) UFP DFP
max of 500
mA (USB2.0) I2C register default is 500
Default Only advertisement
max of 900 Current mode detected Current mode detected or 900 mA (max)
mA (USB3.1) and output through OUT1 and read through I2C
Medium - 1.5 A (max) / OUT2 register Advertisement selected
N/A through writing I2C
High - 3 A (max) register

7.2.3 Accessory Support

The TUSB320 device supports audio and debug accessories in UFP, DFP mode and DRP mode. Audio and
debug accessory support is provided through reading of I2C registers. Audio accessory is also supported through
GPIO mode with INT_N/OUT3 pin (audio accessory is detected when INT_N/OUT3 pin is low).

[Link] Audio Accessory

Audio accessory mode is supported through two types of adapters. First, the passive audio adapter can be used
to convert the Type-C connector into an audio port. To effectively detect the passive audio adapter, the TUSB320
device must detect a resistance < Ra on both of the CC pins.
Secondly, a charge through audio adapter can be used. The primary difference between a passive and charge
through adapter is that the charge through adapter supplies 500 mA of current over VBUS. The charge through
adapter contains a receptacle and a plug. The plug acts as a DFP and supply VBUS when the plug detects a
connection.
When the TUSB320 device is configured in GPIO mode, OUT3 pin determines if an audio accessory is
connected. When an audio accessory is detected, the OUT3 pin is pulled low.

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[Link] Debug Accessory

Debug is an additional state supported by USB Type-C. The specification does not define a specific user
scenario for this state, but the specification is important because the end user could use debug accessory mode
to enter a test state for production specific to the application. The TUBS320 device will detect a debug accessory
if Rd or Rp is detected on both CC1 and CC2.

7.2.4 I2C and GPIO Control

The TUSB320 device can be configured for I2C communication or GPIO outputs using the ADDR pin. The ADDR
pin is a tri-level control pin. When the ADDR pin is left floating (NC), the TUSB320 device is in GPIO output
mode. When the ADDR pin is pulled high or pulled low, the TUSB320 device is in I2C mode.
All outputs for the TUSB320 device are open drain configuration.
The OUT1 and OUT2 pins are used to output the Type-C current mode when in GPIO mode. Additionally, the
OUT3 pin is used to communicate the audio accessory mode in GPIO mode. Table 3 lists the output pin settings.
See the Pin Configuration and Functions section for more information.

Table 3. Simplified Operation for OUT1 and OUT2

OUT1 OUT2 ADVERTISEMENT
H H Default Current in Unattached State
H L Default Current in Attached State
L H Medium Current (1.5 A) in Attached State
L L High Current (3.0 A) in Attached State

When operating in I2C mode, the TUSB320 device uses the SCL and SDA lines for clock and data and the
INT_N pin to communicate a change in I2C registers, or an interrupt, to the system. The INT_N pin is pulled low
when the TUSB320 device updates the registers with new information. The INT_N pin is open drain. The
INTERRUPT_STATUS register will be set when the INT_N pin is pulled low. To clear the INTERRUPT_STATUS
register, the end user writes to I2C.
When operating in GPIO mode, the OUT3 pin is used in place of the INT_N pin to determine if an audio
accessory is detected and attached. The OUT3 pin is pulled low when an audio accessory is detected.

NOTE
When using the 3.3 V supply for I2C, the end user must ensure that the VDD is 3 V and
above. Otherwise the I2C can back power the device.

7.2.5 VBUS Detection

The TUSB320 device supports VBUS detection according to the Type-C specification. VBUS detection is used to
determine the attachment and detachment of a UFP and to determine the entering and exiting of accessary
modes. VBUS detection is also used to successfully resolve the role in DRP mode.
The system VBUS voltage must be routed through a 900-kΩ resistor to the VBUS_DET pin on the TUSB320
device if the PORT pin is configured as a DRP or a UFP. If the TUSB320 device is configured as a DFP and only
ever used in DFP mode, the VBUS_DET pin can be left unconnected.

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7.3 Device Functional Modes

The TUSB320 device has four functional modes. Table 4 lists these modes:

Table 4. USB Type-C States According to TUSB320 Functional Modes

MODES GENERAL BEHAVIOR PORT PIN STATES (1)
[Link]
[Link]
UFP
[Link]
USB port unattached. ID, PORT [Link]
Unattached operational. I2C on. CC pins
configure according to PORT pin. Toggle [Link] → [Link]
DRP
[Link] or [Link]
[Link]
DFP
[Link]
[Link]
UFP Audio accessory
Debug [Link]
[Link]
USB port attached. All GPIOs [Link]
Active DRP
operational. I2C on. Audio accessory
Debug [Link] or Debug [Link]
[Link]
DFP Audio accessory
Debug [Link]
No operation.
Dead battery UFP/DRP/DFP Default device state to UFP/SNK with Rd.
VDD not available.
VDD available.
Shutdown TUSB320LA EN_N pin high. UFP/DRP/DFP Default device state to UFP/SNK with Rd.
TUSB320HA EN pin low.

(1) Required; not in sequential order.

7.3.1 Unattached Mode

Unattached mode is the primary mode of operation for the TUSB320 device, because a USB port can be
unattached for a lengthy period of time. In unattached mode, VDD is available, and all IOs and I2C are
operational. After the TUSB320 device is powered up, the part enters unattached mode until a successful attach
has been determined. Initially, right after power up, the TUSB320 device comes up as an [Link]. The
TUSB320 device checks the PORT pin and operates according to the mode configuration. The TUSB320 device
toggles between the UFP and the DFP if configured as a DRP. In unattached mode, I2C can be used to change
the mode configuration or port role if the board configuration of the PORT pin is not the desired mode. Writing to
the I2C MODE_SELECT register can override the PORT pin in unattached mode. The PORT pin is only sampled
at reset (EN_N high to low transition for the TUSB320LA device or the EN low to high transition for
theTUSB320HA device), after I2C_SOFT_RESET, or power up. I2C must be used after reset to change the
device mode configuration.

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7.3.2 Active Mode

Active mode is defined as the port being attached. In active mode, all GPIOs are operational, and I2C is read /
write (R/W). When in active mode, the TUSB320 device communicates to the AP that the USB port is attached.
This communication happens through the ID pin if TUSB320 is configured as a DFP or DRP connect as source.
If TUSB320 is configured as a UFP or a DRP connected as a sink, the OUT1/OUT2 and INT_N/OUT3 pins are
used. The TUSB320 device exits active mode under the following conditions:
• Cable unplug
• VBUS removal if attached as a UFP
• Dead battery; system battery or supply is removed
• TUSB320LA EN_N pin floated or pulled high
• TUSB320HA EN pin floated or pulled low.
During active mode, I2C be used to change the mode configuration following the sequence below. This same
sequence is valid when TUSB320 is in unattached mode.
• Set the DISABLE_TERM register (address 0x0A bit 0) to a 1'b1.
• Change the MODE_SELECT register (address 0x0A bits 5:4) to desired mode of operation.
• Wait 5 ms.
• Clear the DISABLE_TERM register (address 0x0A bit 0) to 1'b0.

7.3.3 Dead Battery Mode

During dead battery mode, VDD is not available. CC pins always default to pulldown resistors in dead battery
mode. Dead battery mode means:
• TUSB320 in UFP with 5.1-kΩ ± 20% Rd; cable connected and providing charge
• TUSB320 in UFP with 5.1-kΩ ± 20% Rd; nothing connected (application could be off or have a discharged
battery)

NOTE
When VDD is off, the TUSB320 non-failsafe pins (VBUS_DET, ADDR, PORT, OUT[3:1]
pins) could back-drive the TUSB320 device if not handled properly. When necessary to
pull these pins up, TI recommendeds pulling up PORT, ADDR, and INT_N/OUT3 to the
device’s VDD supply. The VBUS_DET must be pulled up to VBUS through a 900-kΩ
resistor.

7.3.4 Shutdown Mode

Shutdown mode for TUSB320LA device is defined as follows:
• Supply voltage available and EN_N pin is pulled high or floating.
• EN_N pin has internal pullup resistor.
• The TUSB320LA device is off, but still maintains the Rd on the CC pins
Shutdown mode for TUSB320HA device is defined as follows:
• Supply voltage available and EN pin is pulled low or floating.
• EN pin has internal pulldown resistor.
• The TUSB320HA device is off, but still maintains the Rd on the CC pins

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7.4 Programming
For further programmability, the TUSB320 device can be controlled using I2C. The TUSB320 device local I2C
interface is available for reading/writing after TI2C_EN when the device is powered up. The SCL and SDA terminals
are used for I2C clock and I2C data respectively. If I2C is the preferred method of control, the ADDR pin must be
set accordingly.

Table 5. TUSB320 I2C Addresses

TUSB320 I2C Target Address
ADDR pin Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W/R)
H 1 1 0 0 1 1 1 0/1
L 1 0 0 0 1 1 1 0/1

The following procedure should be followed to write to TUSB320 I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TUSB320 7-bit
address and a zero-value R/W bit to indicate a write cycle.
2. The TUSB320 device acknowledges the address cycle.
3. The master presents the sub-address (I2C register within the TUSB320 device) to be written, consisting of
one byte of data, MSB-first.
4. The TUSB320 device acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB320 device acknowledges the byte transfer.
7. The master can continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB320 device.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure should be followed to read the TUSB320 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB320 7-bit
address and a one-value R/W bit to indicate a read cycle.
2. The TUSB320 device acknowledges the address cycle.
3. The TUSB320 device transmits the contents of the memory registers MSB-first starting at register 00h or last
read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TUSB320 device
starts at the sub-address specified in the write.
4. The TUSB320 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the TUSB320 device transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
The following procedure should be followed for setting a starting sub-address for I2C reads:
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB320 7-bit
address and a zero-value R/W bit to indicate a read cycle.
2. The TUSB320 device acknowledges the address cycle.
3. The master presents the sub-address (I2C register within the TUSB320 device) to be read, consisting of one
byte of data, MSB-first.
4. The TUSB320 device acknowledges the sub-address cycle.
5. The master terminates the read operation by generating a stop condition (P).

NOTE
If no sub-addressing is included for the read procedure, then the reads start at register
offset 00h and continue byte-by-byte through the registers until the I2C master terminates
the read operation. If a I2C address write occurred prior to the read, then the reads start at
the sub-address specified by the address write.

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7.5 Register Maps

Table 6. CSR Registers
ACCESS
NAME MEANING
TAG
R Read The field can be read by software.
W Write The field can be written by software.
S Set The field can be set by a write of one. Writes of zeros to the field have no effect.
C Clear The field can be cleared by a write of one. Writes of zeros to the field have no effect.
U Update Hardware can autonomously update this field.
NA No Access Not accessible or not applicable.

7.5.1 CSR Registers (address = 0x00 – 0x07)

Figure 4. CSR Registers (address = 0x00 – 0x07)
7 6 5 4 3 2 1 0
DEVICE_ID
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. CSR Registers (address = 0x00 – 0x07)

Bit Field Type Reset Description
For the TUSB320 device these fields return a string of ASCII
characters returning TUSB320
7:0 DEVICE_ID R
Addresses 0x07 - 0x00 = {0x00 0x54 0x55 0x53 0x42 0x33 0x32
0x30}

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7.5.2 CSR Registers (address = 0x08)

Figure 5. CSR Registers (address = 0x08)
7 6 5 4 3 2 1 0
ACTIVE_CABLE_
CURRENT_MODE_ADVERTISE CURRENT_MODE_DETECT ACCESSORY_CONNECTED
DETECTION
RW RU RU RU
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. CSR Registers (address = 0x08)

Bit Field Type Reset Description
These bits are programmed by the application to raise the
current advertisement from default.
00 – Default (500 mA / 900 mA) initial value at startup
7:6 CURRENT_MODE_ADVERTISE RW 00
01 – Mid (1.5 A)
10 – High (3 A)
11 – Reserved
These bits are set when a UFP determines the Type-C Current
mode.
00 – Default (value at start up)
5:4 CURRENT_MODE_DETECT RU 00
01 – Medium
10 – Audio Charged through accessory – 500 mA
11 – High
These bits are read by the application to determine if an
accessory was attached.
000 – No accessory attached (default)
001 – Reserved
010 – Reserved
011 – Reserved
3:1 ACCESSORY_CONNECTED RU 000
100 – Audio accessory
101 – Audio charged thru accessory
110 – Debug accessory when the TUSB320 device is connected
as a DFP.
111 – Debug accessory when the TUSB320 device is connected
as a UFP.
This flag indicates that an active cable has been plugged into
0 ACTIVE_CABLE_DETECTION RU 0 the Type-C connector. When this field is set, an active cable is
detected.

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7.5.3 CSR Registers (address = 0x09)

Figure 6. CSR Registers (address = 0x09)
7 6 5 4 3 2 1 0
DISABLE_UFP_
ATTACHED_STATE CABLE_DIR INTERRUPT_STATUS — DRP_DUTY_CYCLE
ACCESSORY
RU RU RCU R RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. CSR Registers (address = 0x09)

Bit Field Type Reset Description
This is an additional method to communicate attach other than
the ID pin. These bits can be read by the application to
determine what was attached.
7:6 ATTACHED_STATE 00 00 – Not attached (default)
RU
01 – [Link] (DFP)
10 – [Link] (UFP)
11 – Attached to an accessory
Cable orientation. The application can read these bits for cable
orientation information.
5 CABLE_DIR RU 1
0 – CC1
1 – CC2 (default)
The INT pin is pulled low whenever a CSR with RU in Access
field changes. When a CSR change has occurred this bit should
be held at 1 until the application clears it. A write of 1'b1 is
required to clear this field.
4 INTERRUPT_STATUS RCU 0 0 – Clear
1 – Interrupt (When INT_N is pulled low, this bit will be 1. )
Note: SW must make sure the INTERRUPT_STATUS has been
cleared to zero. Rewrites to this register are needed for the
INT_N to be correctly asserted for all interrupt events.
3 Reserved R 0 Reserved
Percentage of time that a DRP advertises DFP during tDRP
00 – 30% (default)
2:1 DRP_DUTY_CYCLE RW 00 01 – 40%
10 – 50%
11 – 60%
Settings this field will disable UFP accessory support.
0 DISABLE_UFP_ACCESSORY RW 0 0 – UFP accessory support enabled (Default)
1 – UFP accessory support disabled

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7.5.4 CSR Registers (address = 0x0A)

Figure 7. CSR Registers (address = 0x0A)

7 6 5 4 3 2 1 0
DEBOUNCE MODE_SELECT I2C_SOFT_RESET SOURCE_PREF DISABLE_TERM
RW RW RSU RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. CSR Registers (address = 0x0A)

Bit Field Type Reset Description
The nominal amount of time the TUSB320 device debounces
the voltages on the CC pins.
00 – 168 ms (default)
7:6 DEBOUNCE RW 00
01 – 118 ms
10 – 134 ms
11 – 152 ms
This register can be written to set the TUSB320 device mode
operation. The ADDR pin must be set to I2C mode. If the default
is maintained, the TUSB320 device operates according to the
PORT pin levels and modes.
5:4 MODE_SELECT RW 00 00 – Maintain mode according to PORT pin selection (default)
01 – UFP mode ([Link])
10 – DFP mode([Link])
11 – DRP mode(start from [Link])
This resets the digital logic. The bit is self-clearing. A write of 1
starts the reset. The following registers can be affected after
setting this bit:
CURRENT_MODE_DETECT
3 I2C_SOFT_RESET RSU 0 ACTIVE_CABLE_DETECTION
ACCESSORY_CONNECTED
ATTACHED_STATE
CABLE_DIR
This field controls the TUSB320 behavior when configured as a
DRP.
00 – Standard DRP (default)
2:1 SOURCE_PREF RW 00
01 – DRP will perform [Link].
10 – Reserved.
11 – DRP will perform [Link].
This field will disable the termination on the CC pins and
transition the CC state machine of the TUSB320 device to the
Disable State.
0 DISABLE_TERM RW 0
0 – Termination enabled according to Port (Default)
1 – Termination disabled and state machine held in Disabled
state.

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7.5.5 CSR Registers (address = 0x45)

Figure 8. CSR Registers (address = 0x45)
7 6 5 4 3 2 1 0
— DISABLE_RD_RP —
R RW RW
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. CSR Registers (address = 0x45)

Bit Field Type Reset Description
7:3 Reserved R 00000 Reserved
When this field is set, Rd and Rp are disabled.
2 DISABLE_RD_RP RW 0 0 – Normal operation (default)
1 – Disable Rd and Rp
1:0 Reserved RW 00 For TI internal use only. Do not change default value.

7.5.6 CSR Registers (address = 0xA0)

Figure 9. CSR Registers (address = 0xA0)
7 6 5 4 3 2 1 0
REVISION
R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. CSR Registers (address = 0xA0)

Bit Field Type Reset Description
7:0 REVISION R 0x02 Revision of TUSB320. Defaults to 0x02.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TUSB320 device is a Type-C configuration channel logic and port controller. The TUSB320 device can
detect when a Type-C device is attached, what type of device is attached, the orientation of the cable, and power
capabilities (both detection and broadcast). The TUSB320 device can be used in a source application (DFP), in a
sink application (UFP), or a combination source/sink application (DRP).

8.2 Typical Application

8.2.1 DRP in I2C Mode
Figure 10 and Figure 11 show a Type-C configuration for the DRP mode.

5V Legacy TypeA VBUS

PMIC VBUS
Switch

VPH PORT
ID
USB TypeC Port

VBUS

USB TypeC Port

VBUS

2.7 - 5 V VDD CC1

VDD CC1
PORT CC/Mode CC2 ID CC/Mode CC2
Controller Controller
DP
GPIOs DP
Processor Processor GPIOs
DM
I2C I2C DM

TUSB320 TUSB320
Copyright © 2016, Texas Instruments Incorporated Copyright © 2016, Texas Instruments Incorporated

Figure 10. TUSB320 in DRP Mode Supporting Default Figure 11. TUSB320 in DRP Mode Supporting Advanced
Implementation Power Delivery

Figure 12 shows the TUSB320 device configured as a DRP in I2C mode.

USB VBUS Switch
(optional BC 1.2 support for legacy)

SCL
SDA

DM DM_OUT DM_IN
DP DP_OUT DP_IN
System VBUS
VIN VOUT
PS_EN EN
PS_FAULT# FAULT#
VBUS
I2C I/O
1.8V or 3.3V VBAT
USB2
150uF
OTG DM

and 100nF
DP

PMIC VBUS

200K 200K 900K A1 B12

VDD

4.7K 4.7K
VBUS_DET A2 B11

PORT A3 B10
Receptacle

A4 B9
Type C

INT# INT_N/OUT3 CC1 CC1

A5 B8

TUSB320LA CC2
A6 B7
ID ID CC2 A7 B6

A8 B5
SCL SCL/OUT2
A9 B4
ADDR

EN_N

GND

SDA SDA/OUT1 A10 B3

1uF A11 B2

A12 B1

Figure 12. DRP in I2C Mode Schematic

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Typical Application (continued)

[Link] Design Requirements
For this design example, use the parameters listed in Table 13:

Table 13. Design Requirements for DRP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) VBAT (less than 5 V)
Mode (I2C or GPIO) I2C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) DRP: PORT pin is NC
Shutdown support No

[Link] Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular use case, VBAT which must
be in the required VDD range is connected to the VDD pin. A 100-nF capacitor is placed near VDD.
The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR
pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or
3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.
The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA
device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the
EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which
puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not
implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.
The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is
an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ
resistor.
The ID pin is used to indicate when a connection has occurred if the TUSB320 device is a DFP while configured
for DRP. An OTG USB controller can use this pin to determine when to operate as a USB Host or USB Device.
When this pin is driven low, the OTG USB controller functions as a host and then enables VBUS. The Type-C
standard requires that a DFP not enable VBUS until the DFP is in the [Link] state. If the ID pin is not low
but VBUS is detected, then OTG USB controller functions as a device. The ID pin is open drain output and
requires an external pullup resistor. THe ID pin should be pulled up to VDD using a 200-kΩ resistor.
The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is not connected, the
TUSB320 device is in DRP mode. The Type-C port mode can also be controlled by the MODE_SELECT register
through the I2C interface.
The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This
large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day
systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the
recommended range.
The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the
TUSB320 device in a DRP mode, it alternates between UFP and DFP. If the TUSB320 device connects as a
UFP, the large bulk capacitance must be removed.

Table 14. USB2 Bulk Capacitance Requirements

PORT CONFIGURATION MIN MAX UNIT
Downstream facing port (DFP) 120 µF
Upstream facing port (UFP) 1 10 µF

22 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB320LAI TUSB320HAI

 TUSB320LAI, TUSB320HAI
[Link] SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017

[Link] Application Curves

Figure 13. Application Curve for DRP in I2C Mode

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: TUSB320LAI TUSB320HAI
TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017 [Link]

8.2.2 DFP in I2C Mode

Figure 14 and Figure 15 show a Type-C configuration for the DFP mode.

5V Legacy TypeA VBUS

PMIC VBUS
Switch
VDD

VPH PORT
ID

USB TypeC Port

USB TypeC Port

VDD VBUS
VBUS
2.7 - 5 V VDD CC1 VDD CC1
PORT CC/Mode CC2 ID CC/Mode CC2
Controller
Controller
DP
GPIOs DP
Processor GPIOs
DM Processor
I2C DM
I2C

TUSB320
TUSB320
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated

Figure 14. TUSB320 in DFP Mode Supporting Default Figure 15. TUSB320 in DFP Mode Supporting Advanced
Implementation Power Delivery

Figure 16 shows the TUSB320 device configured as a DFP in I2C mode.

USB VBUS Switch
(optional BC 1.2 support for legacy)

SCL
SDA

DM DM_OUT DM_IN
DP DP_OUT DP_IN
System VBUS
VIN VOUT
PS_EN EN
PS_FAULT# FAULT#
VBUS
I2C I/O
1.8V or 3.3V VDD_5V
USB2
150uF
OTG DM

and 100nF
DP

PMIC VBUS

200K 200K 900K A1 B12

VDD

4.7K 4.7K 200K

VBUS_DET A2 B11

PORT A3 B10

Receptacle
A4 B9

Type C
INT# INT_N/OUT3 CC1 CC1
A5 B8

TUSB320LA CC2
A6 B7
ID ID CC2 A7 B6

A8 B5
SCL SCL/OUT2
A9 B4
ADDR

EN_N

GND

SDA SDA/OUT1 A10 B3

A11 B2

A12 B1

Figure 16. DFP in I2C Mode Schematic

[Link] Design Requirements

For this design example, use the parameters listed in Table 15:

Table 15. Design Requirements for DFP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) 5V
2 2
Mode (I C or GPIO) I C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) DFP: PORT pin is pulled up
Shutdown support No

24 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB320LAI TUSB320HAI

 TUSB320LAI, TUSB320HAI
[Link] SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017

[Link] Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular case, VDD is set to 5 V. A
100-nF capacitor is placed near VDD.
The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this particular case,
the ADDR pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to
either 1.8 V or 3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the
I2C interface.
The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA
device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the
EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which
puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not
implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.
The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is
an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ
resistor.
The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled high, the
TUSB320 device is in DFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register
through the I2C interface.
The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This
large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day
systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the
recommended range.
The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the
TUSB320 device in a DFP mode, a bulk capacitance of at least 120 µF is required. In this particular case, a 150-
µF capacitor was chosen.

[Link] Application Curves

Figure 17. Application Curve for DFP in I2C Mode

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: TUSB320LAI TUSB320HAI
TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017 [Link]

8.2.3 UFP in I2C Mode

Figure 18 and Figure 19 show a Type-C configuration for the UFP mode.

5V VBUS
PMIC VBUS

VPH PORT
ID

USB TypeC Port

VBUS

USB TypeC Port

VBUS

2.7 - 5 V VDD CC1

VDD CC1
PORT CC/Mode CC2
Controller ID CC/Mode CC2
DP
Controller
GPIOs DP
Processor GPIOs
I2C DM Processor DM
I2C

GND TUSB320
TUSB320
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated

Figure 18. TUSB320 in UFP Mode Supporting Default Figure 19. TUSB320 in UFP Mode Supporting Advanced
Implementation Power Delivery

Figure 20 shows the TUSB320 device configured as a UFP in I2C mode.

Optional power
TUSB320 with VBUS
less than 5.5V

DM
DP

VBUS

D1
I2C I/O
1.8V or 3.3V VDD_5V

USB2 DM

Device 100nF
DP

and PMIC VBUS

200K 200K 900K A1 B12

VDD

4.7K 4.7K
VBUS_DET A2 B11

PORT A3 B10

A4 B9

Receptacle
INT# INT_N/OUT3 CC1 CC1
A5 B8

Type C
TUSB320LA CC2
A6 B7
ID CC2 A7 B6

A8 B5
SCL SCL/OUT2
A9 B4
ADDR

EN_N

GND

SDA SDA/OUT1 A10 B3

1uF A11 B2

A12 B1
4.7K

Figure 20. UFP in I2C Mode Schematic

[Link] Design Requirements

For this design example, use the parameters listed in Table 16:

Table 16. Design Requirements for UFP in I2C Mode

DESIGN PARAMETER VALUE
VDD (2.75 V to 5 V) 5V
2 2
Mode (I C or GPIO) I C: ADDR pin must be pulled down or pulled up
I2C address (0x67 or 0x47) 0x47: ADDR pin must be pulled low or tied to GND
Type-C port type (UFP, DFP, or DRP) UFP: PORT pin is pulled down

26 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB320LAI TUSB320HAI

 TUSB320LAI, TUSB320HAI
[Link] SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017

Table 16. Design Requirements for UFP in I2C Mode (continued)

DESIGN PARAMETER VALUE
Shutdown support No

[Link] Detailed Design Procedure

The TUSB320 device supports a VDD in the range of 2.75 V to 5 V. In this particular case, VDD is set to 5 V. A
100-nF capacitor is placed near VDD. If VBUS is guaranteed to be less than 5.5 V, powering the TUSB320 device
through a diode can be implemented.
The TUSB320 device is placed into I2C mode by either pulling the ADDR pin high or low. In this case, the ADDR
pin is tied to GND which results in a I2C address of 0x47. The SDA and SCL must be pulled up to either 1.8 V or
3.3 V. When pulled up to 3.3 V, the VDD supply must be at least 3 V to keep from back-driving the I2C interface.
The TUSB320LA device can enter shutdown mode by pulling the EN_N pin high, which puts the TUSB320LA
device into a low power state. In this case, external control of the EN_N pin is not implemented and therefore the
EN_N pin is tied to GND. The TUSB320HA device can enter shutdown mode by pulling the EN pin low, which
puts the TUSB320HA device into a low power state. In this case, external control of the EN pin is not
implemented and therefore the EN pin is tied to 1.8 V or 3.3 V.
The INT_N/OUT3 pin is used to notify the PMIC when a change in the TUSB320 I2C registers occurs. This pin is
an open drain output and requires an external pullup resistor. The pin should be pulled up to VDD using a 200-kΩ
resistor.
The Type-C port mode is determined by the state of the PORT pin. When the PORT pin is pulled low, the
TUSB320 device is in UFP mode. The Type-C port mode can also be controlled by the MODE_SELECT register
through the I2C interface.
The VBUS_DET pin must be connected through a 900-kΩ resistor to VBUS on the Type-C that is connected. This
large resistor is required to protect the TUSB320 device from large VBUS voltage that is possible in present day
systems. This resistor along with internal pulldown keeps the voltage observed by the TUSB320 device in the
recommended range.
The USB2 specification requires the bulk capacitance on VBUS based on UFP or DFP. When operating the
TUSB320 device in a UFP mode, a bulk capacitance between 1 µF to 10 µF is required. In this particular case, a
1-µF capacitor was chosen.

[Link] Application Curves

Figure 21. Application Curve for UFP in I2C Mode

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 27

Product Folder Links: TUSB320LAI TUSB320HAI
TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017 [Link]

8.3 Initialization Setup

8.3.1 TUSB320LA Initialization Procedure
1. System is powered off (device has no VDD). The TUSB320LA device is configured internally in UFP mode
with Rds on CC pins (dead battery).
2. VDD ramps – POR circuit. VDD must ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT,
SCL, SDA, ADDR, PORT) must ramp with VDD or lag after VDD.
3. I2C supply ramps up.
4. The TUSB320LA device enters unattached mode and determines the voltage level from the PORT pin. This
determines the mode in which the TUSB320LA device operates (DFP, UFP, DRP).
5. The TUSB320LA device monitors the CC pins as a DFP and VBUS for attach as a UFP.
6. The TUSB320LA device enters active mode when attach has been successfully detected.

8.3.2 TUSB320HA Initialization Procedure

1. System is powered off (device has no VDD). The TUSB320HA device is configured internally in UFP mode
with Rds on CC pins (dead battery).
2. VDD ramps – POR circuit. VDD must ramp within 25 ms or less. IO pull-up power rail (i.e. pull up on ID, INT,
SCL, SDA, ADDR, PORT) must ramp with VDD or lag after VDD.
3. I2C supply ramps up.
4. The TUSB320HA device enters unattached mode and determines the voltage level from the PORT pin. This
determines the mode in which the TUSB320HA device operates (DFP, UFP, DRP).
5. The TUSB320HA device monitors the CC pins as a DFP and VBUS for attach as a UFP.
6. The TUSB320HA device enters active mode when attach has been successfully detected.

9 Power Supply Recommendations

The TUSB320 device has a wide power supply range from 2.7 to 5 V. The TUSB320 device can be run off of a
system power such as a battery.

28 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB320LAI TUSB320HAI

 TUSB320LAI, TUSB320HAI
[Link] SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017

10 Layout

10.1 Layout Guidelines

1. An extra trace (or stub) is created when connecting between more than two points. A trace connecting pin A6
to pin B6 will create a stub because the trace also has to go to the USB Host. Ensure that:
– A stub created by short on pin A6 (DP) and pin B6 (DP) at Type-C receptacle does not exceed 3.5 mm.
– A stub created by short on pin A7 (DM) and pin B7 (DM) at Type-C receptacle does not exceed 3.5 mm.
2. A 100-nF capacitor should be placed as close as possible to the TUSB320 VDD pin.

10.2 Layout Example

SCL/OUT2

Figure 22. TUSB320 Layout

Copyright © 2015–2017, Texas Instruments Incorporated Submit Documentation Feedback 29

Product Folder Links: TUSB320LAI TUSB320HAI
TUSB320LAI, TUSB320HAI
SLLSEQ8D – OCTOBER 2015 – REVISED MAY 2017 [Link]

11 Device and Documentation Support

11.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 17. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
TUSB320LAI Click here Click here Click here Click here Click here
TUSB320HAI Click here Click here Click here Click here Click here

11.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on [Link]. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

30 Submit Documentation Feedback Copyright © 2015–2017, Texas Instruments Incorporated

Product Folder Links: TUSB320LAI TUSB320HAI

 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

TUSB320HAIRWBR Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HA
TUSB320HAIRWBR.A Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 HA
TUSB320HAIRWBRG4 Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HA
TUSB320HAIRWBRG4.A Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 HA
TUSB320LAIRWBR Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 LA
TUSB320LAIRWBR.A Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 LA
TUSB320LAIRWBRG4 Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LA
TUSB320LAIRWBRG4.A Active Production X2QFN (RWB) | 12 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 85 LA

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 23-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB320HAIRWBR X2QFN RWB 12 3000 180.0 8.4 1.8 1.8 0.48 4.0 8.0 Q2
TUSB320HAIRWBRG4 X2QFN RWB 12 3000 180.0 8.4 1.8 1.8 0.48 4.0 8.0 Q2
TUSB320LAIRWBR X2QFN RWB 12 3000 180.0 8.4 1.8 1.8 0.48 4.0 8.0 Q2
TUSB320LAIRWBRG4 X2QFN RWB 12 3000 180.0 8.4 1.8 1.8 0.48 4.0 8.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 23-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TUSB320HAIRWBR X2QFN RWB 12 3000 210.0 185.0 35.0
TUSB320HAIRWBRG4 X2QFN RWB 12 3000 210.0 185.0 35.0
TUSB320LAIRWBR X2QFN RWB 12 3000 210.0 185.0 35.0
TUSB320LAIRWBRG4 X2QFN RWB 12 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RWB0012A SCALE 6.500
X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

1.65
B A
1.55

PIN 1 INDEX AREA

1.65
1.55

C
0.4 MAX

SEATING PLANE

0.05 C

2X 1.2 (0.13)
TYP
SYMM 0.05
6X 0.4
0.00
3 6

2
7
2X SYMM
0.4

1 0.4
8X
8 0.2

12 9
0.25
0.6 12X
4X 0.15
0.4
0.07 C B A
0.05 C

4221631/B 07/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

[Link]
 EXAMPLE BOARD LAYOUT
RWB0012A X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.3)
6X (0.4)
12 9

4X (0.7)
1
8
SYMM
2X (0.4)
(1.5)
7
2

8X (0.5)

3 6
12X (0.2) SYMM (R0.05) TYP

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:30X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

METAL SOLDER MASK

EXPOSED METAL OPENING

EXPOSED METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4221631/B 07/2017

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 ([Link]/lit/slua271).

[Link]
 EXAMPLE STENCIL DESIGN
RWB0012A X2QFN - 0.4 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

(1.3)

6X (0.4)
12 9

4X (0.67)

1
8

SYMM
2X (0.4)
(1.5)

2
7

8X
METAL

8X (0.5)

3 6
(R0.05) TYP
12X (0.2) SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

PADS 1,2,7 & 8

96% PRINTED SOLDER COVERAGE BY AREA
SCALE:50X

4221631/B 07/2017
NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
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Last updated 10/2025