HDL Coding Style

© 2002 Xilinx, Inc. All Rights Reserved

 Objective
After completing this module, you will be able to:
• Select a proper coding style to create efficient FPGA designs
• Specify Xilinx resources that need to be instantiated for various FPGA
synthesis tools

HDL Coding Style - 5 - 3 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 4 © 2002 Xilinx, Inc. All Rights Reserved

 Instantiation Versus Inference
• Instantiate a component when you must dictate exactly which resource
is needed
– Synthesis tool is unable to infer the resource
– Synthesis tool fails to infer the resource
• Xilinx recommends inference whenever possible
– Inference makes your code more portable
– Synthesis tools cannot estimate timing delays through instantiated components
• Xilinx recommends the use of the CORE Generator™ System to create
ALUs, fast multipliers, FIR Filters, etc. for instantiation

HDL Coding Style - 5 - 5 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop
Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 6 © 2002 Xilinx, Inc. All Rights Reserved

 Multiplexers
• Multiplexers are generated from IF and CASE statements
– IF/THEN statements generate priority encoders
– Use CASE to generate complex encoding
• There are several issues to consider with a multiplexer
– Delay and size
• Affected by the number of inputs and number of nested clauses to an IF/THEN
or CASE statement
– Unintended latches or clock enables
• Generated when IF/THEN or CASE statements do not cover all conditions

HDL Coding Style - 5 - 7 © 2002 Xilinx, Inc. All Rights Reserved

 Avoid Nested IF and CASE
Statements
• Nested IF or CASE statements infer cascaded logic
– More levels of logic → lower performance
• When nested IFs are necessary, put critical input signals on the
first (outer) IF statement
– The critical signal ends up in the last logic stage

HDL Coding Style - 5 - 8 © 2002 Xilinx, Inc. All Rights Reserved

 Unintended Latch Inference
• In IF/CASE statements, latches are inferred when:
– All possible input values are not covered
– All outputs are not defined in all branches
• When the IF/CASE statement is in a clocked process (VHDL) or
always block (Verilog), latches are not inferred
– Clock enables are inferred instead
– This is not “wrong,” but it might generate a long clock-enable equation
• Use default assignments before the IF/CASE statement to
prevent latches or inferred clock enables

HDL Coding Style - 5 - 9 © 2002 Xilinx, Inc. All Rights Reserved

 Clock Enables
• Coding style will determine if clock enables are used
• Reset and set have precedence over clock enable

VHDL Verilog
FF_AR_CE: process(ENABLE,CLK) always @(posedge CLOCK)
begin if (ENABLE)
if (CLK’event and CLK = ‘1’) then Q = D_IN;
if (ENABLE = ‘1’) then
Q <= D_IN;
end if;
end if;
end process

HDL Coding Style - 5 - 10 © 2002 Xilinx, Inc. All Rights Reserved

 State Machine Design
• Put the next-state logic in one
Inputs to FSM
CASE statement
S2
– The state register may also be S1
State
included here or in a separate Machine
process or always block Module S3
S5
• Put the state machine outputs
S4
in a separate process or
always block HDL Code
Next-state logic
– Easier for synthesis tools to
optimize logic this way State register
State machine outputs

HDL Coding Style - 5 - 11 © 2002 Xilinx, Inc. All Rights Reserved

 The Perfect State Machine
• The perfect state machine has
– Inputs: input signals, state jumps
– Outputs: output states, and control/enable signals to the rest of the design
– NO arithmetic logic, datapaths, or combinatorial functions inside the state
machine
Current State Feedback to Drive State Jumps

State Register
State
Next State Output State and Enables
Jumps
Input Signals Only!

HDL Coding Style - 5 - 12 © 2002 Xilinx, Inc. All Rights Reserved

 State Machine Encoding
• Use enumerated types to define state vectors (VHDL)
– Most synthesis tools have commands to extract and re-encode state
machines described in this way
• Use one-hot encoding for high-performance state machines
– Uses more registers, but simplifies next-state logic
– Experiment to discover how your synthesis tool chooses the default
encoding scheme
• Register state machine outputs for higher performance

HDL Coding Style - 5 - 13 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop
Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 14 © 2002 Xilinx, Inc. All Rights Reserved

 Instantiation Tips
• Use instantiation only when it is necessary to access device
features or increase performance or decrease area
– Exceptions are noted at the end of this section
• Limit the location of instantiated components to a few source files,
to make it easier to locate these components when porting the code

HDL Coding Style - 5 - 15 © 2002 Xilinx, Inc. All Rights Reserved

 Virtex-II Resources
• Shift register LUT (SRL16 / SRLC16)
• F5, F6, F7, and F8 MUX
• Carry Logic
• MULT_AND
• Memories (distributed and block, RAM and ROM)
• MULT18x18 / MULT18x18S
• SelectI/O
• I/O Registers (Single or Double Data Rate)
• Global clock buffers (BUFG, BUFGDLL, BUFGCE, BUFGMUX)
• DCM
• STARTUP_VIRTEX2

HDL Coding Style - 5 - 16 © 2002 Xilinx, Inc. All Rights Reserved

 Synopsys FPGA Compiler II
• Can be inferred: • Can be inferred using constraints table:
– Shift register LUT (SRL16 / – SelectI/O(single-ended)
SRLC16) – I/O Registers (Single Data Rate)
– F5, F6, F7, and F8 MUX – BUFGDLL*
• Cannot be inferred:
– Carry Logic
– Memories (RAM)
– MULT_AND – SelectI/O (differential)
– Memories (ROM) – I/O Registers (Double Data Rate)
– MULT18x18 / MULT18x18S – Global clock buffers (BUFGCE, BUFGMUX)
– Global clock buffers (BUFG) – DCM
– STARTUP_VIRTEX2

HDL Coding Style - 5 - 17 © 2002 Xilinx, Inc. All Rights Reserved

 Synplicity Synplify Pro 7.1
• Can be inferred: • Can be inferred using
– Shift register LUT (SRL16 / constraints editor or attributes:
SRLC16) – Memories (distributed ROM,
– F5, F6, F7, and F8 MUX some block RAM*)
– SelectI/O(single-ended)
– Carry Logic
– I/O Registers (Single Data Rate)
– MULT_AND – BUFGDLL**
– Memories (distributed RAM)
– MULT18x18 / MULT18x18S
– Global clock buffers (BUFG)

HDL Coding Style - 5 - 18 © 2002 Xilinx, Inc. All Rights Reserved

 Synplicity Synplify Pro 7.1
• Cannot be inferred:
– Memories (complex block RAM)
– SelectI/O (differential)
– I/O Registers (Double Data Rate)
– Global clock buffers (BUFGCE, BUFGMUX)
– DCM
– STARTUP_VIRTEX2

HDL Coding Style - 5 - 19 © 2002 Xilinx, Inc. All Rights Reserved

 Exemplar Leonardo
Spectrum 2002b
• Can be inferred: • Can be inferred using
– Shift register LUT (SRL16 / constraints editor or attributes:
SRLC16) – SelectI/O (single-ended)
– F5, F6, F7, and F8 MUX – I/O Registers (Single Data Rate)
– Carry Logic • Cannot be inferred
– Memories (complex block RAM)
– MULT_AND
– SelectI/O (differential)
– Memories (distributed ROM and – I/O Registers (Double Data Rate)
RAM, some block RAM*) – DCM
– MULT18x18 / MULT18x18S – STARTUP_VIRTEX2
– Global clock buffers (BUFG,
BUFGDLL**, BUFGCE,
BUFGMUX)

HDL Coding Style - 5 - 20 © 2002 Xilinx, Inc. All Rights Reserved

 XST 5.1i
• Can be inferred: • Can be inferred using
– Shift register LUT (SRL16 / constraints editor or attributes:
SRLC16) – SelectI/O
– F5, F6, F7, and F8 MUX – I/O Registers (Single Data Rate)
– Global clock buffers (BUFGCE,
– Carry Logic
BUFGMUX, BUFGDLL**)
MULT_AND
–
• Cannot be inferred:
– Memories (distributed ROM and – I/O Registers (Double Data Rate)
RAM, block RAM*) – DCM
– MULT18x18 / MULT18x18S – STARTUP_VIRTEX2
– Global clock buffers (BUFG)

HDL Coding Style - 5 - 21 © 2002 Xilinx, Inc. All Rights Reserved

 Suggested Instantiation
• Xilinx recommends that you instantiate the following elements:
– Memory resources
• Block RAMs specifically (use CORE Generator™ to build large memories)
– SelectI/O resources
– Clock management resources
• DCM (use the Architecture Wizard)
• IBUFG, BUFG, BUFGMUX, BUFGCE
– Startup block

HDL Coding Style - 5 - 22 © 2002 Xilinx, Inc. All Rights Reserved

 Suggested Instantiation
• Why do we suggest this?
– Easier to change (port) STARTUP Xilinx “wrapper” top_xlnx
to other and newer OBUF_GTL
technologies IBUFG DCM BUFG
Top-Level
Top-Level OBUF_GTL
– Fewer synthesis IBUF_SSTL2_I
Block
Block OBUF_GTL
constraints and
attributes to pass on
• Keeping most of the
attributes and
constraints in the Xilinx UCF file keeps it simple—one file contains critical
information
• Create a separate hierarchical block for instantiating these resources
– Above the top-level block, create a Xilinx “wrapper” with Xilinx specific
instantiations

HDL Coding Style - 5 - 23 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 24 © 2002 Xilinx, Inc. All Rights Reserved

 Review Questions
• What problem occurs with nested CASE and IF/THEN statements?

• Which encoding scheme is preferred for high-performance state

machines?

• Which Xilinx resources generally must be instantiated?

HDL Coding Style - 5 - 25 © 2002 Xilinx, Inc. All Rights Reserved

 Answers
• What problem occurs with nested CASE and IF/THEN statements?
– Nested CASE and IF/THEN statements may generate long delays due to
cascaded functions
• Which encoding scheme is preferred for high-performance state
machines?
– One-hot
• Which Xilinx resources generally must be instantiated?
– Double Data Rate I/O registers
– BUFGMUX
– BUFGCE
– DCM
– STARTUP_VIRTEX2

HDL Coding Style - 5 - 26 © 2002 Xilinx, Inc. All Rights Reserved

 Summary
• Your HDL coding style can affect synthesis results
• Infer functions whenever possible
• Most resources are inferable, either directly or with an attribute
• CASE and IF/THEN statements produce different types of
multiplexers
• Avoid nested CASE and IF/THEN statements
• Use one-hot encoding to improve design performance
• When coding a state machine, separate the next-state logic from
state machine output equations

HDL Coding Style - 5 - 27 © 2002 Xilinx, Inc. All Rights Reserved

 Where Can I Learn More?
• Synthesis & Simulation Design Guide:
[Link] > Software Manuals
• Handbooks: [Link] > Documentation > “Virtex-II
Handbook” or “Virtex-II Pro Handbook”
– Part 2: Virtex-II User Guide > Chapter 2: Design Considerations
• Using the DCM, memory, etc.
• Technical Tips: [Link] > Tech Tips
– Click Exemplar, Synopsys FPGA Compiler, or Synplicity
• Answers Database: [Link] > Troubleshoot
• Synthesis documentation or online help

HDL Coding Style - 5 - 28 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 29 © 2002 Xilinx, Inc. All Rights Reserved

 Shift Register LUT (SRL16)
Synopsys, Synplicity, Exemplar, and XST

• To infer the SRL, the primary characteristics the code must have are:
– No set/reset signal
– Serial-in, Serial-out
• SRLs can be initialized on power-up via an INIT attribute in the Xilinx
User Constraint File (UCF)

HDL Coding Style - 5 - 30 © 2002 Xilinx, Inc. All Rights Reserved

 SRL16E Example

VHDL: Verilog:
process(clk) always @ (posedge clk)
begin
begin
if (ce)
if rising_edge(clk) then sr <= {in, sr[0:14]};
if ce = ‘1’ then end
sr <= input & sr(0 to 14); assign out <= sr[15];
end if;
end if;
end process;
output <= sr(15);

HDL Coding Style - 5 - 31 © 2002 Xilinx, Inc. All Rights Reserved

 Dynamically Addressable SRL
Synopsys, Synplicity, Exemplar, and XST

• SRL16/SRL16E, and SRLC16/SRLC16E

– SRLC16 has two outputs in Virtex™-II, q15 - final output,
and q - dynamically addressable output

HDL Coding Style - 5 - 32 © 2002 Xilinx, Inc. All Rights Reserved

 SRLC16E Example
VHDL: Verilog:
process(clk) always @ (posedge clk)
begin
begin
if (ce)
if rising_edge(clk) then sr <= {in, sr[0:14]};
if CE = ‘1’ then end
sr <= input & sr(0 to 14); assign out <= sr[15];
end if; assign dynamic_out <= sr[addr];
end if;
end process;
output <= sr(15);
dynamic_out <= sr(addr);

HDL Coding Style - 5 - 33 © 2002 Xilinx, Inc. All Rights Reserved

 Virtex-II Multiplexers
Synopsys, Synplicity, Exemplar, and XST

• F5MUX, F6MUX, F7MUX, F8MUX data(7)

F6MUX
primitives data(6)
– Dedicated multiplexers in Virtex™-II CLB
– Only F5/F6 available in Virtex family data(5) muxout
– 4:1 multiplexer will use one slice data(4)
– 16:1 multiplexer will use 4 slices
(1 Virtex-II CLB) data(3)
– 32:1 multiplexer will use 8 slices data(2)
F5MUX

• No attribute needed -- inferred data(1)

automatically data(0)
LUT

HDL Coding Style - 5 - 34 © 2002 Xilinx, Inc. All Rights Reserved

 F5MUX and F6MUX Example
VHDL: Verilog:
process(sel, data) always @ (sel or data)
begin case(sel)
case (sel) is 3'b000: muxout = data[0];
3'b001: muxout = data[1];
when “000” => out <= data(0);
3'b010: muxout = data[2];
when “001” => out <= data(1);
3'b011: muxout = data[3];
when “010” => out <= data(2); 3'b100: muxout = data[4];
when “011” => out <= data(3); 3'b101: muxout = data[5];
when “100” => out <= data(4); 3'b110: muxout = data[6];
when “101” => out <= data(5); 3'b111: muxout = data[7];
when “110” => out <= data(6); default : muxout = 0;
when “111” => out <= data(7); endcase
when others => out <= ‘0’;
end case;
end process;

HDL Coding Style - 5 - 35 © 2002 Xilinx, Inc. All Rights Reserved

 Flip-flop Set/Reset Conditions
• When using asynchronous set and asynchronous reset,
reset has priority
• When using synchronous set and synchronous reset, reset
has priority
• When using any combination of asynchronous set/reset with
synchronous set/reset:
– Asynchronous set/reset has priority (furthermore, reset has highest
priority)
– In this mode, the synchronous set and/or reset is implemented in
the LUT
– The priority of the synchronous set versus synchronous reset is
defined by how the HDL is written

HDL Coding Style - 5 - 36 © 2002 Xilinx, Inc. All Rights Reserved

 Flip-Flop Example
VHDL: Verilog:
process(clk, reset, set) always @ (posedge clk or posedge
begin reset or posedge set)
if (reset = ‘1’) then q <= ‘0’; if (reset)
elsif (set = ‘1’) then q <= ‘1’; q = 0;
elsif rising_edge(clk) then else if (set)
if (sync_set = ‘1’) then q = 1;
q <= ‘1’; else if (sync_set)
elsif (sync_reset = ‘1’) then q = 1;
q <= ‘0’; else if (sync_reset)
elsif (ce = ‘1’) then q = 0;
q <= d; else if (ce)
end if; q = d;
end if; end
end process;

HDL Coding Style - 5 - 37 © 2002 Xilinx, Inc. All Rights Reserved

 Carry Logic
Synopsys, Synplicity, Exemplar, and XST

• Synthesis maps directly to the dedicated carry logic

• Access carry logic through adders, subtractors, counters,
comparators (>15 bits) and other arithmetic operations
– Adders / subtractors (SUM <= A + B)
– Comparators (if A < B then)
– Counters (COUNT <= COUNT + 1)
• Note: Carry logic will not be inferred if arithmetic components are
built with gates
– For example: XOR gates for addition and an AND gate for carry logic will
not infer carry logic

HDL Coding Style - 5 - 38 © 2002 Xilinx, Inc. All Rights Reserved

 Carry Logic Examples
VHDL: Verilog:
count <= count + 1 when assign count = addsub ? count + 1:
(addsub = ‘1’) else count - 1; count - 1;

if (a >= b) then if (a >= b)

a_greater_b <= ‘1’; a_greater_b = 1;

product <= constant * multiplicand; assign product = constant *

multiplicand;

HDL Coding Style - 5 - 39 © 2002 Xilinx, Inc. All Rights Reserved

 MULT18x18
Synopsys, Synplicity, Exemplar, and XST

• Synplicity and Exemplar infer MULT18x18 by default

– Synplify, to use MULT_18x18 set:
• syn_multstyle = block_mult (default)
– Possible values are “block_mult” and “logic”
– Exemplar, to use MULT_18x18 set:
• virtex2_multipliers = true (default)

HDL Coding Style - 5 - 40 © 2002 Xilinx, Inc. All Rights Reserved

 CLB MULT_AND
Synopsys, Synplicity, Exemplar, and XST

• Synplicity set: syn_multstyle = logic

• Exemplar set: virtex2_multipliers = false
• Synopsys will use MULT_AND by default

By+1 LUT
Ax-1
S LO
MUXCY_L
DI CI
By XORCY_L
Ax LI
LO
CI

MULT_AND

HDL Coding Style - 5 - 41 © 2002 Xilinx, Inc. All Rights Reserved

 Multiplier Example
VHDL: Verilog:
library ieee; always @ ( posedge clk or posedge
use ieee.std_logic_signed.all; reset)
use ieee.std_logic_unsigned.all; begin
… if (reset)
process (clk, reset) product <= 0;
begin else
if (reset = ‘1’) then product <= a * b;
product <= (others => ‘0’); end
elsif rising_edge(clk) then
product <= a * b;
end if;
end process;

HDL Coding Style - 5 - 42 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 43 © 2002 Xilinx, Inc. All Rights Reserved

 Block SelectRAM
Synplicity, Exemplar, and XST

• Synplicity: Set the syn_ramstyle attribute to “block_ram”

– Place the attribute on the output signal driven by the inferred RAM
– Requires synchronous write
– Requires registered read address
– Dual-port RAM inferred if read/write address index is different
• Exemplar: Automatically inferred under these conditions:
– Synchronous write
– Registered read address
• XST: Based on the size and characteristics of the code, XST can
automatically select the best style
– Available settings: Auto, Block, Distributed

HDL Coding Style - 5 - 44 © 2002 Xilinx, Inc. All Rights Reserved

 Block RAM Inference Notes
Synplicity, Exemplar, and XST

• Synthesis tools cannot infer:

– Dual-Port block RAMs with configurable aspect ratios
• Ports with different widths
– Block RAMs with enable or reset functionality
• Always enabled
• Output register cannot be reset
– Dual-Port block RAMs with read and write capability on both ports
• Block RAMs with read capability on one port and write on the other port can be
inferred
– Dual-Port functionality with different clocks on each port
• These limitations on inferring block RAMs can be overcome by
creating the RAM with the CORE Generator™ or instantiating
primitives

HDL Coding Style - 5 - 45 © 2002 Xilinx, Inc. All Rights Reserved

 Block RAM Example
VHDL: Verilog:
signal mem: mem_array; reg [31:0] mem[511:0] /*synthesis
attribute syn_ramstyle of mem: signal syn_ramstyle = “block_ram”*/;
is “block_ram”;
… always @ ( posedge clk)
process (clk) begin
begin addr_reg <= addr;
if rising_edge(clk) then if (we)
addr_reg <= addr; mem[addr] <= din;
if (we = ‘1’) then end
mem(addr) <= din;
end if; assign dout = mem[addr_reg];
end if;
end process;
dout <= mem(addr);

HDL Coding Style - 5 - 46 © 2002 Xilinx, Inc. All Rights Reserved

 Distributed SelectRAM
Synplicity, Exemplar, and XST

• Each LUT can implement a 16x1-bit synchronous RAM

• Automatic inference when code is written with two requirements:
– Write must be synchronous
– Read must be asynchronous
• However, if the read address is registered, the SelectRAM can be inferred
and will be driven by a register
– Synplicity: Automatically used -- turn off by setting attribute:
• syn_ramstyle = registers or block_ram
– Exemplar: Automatically used if RAM is less than eight bits wide
• Or set block_ram = false on RAM output signal
– XST: Specify block or distributed RAM, or let XST automatically select the
best implementation style

HDL Coding Style - 5 - 47 © 2002 Xilinx, Inc. All Rights Reserved

 Distributed RAM Example
VHDL: Verilog:
signal mem: mem_array; reg [7:0] mem[31:0];
…
process (clk) always @ ( posedge clk)
begin begin
if rising_edge(clk) then if (we)
if (we = ‘1’) then mem[addr] <= din;
mem(addr) <= din; end
end if;
end if; assign dout = mem[addr];
end process;
dout <= mem(addr);

HDL Coding Style - 5 - 48 © 2002 Xilinx, Inc. All Rights Reserved

 ROM
Synopsys, Synplicity, Exemplar, and XST

• Synplicity: infer ROM primitives with an attribute

– Set syn_romstyle = select_rom
– Otherwise, Synplify will infer a LUT primitive with equations
• Same implementation, except it is not a ROM primitive
• Exemplar, Synopsys, and XST will automatically map to
ROM primitives

HDL Coding Style - 5 - 49 © 2002 Xilinx, Inc. All Rights Reserved

 Distributed ROM Example
VHDL: Verilog:
type rom_type is array(7 downto 0) of reg [1:0] rom_dout /*synthesis
std_logic_vector(1 downto 0); syn_romstyle = “select_rom”*/;
constant rom_table: rom_type :=
(“10”, “00”, “11”, “01”, “11”, “10”, always @ ( addr)
“01”, “00”); case (addr)
attribute syn_romstyle: string; 3’b000: rom_dout <= 2’b00;
attribute syn_romstyle of rom_table: 3’b001: rom_dout <= 2’b01;
signal is “select_rom”; 3’b010: rom_dout <= 2’b10;
… 3’b011: rom_dout <= 2’b11;
rom_dout <= rom_table(addr); 3’b100: rom_dout <= 2’b01;
3’b101: rom_dout <= 2’b11;
3’b110: rom_dout <= 2’b00;
3’b111: rom_dout <= 2’b10;
endcase

HDL Coding Style - 5 - 50 © 2002 Xilinx, Inc. All Rights Reserved

 Outline
• Introduction
• Coding Tips
• Instantiating Resources
• Summary
• Appendix:
– Inferring Logic and Flip-flop Resources
– Inferring Memory
– Inferring I/Os and Global Resources

HDL Coding Style - 5 - 51 © 2002 Xilinx, Inc. All Rights Reserved

 SelectI/O
Synopsys, Synplicity, and Exemplar

• Instantiate in HDL code (required for differential I/O)

– For a complete list of buffers, see the following elements in
the “Libraries Guide”:
• IBUF_selectIO, IBUFDS
• IBUFG_selectIO, IBUFGDS
• IOBUF_selectIO
• OBUF_selectIO, OBUFT_selectIO, OBUFDS, OBUFTDS
• Use attribute (Synplicity, Exemplar)
• Specify in the UCF file
• Use Xilinx Constraints Editor
– In the Ports tab, check the I/O Configuration Options box

HDL Coding Style - 5 - 52 © 2002 Xilinx, Inc. All Rights Reserved

 SelectI/O
• Synopsys: Ports tab of FPGA Compiler II constraints editor
• Synplicity: Use xc_padtype attribute
• Exemplar: Use buffer_sig attribute
• XST: Instantiate or use Xilinx Constraints Editor

HDL Coding Style - 5 - 53 © 2002 Xilinx, Inc. All Rights Reserved

 SelectI/O Example
VHDL: Verilog:
component IBUF_HSTL_III /* For primitive instantiations in
Verilog you must use UPPERCASE
port (I: in std_logic;
for the primitive name and port
O: out std_logic); names */
end component;
... IBUF_HSTL_III ibuf_data_in_inst
ibuf_data_in_inst: IBUF_HSTL_III (.I(data_in), .O(data_in_i));
port map (I => data_in, O =>
data_in_i);

HDL Coding Style - 5 - 54 © 2002 Xilinx, Inc. All Rights Reserved

 IOB Registers
Synopsys, Synplicity, Exemplar, and XST

• For Single Data Rate I/O registers:

– Set Map Process Properties > Pack I/O Registers/Latches into IOBs
– Use the IOB = TRUE attribute in the UCF file
• Use on instantiated FFs or inferred FFs with known instance name
• Example: INST <FF_instance_name> IOB = TRUE;
– Synopsys: Ports tab in FPGA Compiler II constraints editor
– Synplicity: Automatically packs registers in the IOB, based on timing
• To override default behavior, use the syn_useioff attribute
– Exemplar: virtex_map_iob_registers = TRUE
– XST: Automatically packs registers in the IOB, based on timing
• To override default behavior under Synthesize > Properties > Xilinx Specific
Options tab > Pack I/O Registers into IOBs > Auto, Yes, or No

HDL Coding Style - 5 - 55 © 2002 Xilinx, Inc. All Rights Reserved

 IOB Registers
Synopsys, Synplicity, Exemplar, and XST

• Double Data Rate registers must be instantiated

– See the following elements in the “Libraries Guide”:
• IFDDRCPE, IFDDRRSE (for input flip-flops)
• OFDDRCPE, OFDDRRSE (for output or 3-state enable flip-flops)
• OFDDRTCPE, OFDDRTRSE (for output flip-flops)

HDL Coding Style - 5 - 56 © 2002 Xilinx, Inc. All Rights Reserved

 IOB Registers
• Limitations:
– All flip-flops that are packed into the same IOB must share the same clock
and reset signal
• They can have independent clock enables
– Output and 3-state enable registers must have a fanout of one
• Synopsys and Synplicity will automatically replicate 3-state enable registers to
enable packing into IOBs
• Exemplar can replicate 3-state enable registers for packing into IOBs by setting
virtex_map_iob_registers = TRUE
– Output 3-state enables must be active-low
• There is logic in the IOB to invert 3-state enable signal before the register
– DDR registers must use clk and not clk with 50 percent duty-cycle or DLL
outputs clk0 and clk180

HDL Coding Style - 5 - 57 © 2002 Xilinx, Inc. All Rights Reserved

 I/O Register Example
VHDL: Verilog:
process(clk, reset) always @ (posedge clk or posedge reset)
begin if (reset)
if (reset = ‘1’) then begin
data_in_i <= 0;
data_in_i <= ‘0’;
data_out <= 0;
data_out <= ‘0’;
out_en <= 1;
out_en <= ‘1’; end
elsif rising_edge(clk) then else
data_in_i <= data_in; begin
out_en <= out_en_i; data_in_i <= data_in;
if (out_en = ‘0’) then out_en <= out_en_i;
data_out <= data_out_i; if (~out_en)
end if; data_out <= data_out_i;
end if; end
end process;

HDL Coding Style - 5 - 58 © 2002 Xilinx, Inc. All Rights Reserved

 Global Buffers
• BUFG
– All synthesis tools will infer on input signals that drive the clock pin of any
synchronous element
• BUFGDLL
– Synopsys: Specify in the Ports tab of FPGA Compiler II constraints editor
– Synplicity: Can be inferred through synthesis by setting attribute
xc_clockbuftype = BUFGDLL
– Exemplar: Can be inferred through synthesis by setting attribute PAD =
BUFGDLL or BUFGDLLHF
– XST: Must instantiate
• BUFGCE
– Exemplar: Can be inferred by setting virtex2_clock_mux = TRUE

HDL Coding Style - 5 - 59 © 2002 Xilinx, Inc. All Rights Reserved

 DCM
• Digital Clock Manager
– Clock de-skew
– Frequency synthesis
– Phase shifting
• Must be instantiated
– Port names are as shown in diagram

HDL Coding Style - 5 - 60 © 2002 Xilinx, Inc. All Rights Reserved

 STARTUP_VIRTEX2
• Provides three functions
– Global set/reset (GSR)
– Global Three-State for output pins (GTS)
– User-defined configuration clock to synchronize configuration startup
sequence
• Must be instantiated
– Port names are GSR, GTS, and CLK
• Note: Using GSR is not recommended for Virtex™-II designs
– Normal routing resources are faster and plentiful

HDL Coding Style - 5 - 61 © 2002 Xilinx, Inc. All Rights Reserved