Department of

Computer Science and Engineering

1151CS108 –OPERTATING SYSTEMS

Unit IV

School of Computing
Vel Tech Rangarajan Dr. Sagunthala R&D Institute of
Science and Technology
 UNIT IV STORAGE MANAGEMENT

12/12/2025 2
 Course Content

UNIT IV STORAGE MANAGEMENT

 Main Memory: Swapping

 Contiguous Memory Allocation
 Segmentation
 Paging
 Virtual Memory: Demand Paging
 Page Replacement
 Allocation of Frames
 Thrashing.
 Case Study: Android operating system

12/12/2025 Department of Computer Science and Engineering 3

 Base and Limit Registers

• A pair of base and limit registers define the logical address space

• CPU must check every memory access generated in user mode to be sure
it is between base and limit for that user
Citations
Abraham Silberschatz,
Peter Baer Galvin and
Greg Gagne, “Operating
System Concepts”, 9th
Edition, John Wiley and
Sons Inc., 2012.

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4
Hardware Address Protection

Citations
Abraham Silberschatz,
Peter Baer Galvin and
Greg Gagne, “Operating
System Concepts”, 9th
Edition, John Wiley and
Sons Inc., 2012.

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 Address Binding

• Programs on disk, ready to be brought into memory to execute form an input

queue
• Without support, must be loaded into address 0000
• Inconvenient to have first user process physical address always at 0000
• How can it not be?
• Further, addresses represented in different ways at different stages of a
program’s life
• Source code addresses usually symbolic
• Compiled code addresses bind to relocatable addresses
• i.e. “14 bytes from beginning of this module”
• Linker or loader will bind relocatable addresses to absolute addresses
• i.e. 74014
• Each binding maps one address space to another

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Binding of Instructions and Data to Memory

• Address binding of instructions and data to memory addresses can happen at

three different stages

• Compile time: If memory location known a priori, absolute code can be

generated; must recompile code if starting location changes

• Load time: Must generate relocatable code if memory location is not

known at compile time

• Execution time: Binding delayed until run time if the process can be
moved during its execution from one memory segment to another

• Need hardware support for address maps (e.g., base and limit registers)

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Multistep Processing of a User Program

Citations
Abraham Silberschatz,
Peter Baer Galvin and
Greg Gagne, “Operating
System Concepts”, 9th
Edition, John Wiley and
Sons Inc., 2012.

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 Logical vs. Physical Address Space

• The concept of a logical address space that is bound to a separate physical

address space is central to proper memory management

• Logical address – generated by the CPU; also referred to as virtual address

• Physical address – address seen by the memory unit

• Logical and physical addresses are the same in compile-time and load-time
address-binding schemes; logical (virtual) and physical addresses differ in
execution-time address-binding scheme

• Logical address space is the set of all logical addresses generated by a program

• Physical address space is the set of all physical addresses generated by a

program
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 Memory-Management Unit (MMU)
• Hardware device that at run time maps virtual to physical address

• To start, consider simple scheme where the value in the relocation register is
added to every address generated by a user process at the time it is sent to
memory

• Base register now called relocation register

• MS-DOS on Intel 80x86 used 4 relocation registers

• The user program deals with logical addresses; it never sees the real physical
addresses
• Execution-time binding occurs when reference is made to location in
memory
• Logical address bound to physical addresses
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 Swapping

• A process can be swapped temporarily out of memory to a backing store,

and then brought back into memory for continued execution
• Total physical memory space of processes can exceed physical
memory

• Backing store – fast disk large enough to accommodate copies of all

memory images for all users; must provide direct access to these memory
images

• Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed

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 Swapping
• Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
• System maintains a ready queue of ready-to-run processes which have
memory images on disk.
• Does the swapped out process need to swap back in to same physical
addresses?
• Depends on address binding method
• Plus consider pending I/O to / from process memory space
• Modified versions of swapping are found on many systems (i.e., UNIX,
Linux, and Windows)
• Swapping normally disabled
• Started if more than threshold amount of memory allocated
• Disabled again once memory demand reduced below threshold

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Schematic View of Swapping

Citations
Abraham Silberschatz, Peter
Baer Galvin and Greg Gagne,
“Operating System Concepts”
9th Edition, John Wiley and
Sons Inc., 2012.

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Context Switch Time including Swapping

• If next processes to be put on CPU is not in memory, need to swap out a

process and swap in target process

• Context switch time can then be very high

• 100MB process swapping to hard disk with transfer rate of 50MB/sec

• Swap out time of 2000 ms
• Plus swap in of same sized process
• Total context switch swapping component time of 4000ms (4 seconds)
• Can reduce if reduce size of memory swapped – by knowing how much
memory really being used
• System calls to inform OS of memory use via request_memory() and
release_memory()
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Context Switch Time including Swapping

• Other constraints as well on swapping

• Pending I/O – can’t swap out as I/O would occur to wrong process

• Or always transfer I/O to kernel space, then to I/O device

• Known as double buffering, adds overhead

• Standard swapping not used in modern operating systems

• But modified version common

• Swap only when free memory extremely low

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 Swapping on Mobile Systems
• Not typically supported
• Flash memory based
• Small amount of space
• Limited number of write cycles
• Poor throughput between flash memory and CPU on mobile platform

• Instead use other methods to free memory if low

• iOS asks apps to voluntarily relinquish allocated memory
• Read-only data thrown out and reloaded from flash if needed
• Failure to free can result in termination
• Android terminates apps if low free memory, but first writes application
state to flash for fast restart

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 Contiguous Allocation

• Main memory must support both OS and user processes

• Limited resource, must allocate efficiently

• Contiguous allocation is one early method

• Main memory usually into two partitions:

• Resident operating system, usually held in low memory with interrupt

vector

• User processes then held in high memory

• Each process contained in single contiguous section of memory

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 Contiguous Allocation

• Relocation registers used to protect user processes from each other, and
from changing operating-system code and data

• Base register contains value of smallest physical address

• Limit register contains range of logical addresses – each logical address

must be less than the limit register

• MMU maps logical address dynamically

• Can then allow actions such as kernel code being transient and kernel
changing size

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Hardware Support for Relocation and Limit Registers

Citations
Abraham Silberschatz, Peter Baer Galvin
and Greg Gagne, “Operating System
Concepts” 9th Edition, John Wiley and Sons
Inc., 2012.
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 Segmentation
• Memory-management scheme that supports user view of memory
• A program is a collection of segments
• A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
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User’s View of a Program

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Logical View of Segmentation

4
1

3 2
4

user space physical memory space

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 Segmentation Architecture

• Logical address consists of a two tuple:

<segment-number, offset>,

• Segment table – maps two-dimensional physical addresses; each table entry

has:
• base – contains the starting physical address where the segments reside in
memory
• limit – specifies the length of the segment
• Segment-table base register (STBR) points to the segment table’s location in
memory
• Segment-table length register (STLR) indicates number of segments used by
a program;
segment number s is legal if s < STLR
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 Segmentation Architecture

• Protection

• With each entry in segment table associate:

• validation bit = 0  illegal segment

• read/write/execute privileges

• Protection bits associated with segments; code sharing occurs at segment level

• Since segments vary in length, memory allocation is a dynamic storage-

allocation problem

• A segmentation example is shown in the following diagram

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Segmentation Hardware

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 Paging
• Physical address space of a process can be noncontiguous; process is allocated
physical memory whenever the latter is available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load program
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have Internal fragmentation
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 Address Translation Scheme

• Address generated by CPU is divided into:

• Page number (p) – used as an index into a page table which

contains base address of each page in physical memory

• Page offset (d) – combined with base address to define the physical
memory address that is sent to the memory unit

page number page offset

p d
m -n n
• For given logical address space 2m and page size 2n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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Paging Example

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 Paging
• Calculating internal fragmentation
• Page size = 2,048 bytes
• Process size = 72,766 bytes
• 35 pages + 1,086 bytes
• Internal fragmentation of 2,048 - 1,086 = 962 bytes
• Worst case fragmentation = 1 frame – 1 byte
• On average fragmentation = 1 / 2 frame size
• So small frame sizes desirable?
• But each page table entry takes memory to track
• Page sizes growing over time
• Solaris supports two page sizes – 8 KB and 4 MB
• Process view and physical memory now very different
• By implementation process can only access its own memory
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 Free Frames

Before allocation After allocation

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 Implementation of Page Table

• Page table is kept in main memory

• Page-table base register (PTBR) points to the page table

• Page-table length register (PTLR) indicates size of the page table

• In this scheme every data/instruction access requires two memory

accesses

• One for the page table and one for the data / instruction

• The two memory access problem can be solved by the use of a special
fast-lookup hardware cache called associative memory or translation
look-aside buffers (TLBs)

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 Implementation of Page Table

• Some TLBs store address-space identifiers (ASIDs) in each TLB entry

– uniquely identifies each process to provide address-space protection for
that process

• Otherwise need to flush at every context switch

• TLBs typically small (64 to 1,024 entries)

• On a TLB miss, value is loaded into the TLB for faster access next time

• Replacement policies must be considered

• Some entries can be wired down for permanent fast access

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 Associative Memory
• Associative memory – parallel search

Page # Frame #

• Address translation (p, d)

• If p is in associative register, get frame # out
• Otherwise get frame # from page table in memory

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Paging Hardware With TLB

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 Effective Access Time
• Associative Lookup =  time unit
• Can be < 10% of memory access time
• Hit ratio = 
• Hit ratio – percentage of times that a page number is found in the associative
registers; ratio related to number of associative registers
• Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
• Effective Access Time (EAT)
EAT = (1 + )  + (2 + )(1 – )
=2+–
• Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
• EAT = 0.80 x 100 + 0.20 x 200 = 120ns
• Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search, 100ns for
memory access
• EAT = 0.99 x 100 + 0.01 x 200 = 101ns

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 Virtual memory

• Virtual memory – separation of user logical memory from physical

memory

• Only part of the program needs to be in memory for execution

• Logical address space can therefore be much larger than physical

address space

• Allows address spaces to be shared by several processes

• Allows for more efficient process creation

• More programs running concurrently

• Less I/O needed to load or swap processes

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 Virtual memory

• Virtual address space – logical view of how process is stored in memory

• Usually start at address 0, contiguous addresses until end of space

• Meanwhile, physical memory organized in page frames

• MMU must map logical to physical

• Virtual memory can be implemented via:

• Demand paging

• Demand segmentation

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 Demand Paging
• Could bring entire process into memory at
load time
• Or bring a page into memory only when it is
needed
• Less I/O needed, no unnecessary I/O
• Less memory needed
• Faster response
• More users
• Similar to paging system with swapping
(diagram on right)
• Page is needed  reference to it
• invalid reference  abort
• not-in-memory  bring to memory
• Lazy swapper – never swaps a page into
memory unless page will be needed
• Swapper that deals with pages is a pager
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 Basic Concepts
• With swapping, pager guesses which pages will be used before swapping out
again
• Instead, pager brings in only those pages into memory
• How to determine that set of pages?
• Need new MMU functionality to implement demand paging

• If pages needed are already memory resident

• No difference from non demand-paging

• If page needed and not memory resident

• Need to detect and load the page into memory from storage
• Without changing program behavior
• Without programmer needing to change code
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Page Table When Some Pages Are Not in Main Memory

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Steps in Handling a Page Fault

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 Aspects of Demand Paging
• Extreme case – start process with no pages in memory
OS sets instruction pointer to first instruction of process, non-memory-
resident -> page fault
• And for every other process pages on first access Pure demand paging
• Actually, a given instruction could access multiple pages -> multiple page
faults
• Consider fetch and decode of instruction which adds 2 numbers from
memory and stores result back to memory
• Pain decreased because of locality of reference
Hardware support needed for demand paging
• Page table with valid / invalid bit
• Secondary memory (swap device with swap space)
• Instruction restart
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 Page Replacement

• Prevent over-allocation of memory by modifying page-fault service

routine to include page replacement

• Use modify (dirty) bit to reduce overhead of page transfers – only

modified pages are written to disk

• Page replacement completes separation between logical memory and

physical memory – large virtual memory can be provided on a smaller
physical memory

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Need For Page Replacement

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Page and Frame Replacement Algorithms
• Frame-allocation algorithm determines
• How many frames to give each process
• Which frames to replace
• Page-replacement algorithm
• Want lowest page-fault rate on both first access and re-access
• Evaluate algorithm by running it on a particular string of memory
references (reference string) and computing the number of page faults on
that string
• String is just page numbers, not full addresses
• Repeated access to the same page does not cause a page fault
• Results depend on number of frames available
• In all our examples, the reference string of referenced page numbers is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1

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First-In-First-Out (FIFO) Algorithm

• Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1

• 3 frames (3 pages can be in memory at a time per process)

• Can vary by reference string: consider 1,2,3,4,1,2,5,1,2,3,4,5

• Adding more frames can cause more page faults!
• Belady’s Anomaly
• How to track ages of pages?
• Just use a FIFO queue
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 Optimal Algorithm
• Replace page that will not be used for longest period of time

• 9 is optimal for the example

• How do you know this?

• Can’t read the future

• Used for measuring how well your algorithm performs

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Least Recently Used (LRU) Algorithm
• Use past knowledge rather than future
• Replace page that has not been used in the most amount of time
• Associate time of last use with each page

• 12 faults – better than FIFO but worse than OPT

• Generally good algorithm and frequently used
• But how to implement?
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 Allocation of Frames
• Each process needs minimum number of frames

• Example: IBM 370 – 6 pages to handle SS MOVE instruction:

• instruction is 6 bytes, might span 2 pages

• 2 pages to handle from

• 2 pages to handle to

• Maximum of course is total frames in the system

• Two major allocation schemes

• fixed allocation

• priority allocation

• Many variations Department of Computer Science and Engineering

Fixed Allocation

• Equal allocation – For example, if there are 100 frames (after allocating
frames for the OS) and 5 processes, give each process 20 frames

• Keep some as free frame buffer pool

• Proportional allocation – Allocate according to the size of process

• Dynamic as degree of multiprogramming, process sizes change

si  size of process pi m = 64
S   si s1 = 10
s2 = 127
m  total number of frames
10
s a1 = ´ 62 » 4
ai  allocation for pi  i  m 137
S 127
a2 = ´ 62 » 57
137
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 Thrashing

• If a process does not have “enough” pages, the page-fault rate is very
high
• Page fault to get page
• Replace existing frame
• But quickly need replaced frame back
• This leads to:
• Low CPU utilization
• Operating system thinking that it needs to increase the degree of
multiprogramming
• Another process added to the system
Thrashing  a process is busy swapping pages in and out

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