EDK MEMORY MODEL SIMULATION
GUIDE
Version: 1.0
Date: 19 - Jan - 2016
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EDK MEMORY MODEL SIMULATION
Document Information
Author Vikas/Pruthvi
Reviewer Sudipto
Approver
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Change History
Version # Release Date Sections Author Change Description
Changed
1.0 19-Jan-2016 -- Vikas.B Initial Version
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EDK MEMORY MODEL SIMULATION
Table of Contents
1. Prerequisite.......................................................................... 4
1.1 System Requirements...........................................................................................4
1.2 Tools Used............................................................................................................ 4
2. EDK Memory Model Creation..................................................4
2.1 Description............................................................................................................ 4
3. Library Compilation...............................................................4
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3.1 Description............................................................................................................ 4
4. Generation of EDK Simulation Files........................................4
4.1 Description............................................................................................................ 4
5. Simulation of EDK Memory Model...........................................5
5.1 Description............................................................................................................ 5
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List of Figures
Figure 1: Xilinx Simulation Library Compilation wizard step 1……………………………………………6
Figure 2: Xilinx Simulation Library Compilation wizard step 2……………………………………………6
Figure 3: Xilinx Simulation Library Compilation wizard step 3……………………………………………7
Figure 4: Preferences settings in Xilinx XPS ………………………………………………………………...7
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1. Prerequisite
1.1 System Requirements
Microsoft Windows 7 with 4GB RAM
1.2 Tools Used
Xilinx ISE 14.7
Modelsim PE 6.4c
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2. EDK Memory Model Creation
2.1 Description
Take the existing mhs file (interface rtl/application rtl) and modify the mhs file such that it contains only
Clock and reset generation and corresponding ports, DDR2 memory ports and MPMC interface ports.
Take the existing xmp file (interface rtl/application rtl). In xmp file retain the LockAddr of MPMC and
remove the LockAddr of other interfaces and Processor interface (MicroBlaze or PowerPC). Set the
IntStyle to default.
Make sure that EDK project opens successfully in XPS.
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3. Library compilation
3.1 Description
Open compile simulation libraries under EDK folder -> tools.
Select Modelsim PE simulator.
Select 32 bit format.
Select suitable simulation executable location.
Refer to figure 1 and figure 2 for the above steps.
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Figure 1: Xilinx Simulation Library Compilation wizard step 1
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Figure 2: Xilinx Simulation Library Compilation wizard step 2
Select suitable FPGA device.
Let all the settings to default and generate the libraries. Refer to figure 3.
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Figure 3: Xilinx Simulation Library Compilation wizard step 3
4. Generation of EDK simulation Files
4.1 Description
Open the modified xmp file in Xilinx Platform Studio (ISE 14.7).
Go to Edit -> Preferences -> Simulation.
Select Modelsim Simulator.
Set appropriate Modelsim simulator path.
Set appropriate Xilinx compiled library path (explained as above). Click OK.
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Go to Simulation -> Generate Simulation HDL files.
Refer to figure 4 for preferences settings.
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Figure 4: Preferences settings in Xilinx XPS
5. Simulation of EDK Memory model
5.1 Description
Modify the test bench compilation do script to include the compilation of all the edk generated files and
ddr model.
Take all the vhdl files generated by xps in simulation/behavioral folder and compile them in test bench
compilation do file.
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Take the compilation do file generated by XPS from simulation\behavioral folder.
Comment the last 5 lines in compilation do file generated by xps. Integrate the same do file in
test bench compilation do file.
Take ddr2_model.v, ddr2_model_parameters.vh and wiredly.v from __xps\mig\platgen\mpmc_0\
example_design\sim and compile them.
Compile ddr2_model.v as below
vlog -quiet -novopt -incr -work work_tb +incdir+$INCLUDE_DIRECTORY_PATH +define+x8
$DIRECTORY_PATH/ddr2_model.v
Instantiate ddr2_model.v according to the on board DDR data width(based on DQ_BITS).
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Open Modelsim PE 6.4c.
Give the vsim command as below
vsim -GTESTCASE=$entry -t ps -onfinish stop -voptargs=+acc -L xilinxcorelib -L secureip
-L unisims_ver -L unisim work_tb.glbl work_tb.sx_sim_top
Make sure the libraries are mapped properly.
In the test case wait until the DDR initialization done is asserted high.
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