Process Flow for 22nm Planar:

Process Flow for 22nm

Planar Logic

© 2016 Threshold Systems Inc.

© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

Presented
by
Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 1

 Table of Contents:

22nm Planar Process Flow

1. 22nm Logic Fabrication Sequence ............................. page 3

2. Shallow Trench Isolation Module ............................... page 5
3. Well Module Definition ................................................. page 23
4. Device module Processing ........................................... page 33
5. The Contact Module ...................................................... page 79
6. Contact Module: Polished-back Contacts ................ page 85
7. Device Module Gate-Last ............................................. page 89
8. Back-end Metallization ................................................ page 103

© 2018 Threshold Systems Inc.

All rights are reserved. No part of this publication may not be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means , electronic, mechanical, photocopying,
recording or otherwise, without the prior written permission of Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 2

 Process Integration:

22nm Planar Logic

Fabrication Sequence

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© 2018 Threshold Systems Inc.

Presented
by
Jerry Healey

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 3

 Processing Modules:

The STI Module The Contact Module

© 2016 Threshold Systems Inc.

The Well Module © 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

Metallization

© 2016 Threshold Systems Inc.

The Device Module

© 2016 Threshold Systems Inc. © 2016 Threshold Systems Inc.

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 The STI Module:

Shallow Trench Isolation (STI):

Oxide
Ox

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 The Purpose of STI:

An Active Area A Shallow Trench

Shallow Trench Isolation consists of a series of trenches that are
etched into the silicon surface and which are filed with silicon
TEOS
TEOS TEOS TEOS TEOS
dioxide (SiO2) which is simply glass.
Epitaxial Silicon Glass (SiO2) is a superb electrical insulator and by surrounding the
P+ Silicon <100>

© 2016 Threshold Systems Inc.

active areas (where the transistors will reside) with glass-filled
trenches we can ensure that the transistor structures are electrically
isolated from each other.
Beginning at the 350 nm node STI replaced LOCOS as the isolation
technology of choice.

Shallow Trench
Isolation (STI)
A Transistor A Shallow Trench

TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>
P-Well

© 2016 Threshold Systems Inc.

© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 6
 Pad Oxide Growth:

The starting material for this type of process consists of <100> heavily doped
P+ Silicon with a typical resistively of 0.01 Ω-cm. The front-side of the wafers
are covered in a 2 µm thick layer of Epitaxial Silicon which has a resistively of
approximately 14 Ω-cm.

Epita
xial S

Source: Applied Materials

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© 2018 Threshold Systems Inc.
A “wet hood” that contains four cleaning stations.
Pad Oxide

The wafers are cleaned with Piranha + HF + SC1+ SC2 and 100Å of pad
oxide is grown across their surface.
The most common cleaning agents are:
Piranha - to remove organics
Epita
xial S
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ilicon SC1 - to remove particles

sI

P+ Sil
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Hydrofluoric acid (HF) to remove silicon dioxide

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 Nitride Barrier Deposition:

Next a 1,200 Å thick layer of Silicon Nitride is deposited via CVD.

The wafers are then cleaned in a Megasonic with SC1.

Silico
n Nitr
ide
Epita
xial S

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Pad Oxide
Silicon Nitride is generally a very tensile film relative to silicon. They have
differing coefficients of thermal expansion and contraction. For this reason
nitride is never deposited directly onto a silicon surface as this differential
Silicon Nitride
expansion and contraction could induce dislocation faults into the silicon
when the wafer is heated and cooled.
Epitaxial Silicon
As a consequence, when silicon nitride is to be deposited onto a silicon
P+ Silicon <100> surface, a thin layer of silicon dioxide, know as a “Pad Oxide”, is first grown
© 2016 Threshold Systems Inc.
on the silicon. The nitride is then deposited onto the Pad Oxide. The Pad
Oxide acts as a stress relief buffer between the silicon nitride and the
underlying silicon surface and prevents the silicon nitride from inducing
any damage into the silicon.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 8

 Hard Mask Deposition & Lithography:

BARC
2,000 Å thick layer of amorphous Carbon is deposited across the
wafers surface using CVD. This is followed by a 500Å layer of
Bottom Anti-Reflective Coating (BARC). The amorphous carbon
will act as a hard mask.
Photor
es ist Next, a ~3,000Å of photoresist is spun onto the wafers and soft
Amorp baked.
h ous Ca
rbon H
Silicon ard Ma
sk
Nitrid
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Epita
xial S

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100>

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UV Light UV Light
Quartz Glass The wafers are exposed to 193 nm UV light through a photomask
Photomask that is made of transparent quartz and patterned with chrome
that is opaque to UV light.
Chrome Chrome Chrome Chrome

Photoresist BARC

Amorphous Carbon Carbon Hard

Hard Mask Mask

Silicon Nitride

Epitaxial Silicon

P+ Silicon <100>
© 2016 Threshold Systems Inc.

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 Photolithography:

The Lithography tools that print microchip circuits are extremely sophisticated and Lithography Equipment
are the most precise instruments in the world. They are capable of printing images as
small as 20 nm and aligning to accuracies of less than 1 nm.
They are called “scanners” because the illuminating light scans across a chip printing
one microchip at a time. (They used to be called “steppers”.)
Photolithography scanners employ excimer laser light sources at wavelengths of
193nm and super-sophisticated optical optical pathways that terminate in a column
of precisely calibrated lenses.

© 2010 ASML
The lens column shrinks the precise patten on the reticle (mask) and prints it into the
photoresist located on the wafer’s surface.
Through the use of Resolution Enhancement Techniques (RET), Optical Proximity
Correction (OPC) and other optical processing, modern scanners are able to print
images smaller than the wavelength of the illumination light (193nm) being used.
A state-of-the-art scanners can cost as much as 70 million dollars and can process up
A 193i immersion scanner.
to 200-250 wafers per hour. A modern semiconductor fab may require 20-to-30
scanners.
All process flows at the 20nm node employ 193nm immersion scanners which are
denoted as “193i”.
© 2018 Threshold Systems Inc.
A Photomask A Lithography Lens

© Carl Zeiss
© Courtesy of Zeiss

The Lens column in a scanner.

In immersion lithography a tiny drop of water is

present between between the lens and the wafer.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 10

 Bottom Anti-Reflective Coatings (BARC ):

Without BARC UV Light With BARC

UV Light

Quartz Glass/Chrome Quartz Glass/Chrome

Photomask Photomask

Chrome Chrome

Photoresist The incident UV Light reflects Photoresist Anti-Reflective Coating (ARC);

off of the surface of the Carbon
no reflection occurs because the
Hard Mask, overexposing the
BARC causes destructive
Amorphous Carbon Hard Mask Photoresist in this area.
Amorphous Carbon Hard Mask interference between the incident
wave and the reflective wave.
Silicon Nitride Silicon Nitride

Photoresist Develop Photoresist Develop

Source: Dow Chemical Source: Dow Chemical

Photoresist No deformity occurs; the resist

The overexposed Photoresist in this
PR region develops away creating pattern is well-formed and an
deformed photoresist (PR). Such Amorphous Carbon Hard Mask accurate reproduction of the
deformity is highly undesirable because pattern that was on the photo-
Amorphous Carbon Hard Mask Amorphous Carbon Hard Mask
now the PR will not be able to accurately mask is replicated in the
shield the Carbon Hard Mask from the photoresist.
Silicon Nitride Silicon Nitride
upcoming etch. This will result in a
malformed Hard Mask and then a
Photoresist malformed pattern in the Nitride.

© 2016 Threshold Systems Inc. © 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 11
 Hard Mask Definition:

BARC
After patterning the wafers are soft-baked to give the resist a measure of
structural integrity and then the resist is exposed and developed. The
PR resulting photoresist pattern then undergoes a Post Exposure UV Bake
PR (PEB) to finalize the photoresist pattern and to turn the photoresist into a
PR cross-linked imidized mass that will resist etching.
Amorp PR
h ous Ca
rbon H
Silicon ard Ma
sk
Nitrid
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Epita
xial S

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© 2018 Threshold Systems Inc.

A highly anisotropic etch cuts down through the BARC and Hard Mask layers.
The photoresist is largely unaffected by the etch process and protect the
material beneath it.
PR
PR
PR
HM
PR
HM
HM
Silicon
Nitrid HM
e
16

Epita
20

xial S
ilicon
s©

P+ Sil
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 12

 Photoresist Strip & Trench Etch:

Patterned Carbon
Hard Mask

The photoresist and the BARC are removed leaving behind the patterned
amorphous carbon hard mask. The wafers are cleaned in Piranha to
remove any residual photoresist.

Silicon
Nitrid
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Epita
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ilicon

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Using the amorphous carbon layer as a hard mask, an anisotropic etch
Trench cuts down through the silicon nitride and the pad oxide and into the
silicon forming a shallow trench. Once the silicon surface is reached the
etcher pressure and gases are changed to make the etch process less
anisotropic. This results in trench side-walls that are sloped at an angle
Hard from 5 to 15 degrees.
Mask
Nitrid The amorphous carbon hard mask has a selectivity of 20:1. It is also
e
transparent to the 633 nm light used for alignment purposes, & therefore
does not interfere with this critical operation.
Epitax
ial
.

Silicon
nc

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 Trench Etch:
Wide Trench Narrow Trench

Silicon Nitride The amorphous carbon hard mask is selectively stripped away and the
Silicon Nitride
wafers are cleaned in Piranha.

Epitaxial Silicon
P+ Silicon <100>

© 2016 Threshold Systems Inc.

© 2007 Threshold Systems

© 2007 Threshold Systems

Nitride It is important to realize that not all trenches are of the same size. Since
Pad Oxide any region on the chip that is NOT an active area (I.e. a Well) will most
likely be Shallow Trench Isolation (STI), the size and shape of the trenches
Silicon will vary widely across the chip.

A wide Shallow Trench Narrow Shallow Trenches

© 2018 Threshold Systems Inc.
Trench Liner
The wafers are again cleaned (P/HF/SC1/SC2) and then a 100 Å thick layer
of silicon dioxide is grown in the trenches. This oxide layer is known as a
“trench liner” and is helps to relieve the stress in the silicon around the
upper and lower corners of the trench. The silicon nitride acts as a
diffusion barrier and prevents any silicon dioxide from growing beneath it.
Nitrid
e
Nitrid
e
Nitrid
e
Epitax Nitrid
ial e
Silicon
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 Trench Fill & Oxide Polish:

The surface of the oxide is then cleaned in P/SC1/SC2 and 4,000 Å of TEOS
(Tetra-Ethyl-Ortho-Silicate) oxide is deposited. TEOS is an oxide deposited
by CVD, as opposed to a grown (thermal) oxide. Its key advantage is that it
allows thick layers of oxide to be deposited quickly. It main disadvantage
is that a deposited TEOS oxide is not as dense as a grown oxide.
TEOS O
xide The wafers are then heated at 1,000 ˚C for 20 minutes to densify the TEOS
Nitrid
e and make it more resistant to wet etches.
Nitrid
e
Nitrid
e
Nitrid
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20 © 2018 Threshold Systems Inc.
©

Polished Nitride

The wafers are polished back using CMP. The very hard silicon nitride layer
acts as a CMP stop. After the polish step the wafers are cleaned in P/SC1.

After the oxide has been polished, the thin layer of nitride on the surface
Oxide that acted as a CMP stop must be removed.
Ox
Ox
Ox
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 15

 Chemical & Mechanical Polishing(CMP):

There are a number of operations throughout the semiconductor manufacturing process CMP Planarization
where the surface of the wafers needs to be smoothed or “planarized.”
Planarization is required because the many oxide and Copper deposition operations create
Rough, non-planar surface
a rough upper surface on the wafer which is referred to as “topographical variation”.
Because microchip manufacturing consists of depositing and patterning a series of
structures all stacked on top of each other (known as the “planar” process) it is important Oxide

© 2010 Threshold Systems

that each layer be polished after it is deposited so that its upper surface is smooth and flat.
Chemical Mechanical Planarization (CMP) smoothes out the rough topography of the as-
deposited oxide or Copper films by polishing away the film’s high spots and producing a
smooth planar surface.
CMP is used several times during the semiconductor manufacturing process and is a key
enabling technology without which advanced IC’s could not be produced. Cross-sectional close-up of a tiny portion of a microchip after
an oxide deposition. Note the undulating upper surface.

© 2018 Threshold Systems Inc. Smooth planar surface

Oxide

© 2010 Threshold Systems

The same cross-sectional close-up of microchip after it has
been polished by CMP. Note how smooth the upper surface
is after this polishing.

© 2010 Threshold Systems

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 16

 CMP Technology:
CMP Configuration
Wafer Carrier Spindle
CMP works by polishing the wafer in an abrasive liquid slurry while applying a small
Backing Film
downward force.
Wafer
Wafer Wafer Carrier Chuck
The wafer is loaded into a wafer carrier face-down. The wafer carrier is then pressed Polishing
Pads
against a rotating pad called a platen.
Both the platen and the wafer carrier rotate while a liquid abrasive known as a slurry
is dispensed onto the platen by a slurry applicator. Platen

© 2007 Threshold Systems

As the wafer rotates in the carrier its upper surface is slowly and carefully polished.
The wafer is placed face-down in the carrier
This results in a smooth, flat upper surface on the wafer. and pressed against the polishing pads
A device known as an end effector keeps the platen pad clean and maintains a
uniform pad surface. Slurry
Wafer
Applicator
After being polished the wafer is rinsed and cleaned to remove all of the slurry. Carrier

© 2018 Threshold Systems Inc. End Effector

© Applied Materials

The central components of a CMP System

Slurry Applicator Downward

Pad Force
Conditioner Slurry
Nozzles Wafer
Carrier

Polishing
Pad

Platen

© 2007 Threshold Systems

© 2007 Threshold Systems © 2007 Threshold Systems
The wafers are cleaned after being polished. A top-down view of the polishing table. A side of the polishing table.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 17

 Tiling Technique:
Method A Method B

1. TEOS Oxide 5.

Epitaxial Silicon

P+ Silicon <100>

© 2009 Threshold Systems © 2009 Threshold Systems

2.
© 2018 Threshold
6.
Systems Inc. No Dishing!
PR PR Photoresist PR

TEOS Oxide
Epitaxial Silicon

P+ Silicon <100>

© 2009 Threshold Systems

Epitaxial Silicon

P+ Silicon <100>

© 2009 Threshold Systems

3. Not all trenches are uniform in size. Some trenches are very large and this poses special
TEOS problems for CMP planarity. Illustration #1 displays a very large trench that creates a
large variation in the TEOS oxide density across the surface of the wafer. This is highly
undesirable for CMP.
TEOS Oxide
Epitaxial Silicon In order to avoid this problem the trenches and their adjacent area are patterned with
P+ Silicon <100> photoresist (figure #2) and the oxide over the active areas is etched away (figure #3).
This produces an oxide density that is somewhat more uniform and which should polish
© 2009 Threshold Systems more evenly. However the very large open trenches can still end up being somewhat
dished after the CMP operation is completed (figure #4).
Dishing!

4. An alternate approach is illustrated in Method B wherein “tiles” are designed into the
TEOS Oxide middle of the large open structures (figure #5). These tiles are dummy structures that
Epitaxial Silicon perform no function other than to present a uniform oxide surface to the CMP polish
platen. This eliminates the dishing effect (figure #6) and also eliminates the photo and
P+ Silicon <100>
etch operations employed in the method A.
© 2009 Threshold Systems

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 Nitride Strip:

Polished Nitride

After the oxide has been polished back the thin layer of nitride on the
surface that acted as a CMP stop must be removed.

Oxide
Ox
Ox

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P+ Sil

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Pad Oxide Trench Oxide

The residual silicon nitride is removed by immersing the wafers in hot (140 ºC)
Phosphoric acid for 20 minutes. The Phosphoric acid has a high selectivity to
nitride over oxide and will not attack the oxide.

Oxide
Ox
Ox
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nc

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P+ Sil
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100>
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 19

 Pad Oxide Strip & Sacrificial Gate Growth:

Bare Epitaxial Silicon

Next, the Pad Oxide is stripped by immersing the wafers in Hydrofluoric acid.

The Pad Oxide strip unintentionally removes oxide preferentially from the
trench corners because these areas are under stress and etch faster. This
results in the creation of “notches” along the sides of the trench that can
cause problems later in the process.
STI Notch
STI
STI

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STI

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P+ Sil

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100> STI

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Epitax

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© © 2018 Threshold Systems Inc.
Sacrificial Gate Oxide

The wafers are cleaned in P/SC1/SC2 and a 50 Å sacrificial gate oxide (Sac
Ox) is grown. The sacrificial gate oxide also acts as a screen oxide.

STI
STI
STI
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STI
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Sy

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 Notch Formation:

Notch Formation
Notch
TEOS TEOS
STI TEOS TEOS TEOS
STI TEOS
Notch

Epitaxial Silicon
> P+ Silicon <100> STI STI
STI
© 2016 Threshold Systems Inc.
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

Etch
The Pad Oxide strip unintentionally removes oxide preferentially from
the trench corners primarily because the STI oxide is a deposited oxide
which is much softer than the pad oxide which is a grown thermal oxide.
Etch In addition, the corner areas of the STI oxide are under mechanical
stress, and microstructures that under stress etch faster.
TEOS
STI TEOS
Finally, the sharp corners of the STI oxide are attacked from two sides
during the Pad Oxide etch process and this accelerates the retreat of
these corners.

This preferential etching results in the creation of “notches” along the

sides of the trench that can cause problems later in the process.

© 2016 Threshold Systems Inc.

>
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 22
 Well Module:

Well Definition Module:

STI
P-Well

ell
N-Well

W
P-
P-Well
N-Well

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 23

 The Well Module:

The Well Module:

An Active Area A Shallow Trench
A Well is a localized region of dopant that has been implanted into the silicon
surface in order to tailor its electrical characteristics and optimize transistor TEOS TEOS TEOS TEOS TEOS

performance. The Wells also augment the electrical isolation provided by the
Shallow Trench Isolation by establishing diode barriers between adjacent Epitaxial Silicon
P+ Silicon <100>
PMOS and NMOS devices.
In the well fabrication module the P-Wells and the N-Wells required for the A silicon wafer with STI
NMOS and PMOS transistors are realized using a series of masking and ion
implantation steps.

© 2018 Threshold Systems Inc.

P-Well N-Well A Shallow Trench

TEOS TEOS TEOS TEOS TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>

A silicon wafer with P and N wells

© 2016 Threshold Systems Inc.

P-Well

The P-Well

© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 24

 P-Well Implant:

The wafers are primed in HMDS and then coated with TARC (Top Anti-
Boron Implant Reflective Coating) and photoresist. The photoresist is soft baked to give
it a measure of structural integrity. After exposure and development the
photoresist has a pattern that covers the region where the N-Wells will
be located and which exposes the regions of the wafers where the P-
Wells are located.
TARC
Next, the wafers are implanted with a chain implant of Boron
that establishes the retrograde well P-Well (B, 5E13@200KeV, 7º),
a mid-well Field Channel Stop (B, 5E12@50KeV, 7º), and finally a
Threshold Voltage adjust (B, 5E11@5KeV 7º).

The P-Well established by the well implant is “Retrograde” in

Photor
e sist nature. This means that the highest concentration of dopant is
STI
P-Wel not located on the surface of the Well, but below the surface as
l STI
Epitax Photor
e ell indicated in the graph below. This arrangement permits high
ial ST sist P-W
Silicon I carrier mobility near the surface of the silicon where the

.
nc
P-Wel
transistor channel is located.

sI
l STI

m
P+ Sil

ste
icon <
100>

Sy
STI
ld
hos
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Th
16

Retrograde Well
20
©

© 2018 Threshold Systems Inc. Diffused Well

Dopant Concentration

© 2016 Threshold Systems Inc.

Retrograde Well

Depth
Wafer Surface

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 25

 Ion Implantation:

Ion Implantation is the process of accelerating atoms to a very high energy and then
Dopant atoms
implanting a very exact number of them into the surface of a silicon wafer at a precise
depth. These atoms are known as “dopant” atoms.
The kinds of atoms that are implanted are generally Boron, Phosphorous or Arsenic.
These atoms alter the electrical characteristics the silicon and create localized regions that
have specific electrical characteristics (like Sources, Drains or Wells) required to form
transistors and other electrical structures.
P-Well P-Well
The big advantage of doping with an implanter is that is provides enormous control over
the depth, quantity and purity of the dopant atoms that are implanted. Ion Implantation is the introduction of precise
Implants are specified by four parameters: Dopant species, dose, energy and implant quantities of atoms into the silicon surface at specific
depths. These dopant atoms, once activated, alter
angle. the electrical characteristics of the silicon.

© 2018 Threshold Systems Inc. Boron Boron Ions

The dopant species. In The implant angle (deviation

this case, Boron. from vertical). In this case zero
degrees. PR Photoresist Photoresist
B, 3E15@ 50KeV, 0 º
TEOS TEOS TEOS TEOS TEOS
P-Well

P-Well P-Well
The dose of the implant, expressed The implant energy expressed in Epitaxial Silicon
in “ions/cm2”. In this case 3 x 1015 Kilo-electron Volts (KeV). This P+ Silicon <100>
ions/cm2. determines how deep the ions are
implanted. The location of where the dopant atoms are placed
into the silicon can be controlled by using
photoresist. Those areas covered by the photoresist
are shielded from the implant. Exposed regions
receive the full dose of the implant.

© 2010 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 26

 Ion Implantation:

Ion Implanters
Ion Implanters are a special kind of particle accelerator and operate in a similar
fashion to standard particle accelerators.
The dopant species to be implanted is first converted into a gas and then ionized so
that it has a charge and can be accelerated to a precise energy in an electric field.
The accelerated dopant ions are then filtered in a mass spectrum analyzer that
removes any contaminant gas atoms.
The ion beam is then steered by powerful magnets and directed toward the wafer
where is rastered across the wafer’s surface to implant the dopant species.
The exact dose of the implant is determined by “counting” the dopant atoms by
precisely measuring the accumulated charge in the ion beam as it passes a specific
point in the implanter.
Source: Axcelis
After dopant atoms have been implanted it is necessary to “activate” them by
applying heat in order to move them onto substitutional sites in the silicon lattice
where they become electrically active. Ion Source
Magnetic
Extraction Electrode Quadrupole
Assembly Triple Index
Ion Implanters are by far the largest machines in the fab and they cost several Analyzer Magnets
Lens

million dollars. Magnetic Electron

Reflector

Electron shower

© 2018 Threshold Systems Inc. Post Accel Electrode

Flag Faraday

Disk
(X-Y mechanical scan)

Process Chamber
(two axis tilt capability)

A component of an ion Implanter displaying the Ion

source, analyzing magnet and associated components.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 27

 Photoresist Strip and N-Well Implant:

Sac Oxide

The photoresist from the previous operation is stripped in an ionized

oxygen plasma and the wafers are cleaned in Piranha.

The TEOS oxide in the STI trenches is now completely exposed as is the
STI Sacrificial Oxide (“Sac Ox”).
P-Wel
l STI
Epitax ell
ial ST -W
I P
Silicon
P-Wel STI
P+ Sil l

.
nc
icon <

sI
100>

m
STI

ste
Sy
ld
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16
20
© © 2018 Threshold Systems Inc.
Phosphorous + Arsenic

TARC The wafers are primed in HMDS and then coated with TARC, and the photoresist
is soft baked to give it a measure of structural integrity. After exposure,
development, and hard-bake, the photoresist has a pattern that covers the
I region where the P-Wells are located and which exposes the N-Well regions.
ST
The wafers then receive a chained implant of Phosphorus and Arsenic that
STI Photor
implants the retrograde N-well (P, 5E13 @400KeV, 0º), a mid-well Field Channel
P-Wel e sist Stop (P, 5E12@100KeV, 0º) the Threshold Voltage adjust (As, 5E11@5KeV, 0º).
l STI ell
N-We W
ll STI P-
P-Wel
.

l
nc

STI
sI

P+ Sil
m

icon < N-We

ste

100> ll STI
Sy
ld
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s
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Th
16
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©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 28

 High Vt N-Well Vt Adjust:
Arsenic

TARC
The photoresist from the previous operation is stripped in an ionized
oxygen plasma and the wafers are cleaned in Piranha.

I The wafers are primed with HMDS, coated in photoresist and TARC, and
ST
Photor then patterned. After patterning that portion of the active area that is
esist
designated to be the High Vt N-Well processing section is exposed, while all
STI other regions are covered with photoresist.
P-Wel
l STI Photor
esist ell
N-We -W The High Voltage N-Wells receive an implant of As,3E11@5KeV, 0º to give
ll STI P
P-Wel
l
them a higher Threshold Voltage (Vt) than the Low Voltage N-Wells.
STI

.
nc
P+ Sil
icon < N-We

sI
100> ll

m
STI

ste
Sy
ld
ho
High Vt N-Well

s
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16
20
© 2018 Threshold Systems Inc.
©

Low Vt N-Well

Sac Oxide

The photoresist from the previous operation is stripped and the

STI wafers are cleaned in Piranha to remove any residual photoresist.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
.

l
nc

STI
sI

P+ Sil
m

icon < N-We

ste

100> ll STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 29

 High Vt P-Well Vt Adjust & Well Anneal:
Boron
TARC
The wafers are primed with HMDS, coated in photoresist and TARC, soft
baked and then patterned. After patterning that portion of the active area
that is designated to be the High Vt P-Well processing section is exposed,
while all other regions are covered with photoresist.
I
ST
The High Vt P-Wells receive an implant of B, 3E11@5KeV, 0º to give them a
higher Threshold Voltage (Vt) than the Low Voltage P-Wells.
STI
P-Wel Photor
e
l STI sist ell
N-We -W
ll STI P
P-Wel

.
P+ Sil l

nc
icon < STI

sI
100>

m
N-We

ste
ll STI

Sy
ld
High Vt P-Well

sho
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16
Low Vt P-Well

20
©
© 2018 Threshold Systems Inc.

The photoresist from the previous operation is stripped and the wafers
Sac Oxide are cleaned in Piranha.

Following the well implants, the wafers undergo a Rapid Thermal

Anneal (RTA) at 1,000 ºC for 10 seconds to activate the implanted
I dopants in the wells.
ST

The anneal makes the dopant atom electrically active and anneals out
STI the damage done to the silicon during the implants.
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
.

l
nc

STI
sI

P+ Sil
m

icon < N-We

ste

100> ll STI
Sy
ld
hos
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 30

 Rapid Thermal Processing (RTP):
Rapid Thermal Processing is a key enabling technology that is required in order to make Ion Implantation work.
It is not enough to simply implant dopant atoms into a silicon wafer. The dopant atoms must be “activated”.
Activation is the process of causing the dopant atoms to move onto substitutional sites in the silicon lattice and become electrically active, modifying the
Silicon’s electrical characteristics.
Activation requires that the wafers be heated to a high temperature, usually from 1,000 - 1,350 ºC.
However, it is extremely important that the activation process not involve a lot of heat or the heat energy will cause the dopant atoms to diffuse into undesired
regions of the wafer.
RTP solves this problem by raising the temperature to the activation point and then rapidly dropping it back down again. It does this so rapidly that the wafers
do not have time to heat up.
The RTP equipment consists of an array of high-intensity lamps that heat up very rapidly and impart a short, abrupt flash of thermal energy to the front side of
the wafer that does not involve a lot of heat.
© 2018 Threshold Systems Inc.

Front of Wafer

Back of Wafer

© Applied Materials

© Ultra-Tech
RTP abruptly raises the temperature of the front
side of the wafer for a fraction of a second
without adding a lot of heat.
Traditional RTP chambers consist of a series of very
Unlike traditional RTP tools, Laser annealing
bright lamps that raise the temperature of the wafer’s
tools activate the implanted dopant while
surface for a brief instant.
providing virtually zero heat. This is a more
sophisticated approach to annealing.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 31

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 32
 Device Module Gate Last:

Device Module Processing

TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 33

 The Gate Module:

The Gate Module:

P-Well N-Well A Shallow Trench

In the Gate Module the transistor structures are fabricated. They TEOS TEOS TEOS TEOS TEOS

consist of the Source and Drains, the Halo and Extension implants, P-Well N-Well P-Well N-Well

the Nitride Spacers and the all-important Gate Electrode and gate Epitaxial Silicon
P+ Silicon <100>
dielectric.
A silicon wafer with P and N wells
The Gate Electrode initially consists of a strip of doped amorphous
silicon of precise dimensions. In the replacement gate methodology,
the amorphous silicon is merely a place-holder that is removed and
replaced with a complex series of metals.
Beneath the Gate Electrode is the transistor dielectric.

Gate Electrode

TEOS TEOS TEOS TEOS TEOS

The Gate P-Well N-Well P-Well N-Well

Electrode Epitaxial Silicon
P+ Silicon <100>

A silicon wafer with Gate electrodes formed over the P and N wells

© 2016 Threshold Systems Inc.

P-Well

© 2018 Threshold Systems Inc.

© Threshold Systems 2011

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 34

 Oxide ESL Growth & AmSi Deposition:

30 Å SiO2 ESL
Hi-K
TEOS TEOS TEOS TEOS TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon
© 2016 Threshold Systems<100>
Inc.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI A thin 30Å Etch Stop Layer (ESL) of SiON thermal layer oxide is grown across
P+ Sil

.
nc
icon < N-We the surface of the wafer. This oxide layer will act as an etch stop layer to

sI
100> ll STI

m
ste
protect the transistor channel when the amorphous silicon gate mandrel

Sy
(not yet deposited) is etched away.

ld
hos
re
Th
Note that there is no Hi-k dielectric deposited at this point in the process flow.

16
20
©
800 Å of Amorphous Silicon
© 2018 Threshold Systems Inc.
TiN

TEOS TEOS TEOS TEOS TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>

© 2016 Threshold Systems Inc.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI 800 Å of amorphous silicon (AmSi) is deposited using Chemical Vapor

Sy
ld

Deposition(CVD) technology. The amorphous Silicon is NOT doped.

ho
s
re
Th
16

After it has been patterned and etched the AmSi forms the sacrificial gate
20
©

mandrel.

Note that there is no metal gate beneath the amorphous silicon gate electrode.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 35

 Amorphous Silicon Dope & Hard Mask Dep:
Phosphorus

The amorphous silicon is implant doped with Phosphorus (5.0E15@ 5 KeV, 0º)
to make it conductive. The gate electrode is sacrificial and will be removed
later in the process. Doping the gate electrode aids in its removal but is not
necessary.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We

m
100> ll

ste
STI

Sy
ld
ho
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re
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16 © 2018 Threshold Systems Inc.
20
©

BARC

A 1,500 Å thick amorphous Carbon hard mask and a 300 Å thick BARC
layer are deposited.

Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

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100> ll
ste

STI
Sy
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ol
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16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 36

 Photoresist Deposition & 1st Patterning:

Next, the wafers are primed in HMDS, coated in BARC (Bottom Anti-
Reflective Coating), photoresist and patterned. This is the most critical
Photores lithography operation in the entire process flow. It generates a series of
ist
parallel lines that will be further defined by a cut mask in a following
lithography operation.
BARC
Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel

.
nc
l STI

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100> ll STI

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20
©
16
© 2018 Threshold Systems Inc.
Exposed Unexposed
Photoresist Photoresist
Next, the wafers are exposed using a grating mask. This mask prints
straight lines in one direction only.

The photoresist is not developed yet.

Photoresis
t
Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

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m

100> ll
ste

STI
Sy
d
ol
sh
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 37

 Cut Mask 2nd Patterning:
Second Mask
First Mask (Cut Mask) The photoresist is then exposed through a “cut mask” which exposes the
undeveloped photoresist in a direction perpendicular to the direction of
the first mask. This exposes the photoresist along this axis and allows the
continuous grating lines that run all across the chip to be cut.

Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel
l STI

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nc
P+ Sil

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100> ll

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STI

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ld
ho
© 2018 Threshold Systems Inc.

s
re
Th
16
20
©

Top-Down View of the Cut Mask Operation

Unexposed Exposed Exposed

Photoresist Photoresist Photoresist

Cut Mask

Y. Trouiller et al, Proc. (2007)

First Litho Pattern 2nd Exposure through Litho Pattern Hard Mask Etch Final Poly
the Cut Mask (Cut Mask)
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 38

 Photoresist Trim Process:

Patterned
Photoresist
The wafers are then loaded into an etcher and exposed to a controlled
oxygen plasma that isotropically etches the patterned photoresist. This
causes the photoresist to shrink in size to a targeted dimension.

This process is know as “photoresist trim”.

Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

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100> ll

ste
STI

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ho
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re
© 2018 Threshold Systems Inc.
Th
16
20
©

Trimmed
Photoresist
The trimmed photoresist lines are now narrower and can be used to
define smaller narrower gate electrodes.

Photoresist trim is a technique that allows the fabrication of very narrow

photoresist lines (and thus narrow gate electrode lines) that are smaller
that the photoresist lines that are optically printed.
Carbo
n Hard M
ask
STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

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sI

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100> ll
ste

STI
Sy
ld
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re
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16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 39

 Multiple Mask Patterning:

Double exposure is a sequence of two separate exposures of the same

photoresist layer using two different photomasks. This technique is
commonly used for patterns in the same layer which look very different or
have incompatible densities or pitches that cannot be successfully printed
with a single mask.
Litho-Etch-Litho-Etch (LELE) is the most basic style of double patterning,
where a pattern with unresolvable pitch is decomposed into two mask
layouts, each with resolvable features colored differently.
The green colored pattern to the left is the desired pattern created by the
chip designer. However the 193i Lithography tool is incapable of resolving
such a pattern which has lines that are so densely packed.
The pattern is split into two separate masks (the Red and the Blue masks).
The two fractured patterns are then overlaid to ensure that they will stitch
together. Next Optical Proximity (OPC) correction is performed on the
pattern and the physical masks are generated.
The patterns printed with mask one and mask two will appear on the wafer Source: ASML
after the LELE processing as indicated in the light blue patterns in the
diagram to the left. These two patterns are printed separately and overlaid
on the wafer to produce the final contour on the wafer.
Multiple patterning is necessary because we don’t have a lithography tool
© 2018 Threshold Systems Inc.
that is capable of resolving such fine patterns. It is also adds enormously to
the cost of new technology nodes. So much so that the 22/14nm nodes
have not presented any of the normal cost reductions associated with new
technology nodes.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 40

 Overlay Complexity:

The central issue with double and triple patterning is

overlay alignment. Aligning multiple patterns is complex,
difficult, time consuming and expensive. It doubles or
triples the lithography cycle time.
Because we cannot resolve the ultra-fine lines required to
pattern sub-20nm node devices, we break the mask
patterns up into two or sometimes three masks, print them
two or three times, and rely on overlay alignment to stitch
the patterns together to form the intended final pattern.
For example, in a traditional single exposure methodology,
a via and two associated metal lines aligned together
would require 3 overlay operations (refer to the diagram to
the right).
For a double patterning of the same structures, each of the
metal lines would be split into two different masks. This
would require eight separate overlay operations because
Source: ASML
the via would have to be aligned to the each metal line
twice and the metal lines would have to be aligned to each
other.
© 2018 Threshold Systems Inc.
Triple layer patterning (required at the 10nm node), where
the metal layers are split onto three masks and the vias
into two masks, would require 21 overlay alignments.
The 10nm node may require quadruple layer patterning
and the same example would require 40 overlay
operations. This would be a very expensive process,
perhaps prohibitively expensive.

Source: ASML

Double and triple layer patterning would not be necessary if EUV were available …

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 41

 Photoresist Trim:

Photoresist trimming is a “trick-of-the-trade” used by Etch Engineers to allow

them to etch polysilicon to dimensions that are smaller than the photoresist 1a. Before Trim
Resist Trim
lines printed on the wafer by the lithography process.
It works like this:
1b. After Trim
a) the photoresist lines are printed and developed (1a)
b) the developed photoresist lines are exposed to an oxygen plasma that 2. Advanced
Photolithographic
uniformly shrinks their length dimension (1b) Reduction
c) these new smaller photoresist lines are used to etch the polysilicon
This remarkable trick allows gate electrodes to be etched that are smaller
© 2016 Threshold Systems Inc.
than the smallest dimension that the lithography scanner is capable of
printing.
However, there is a limit to how far photoresist can be trimmed (a maximum
of ~ 30-40%). Beyond this point the photoresist simply becomes too tall and
looses its structural integrity. Trimmed
It is important to realize that although photoresist trimming reduces the Photoresist

dimension the resist lines, it does not increase their density. Increased density
and smaller photoresist lines can only be achieved through advanced Polysilicon
photolithographic reduction (refer to #2 above right).

© 2018 Threshold Systems Inc.

© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 42

 Photoresist Trim Process:

Step #6 After Trim Photoresist Measurement

Step #1 Feedback
Too narrow; strip resist and start again

Perfect! Send on to etch the Poly

© Fujitsu

© Fujitsu

© Fujitsu
Too wide; send

Number of Measured Sites

back for more
Step #4 Step #5
Etcher CD SEM Step #7 trim
CD SEM Etch the
Polysilicon
Amorphous Silicon Amorphous Silicon Amorphous Silicon

TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS

P-Well N-Well P-Well N-Well P-Well N-Well P-Well N-Well P-Well N-Well P-Well N-Well

Epitaxial Silicon Epitaxial Silicon Epitaxial Silicon

P+ Silicon <100> P+ Silicon <100> P+ Silicon <100>
Measure Resist Trim Measure

Photoresist
Step #2 Width
Desired Width
Feed-forward
© 2018 Threshold Systems Inc.
© 2016 Threshold Systems Inc. © 2016 Threshold Systems Inc.

Trimming photoresist is an iterative process that is performed on every wafer.

Step #3
After the resist has been printed and developed its width is measured in a SEM (step #1). This measurement information is feed-
forward to the etcher that is performing the resist trim (step #2).
Photoresist Trim Rate Chart
45 A photoresist trim etch rate look-up chart is consulted (step #3) to determine how long to trim the resist for to obtain the desired
40 dimension.
Amount of Trimmed PR (nm)

35 Trim Rate =
1.228 nm/sec The wafers on then sent on to have the photoresist trimmed in an etcher (step #4 ) and then the wafers are sent on so that the
30
resist after-trim dimension can be measured in a SEM (step #5).
25
20 This information is feedback to the etcher (step #6) and the etch time is adjusted to fine-tune the resist trim process. If the resist
15 is not small enough, the wafers are returned to the etcher to have their resist additionally trimmed.
10 If the resist is the correct dimension the wafers are sent on to have the polysilicon etched (Step #7). If too much resist has been
5 trimmed, then the entire photoresist pattern will be stripped and the entire photolithographic patterning and resist trim
process must be repeated.
0 5 10 15 20 25 30 35 40 45
Time (sec) This process is completely automated.

© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 43
 Hard Mask Etch & Photoresist Strip:

Hard Mask
The amorphous carbon hard mask is etched in a highly anisotropic etch process
that stops on the amorphous silicon.

STI Amorp
P-Wel hous S
i
l STI ell
N-We -W
ll STI P
P-Wel

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nc
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P+ Sil

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© 2018 Threshold Systems Inc.
20
©

Hard Mask

The photoresist is stripped and the wafers are cleaned in Piranha.

STI Amorp
P-Wel hous S
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l STI ell
N-We -W
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P-Wel
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.
nc

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STI
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©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 44

 Amorphous Silicon Etch & Hard Mask Strip:

A highly anisotropic etch recipe is then used to transfer the pattern from
the hard masks into the amorphous silicon.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

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icon < N-We

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100> ll

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STI

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© 2018 Threshold Systems Inc.
16
20
©

Amorphous
Silicon

The Hard Mask is stripped.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

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100> ll
ste

STI
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 45

 Poly Oxidation & Poly Stringers:

Poly Oxide

The wafers are cleaned in Piranha and 15Å of thermal poly oxide is grown.
This is followed by the deposition of 15Å of CVD oxide. These two oxide layers
form what is referred to as the “Offset Spacer” (sometimes also referred to as
“Spacer-Zero” or the “Spacer-1”). In previous generation of devices this oxide
was much thicker and referred to as “Poly Oxide”.
STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

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m
100> ll

ste
STI

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ld
hos
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© 2018 Threshold Systems Inc.
16
20
©

Poly Stringers
The original Pad Oxide strip (performed several operations ago after trench
fill and nitride removal) removes oxide preferentially from the trench corners
resulting in the creation of “notches” all along the sides of the trenches that
facilitate the formation of polysilicon stringers.
Notch The poly stringers form at the end of the polysilicon etch operation. The final
phase of this etch process is highly selective over-etch that is designed to
remove any small amounts of polysilicon remaining in the Source/Drain
regions and in the notches. If this phase of the etch is not carefully designed,
the thick polysilicon stringers will remain in the trench notches and will form
STI unintended conductive pathways that will short-out adjacent transistors.
STI
For this reason it is very important to minimize the size of the notches to
facilitate easy stringer removal.
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 46

 What Do These Structures Really Look Like?

© 2018 Threshold Systems Inc. Gate

Trench Oxide A
c
Gate
Active Region t
i
v
Gate Landing
Gate e

Gate

Gate Epitaxial Silicon

Bulk Silicon

© Threshold Systems 2006 © Threshold Systems 2006

An artificially colored section of a memory array An artificially colored section of a Logic chip displaying
displaying 3D angled views of real-world gate an angled view of the trench oxide, active areas and
electrodes running over active regions and trench gate electrodes. Note how the trench oxide is not
oxide. always at minimum dimension and that it assumes a
wide range of shapes and sizes.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 47

 NMOS Halo Implant:

Boron
TARC
The wafers are coated with photoresist and a Top Anti-Reflective Coating
(TARC) and then patterned. After patterning the photoresist covers all of
the active areas except the P-Wells.

A Halo implant of Boron (4.4E13@3KeV), at a tilt angle of 30 º, is applied

to the High Vt P-Well. This is a quad implant meaning that the wafers are
Photor implanted four times and rotated 90 º between implants. This ensures
e sist
that all sides of the gate electrode have a pocket of Boron implanted
STI
P-Wel Photor beneath the gate edge. The Halo implant is ~ 150 - 200 Å deep.
e sist
l STI ell Boron
N-We
ll STI
P-Wel
l STI
P-W
© 2018 Threshold Systems Inc.

.
nc
P+ Sil

sI
icon < N-We

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100> ll

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STI

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Photoresist

ld
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©
TEOS TEOS TEOS TE

Boron P-Well N-Well P-Well

Epitaxial Silicon
TARC P+ Silicon <100>

A view of the Boron Halo implant when the wafers have been rotated 180
degrees. This would be the third of the four implants that comprise the
quad Halo implant. The others being implanted when the wafer is at
angular positions of zero, 90 and 270 degrees.
Photor
e sist
STI
P-Wel Photor
l STI e sist ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
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100> ll
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 48

 NMOS Extension Implant:
Arsenic

Using the same photoresist pattern that was used for the Halo implant, an
Arsenic Extension implant (1E15@1 KeV, 0º ) is implanted into the P-Wels. This
implant establishes the Extension implants of the NMOS transistors.
TARC
The extension implants are at approximately the same depth as the Halo
implants (150-200 Å for a 20nm device).

Photor
e sist
STI
P-Wel Photor
l STI e sist ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil
© 2018 Threshold Systems Inc.

sI
icon < N-We

m
100> ll

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STI

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©

ArsenicArsenic

Photoresist The adjacent 2D image clearly displays the Extension implant. This implant is
self-aligned to the edge of the gate electrode and this high dose implant
overwhelms the Halo implant in the area where the two implants overlap.
However, the tip of the Halo implant is tucked under the gate electrode and the
TEOS TEOS TEOS TEOS electrode shields the tip of the Halo from the Extension implant in this location.
TEOS

P-Well N-Well P-Well N-Well The Extension implant determines the final L-effective (Leff) of the transistor
Epitaxial Silicon and has a huge effect on IdSAT.
P+ Silicon <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 49

 NMOS Anneal & PMOS Halo:

The photoresist from the previous operation is ashed away and the wafers
are cleaned in Piranha.

The wafers are then undergo a Rapid Thermal Process (~950 degree C
Spike for ~ 1 second followed by a ~1,350 degrees FLASH anneal for 1-3
milliseconds) that activates the NMOS Extension and Halo implants. In
some process flows the Flash anneal is replaced by a sub-melt Laser
STI anneal at the same temperature of ~1,350 degrees C. The location of the
ˆˆ P-Wel Extension implant fixes the final Leff of the NMOS transistors.
l STI ell
N-We -W
ll STI P
P-Wel The anneal makes the dopant atom electrically active and anneals out the
l STI

.
nc
P+ Sil damage done to the silicon during the implants.

sI
icon < N-We

m
100> ll STI

ste
Sy
ld
ho
s
re
Th
16
20
© 2018 Threshold Systems Inc.
©

Arsenic

TARC Next, the wafers are patterned with photoresist and coated with TARC. After
photoresist development only the N-Wells are exposed. A tilted 30 º Arsenic
Halo implant (2.2E13@20KeV) is applied to this well. It is a quad implant.

STI Photor
e sist
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 50

 PMOS Halo & Extension:
Arsenic
TARC

A view of the Arsenic Halo implant when the wafers have been rotated 180
degrees. This would be the third of the four implants that comprise the
quad Halo implant. The others being implanted when the wafer is at
angular positions of zero, 90 and 270 degrees.

Photor The Halo implant is ~ 150 - 200 Å deep for a 20nm node device.
STI e sist
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We

m
100> ll

ste
STI

Sy
ld
ho
s
re
© 2018 Threshold Systems Inc.
Th
16
20
©

Ge + B + C
TARC
A Pre-Amorphizing Implant (PAI) of Germanium (5E14@4KeV, 0º) is
applied to the N-Wells, and then a low energy Extension implant of (B,
8E14@300eV, 0º) is applied. This is followed by a Carbon implant of
5E14@3KeV which facilitates a superior Extension implant profile.

Photor
e
The PAI limits the channeling of the Boron atoms, while the Boron
sist
implant establishes the Extension implants of the PMOS transistors.
STI Photor
e sist
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 51

 PMOS Anneal:

The photoresist from the previous operation is ashed away and the wafers
are cleaned in Piranha.

The wafers are then undergo a Rapid Thermal Process (~950 degree C
Spike for ~ 1 second followed by a ~1,350 degrees FLASH anneal for 1-3
milliseconds) that activates the PMOS Extension and Halo implants. In
some process flows the Flash anneal is replaced by a sub-melt Laser
anneal at the same temperature of ~1,350 degrees C.
STI
P-Wel
l STI ell The location of the Extension implant fixes the final Leff of the PMOS
N-We -W
ll STI P transistors.
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We The anneal makes the dopant atom electrically active and anneals out the

m
100> ll STI

ste
damage done to the silicon during the implants and has a huge effect on

Sy
ld
ho
IdSAT.

s
re
Th
16
20
©
© 2018 Threshold Systems Inc.

Front of Wafer

Back of Wafer

RTP abruptly raises the temperature of the front

side of the wafer for a fraction of a second
without adding a lot of heat.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 52

 The Extension and the Halo Implants:

Along any PN junction there is always a “depletion region” which is a

Without a Halo Implant
zone that is depleted of charged carriers. All of the positive charges
along one side of the junction must be equal to all of the negative
charges on the opposite side of the junction so that charge neutrality is
Extension implant maintained.
(P-doped 1015 ions cm-2)
When the PN junction consist of an Extension implant that is heavily
Punch-through!
Depletion region doped (P-doped 1015 ions cm-2) and a N-Well that is lightly doped (N-
(Upper Boundary) doped 1012 ions cm-2) the depletion region will extend deeply into the
lightly doped N-Well so that enough charge in the N-Well can be
grabbed to neutralize all of the opposite polarity charge in the Extension
Large Depletion region implant.
TEOS
Depletion
Region
TEOS
(Lower Boundary)
When the gate electrode is extremely narrow, the lower boundaries of
the depletion regions from the Source and Drain of the transistor can
touch, resulting in a soft breakdown condition known as “Punch-
through”. When this happens the transistor will be in the ON state even
when it is supposed to be OFF.
N-Well N-Well
(N-doped 1012 ions cm-2)
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

By implanting a N-type Halo implant (N-doped 1013 ions cm-2) that is at
With a Halo Implant a higher dose than the N-Well, more charge is supplied on the Well side
of the PN junction to balance the opposite charge on the Extension side
of the PN junction. This means that the lower boundary of the depletion
Extension implant
region does not extend as deeply into the N-Well and the Punch-through
(P-doped 1015 ions cm-2)
condition is avoided.
Depletion region
The Halo implant extends only slightly beneath the edge of the gate
(Upper Boundary)
electrode and is not located in the vast majority of the channel region
beneath the gate electrode, so it does no lower carrier mobility.
Small
Depletion region
Depletion
TEOS
Region TEOS(Lower Boundary)

N-Well
Halo Implant
(N-doped 1013 ions cm-2)
N-Well
(N-doped 1012 ions cm-2)
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 53

 Nitride Spacer Deposition and Etch:

Silicon Nitride

A 150 Å thick blanket layer of silicon nitride is deposited over the surface of
the wafers. Because of the conformal nature of silicon nitride, it is thickest
along the side-walls of the gate electrodes.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We

m
100> ll

ste
STI

Sy
ld
ho
s
© 2018 Threshold Systems Inc.
re
Th
16
20
©

Silicon Nitride
Spacers
A highly anisotropic etch removes the silicon nitride from all of the horizontal
surfaces, and but leaves nitride side-wall spacers along the sides of the gate
electrodes where the nitride is thickest. The nitride side-wall spacers act as
mini-implant masks during the contact implants that come later in the
process.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 54

 Nitride Spacer Etch:

Etchant Ions Etchant Ions

TEOS TEOS
TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS TEOS Because the etch is highly anisotropic (etches in one direction only, i.e.
downward) the silicon nitride is cleared everywhere except the on the
P-Well N-Well N-Well P-Well P-Well N-Well N-Well P-Well N-Well sidewalls of the gate electrode because this is where the nitride is the
Epitaxial Silicon
thickest.
Epitaxial Silicon
P+ Silicon <100> P+ Silicon <100>
© 2016 Threshold Systems Inc. © 2016 Threshold Systems Inc. © 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

STI
ace rs
e Sp
STI Nitr
id
A highly anisotropic etch removes the silicon nitride from all of the horizontal
surfaces, and but leaves nitride side-wall spacers along the sides of the gate
ers
eS pac electrodes. The nitride side-wall spacers act as mini-implant masks during the
STI Nitrid
contact implants that come later in the process.
ers
eS pac
STI Nitrid

rs
Sp ace
ride
STI Nit

ell
P-W
STI
.
s Inc
ys tem
oldS
sh
hre
16T
[Link] 20 © 2018 by Threshold Systems Inc. All Rights Reserved. 55
©
 PMOS Hard Mask Deposition & Patterning:

SiCN Hard Mask

Next, 300Å of SiCN is deposited across the surface of the wafer.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We

m
100> ll

ste
STI

Sy
ld
ho
s
re
© 2018 Threshold Systems Inc.
Th
16
20
©

The SiCN is patterned with photoresist.

sist
h o tore
P
is t
tores
Pho

Photores
is t
STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 56

 PMOS Hard Mask Etch & Photoresist Strip:

The exposed SiCN is etched away in a highly anisotropic etch.

sist
tore
Pho
esist
h o tor
P

Photores
is t
STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI

.
nc
P+ Sil

sI
icon < N-We

m
100> ll

ste
STI

Sy
© 2018 Threshold Systems Inc.

ld
ho
s
re
Th
16
20
©

SiCN Hard Mask

The photoresist is stripped in an ionized oxygen plasma and the wafers

are cleaned in Piranha.

STI
P-Wel
l STI ell
N-We -W
ll STI P
P-Wel
l STI
.
nc

P+ Sil
sI

icon < N-We

m

100> ll
ste

STI
Sy
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 57

 PMOS Source/Drain Etch & SiGe Fill:

SiCN Hard Mask

The exposed Source/Drains of the PMOS transistor are wet etched away
using a NH4OH solution that etches along crystallographic planes. The P-
Wells and the gate electrodes are protected by the SiCN. The etch will not
attack the exposed oxide in the STI trenches.

STI
P-Wel
l STI ell
-W
N-We STI P Crystal Plane
ll P-Wel
l STI

.
nc
P+ Sil

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
TEOS TEOS TEOS TEOS TEOS

sho
re
Th
16
20
Etched out N-Well N-Well
P-Well P-Well
Source/Drains ©
Epitaxial Silicon
SiCN Hard Mask
P+ Silicon <100>
© 2016 Threshold Systems Inc.

The wafers then undergo a selective epitaxial deposition of SiGe. The SiGe
will only nucleate on an exposed silicon surface which means that it will
only form in the PMOS Source/Drain regions (every other part of the
STI wafer consists of nitride or oxide, or is covered in SiCN). The SiGe is ~ 40%
P-Wel Ge and it will exert a high level of compressive strain on the PMOS
l STI ell
P-W channel, greatly increasing the mobility of the holes in the channel and
N-We STI
ll P-Wel therefore increase Idsat.
l STI
.
nc

P+ Sil
sI

icon <
m

100> As the Epitaxial SiGe is deposited it is heavily doped with Boron to make it
ste

N-We STI
ll
Sy

P-Type silicon.
ld
hos
re
Th

© 2018 Threshold Systems Inc.

16

SiGe Fill
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 58

 Hard Mask Strip:

The remaining SiCN hard mask is etched away in an isotropic etch.

STI Halo & Extension

P-Wel SiGe Implants
l STI SiGe ell
-W
N-We STI P
ll P-Wel
l STI SiGe

.
SiGe SiGe

nc
TEOS
P+ S SiGTEOS TEOS TEOS SiGe SiGe TEOS

sI
ilicon e

m
<100

ste
> N-We STI

Sy
ll

ld
ho
P-Well N-Well P-Well N-Well

s
re
Th
16
Epitaxial Silicon

20
©
P+ Silicon <100>
© 2016 Threshold Systems Inc.

The adjacent image illustrates a close-up view of the SiGe replacement

Source Drains for the PMOS devices. Note that even though the Source/
Drains have been replaced the Extension and Halo implants are still
present.

© 2018 Threshold Systems Inc.

SiGe
SiGe

© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 59

 NMOS Hard Mask Deposition & Patterning:

SiCN Hard Mask

Next, 300Å of SiCN is deposited across the surface of the wafer.

STI
P-Wel SiGe
l STI SiGe ell
-W
N-We STI P
ll P-Wel
l STI SiGe

.
nc
P+ Sil SiGe

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
ho
s
re
Th
16
20
© 2018 Threshold Systems Inc.
©

The SiCN is patterned with photoresist.

Photoresis
STI t
P-Wel SiGe
l STI SiGe ell
-W
N-We STI P
ll P-Wel
l STI SiGe
.
nc

P+ Sil SiGe
sI

icon <
m

100>
ste

N-We STI
Sy

ll
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 60

 NMOS Hard Mask Etch + Source/Drain Etch:

SiCN Hard Mask

The photoresist is stripped.

STI
P-Wel SiGe
Crystal Plane
l STI SiGe ell
-W
N-We STI P
ll P-Wel
l STI SiGe

.
nc
P+ Sil SiGe

sI
icon < TEOS TEOS SiGe SiGe TEOS TEOS SiGe SiGe TEOS

m
100>

ste
N-We STI

Sy
ll

ld
hos
re
P-Well N-Well P-Well N-Well

Th
16
20
Epitaxial Silicon

©
P+ Silicon <100>
© 2016 Threshold Systems Inc.
SiCN Hard Mask

The oxide over the Source/Drains is etched away using a HF wet etch.

The exposed Source/Drains of the PMOS transistor are then wet etched
away using a NH4OH solution that etches along crystallographic planes.

STI
P-Wel
l
STI SiGe

N-We
SiGe

ll
STI P-
W
ell
© 2018 Threshold Systems Inc.
STI SiGe
.

P-Wel
nc

P+ Sil l SiGe
sI

icon <
m

100> STI
ste

N-We
Sy

ll
ld
ho
s
re
Th

Etched out
16
20

Source/Drains
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 61

 NMOS Source/Drain Selective SiC Dep:

SiCN Hard Mask

The wafers then undergo a selective epitaxial deposition of SiC. The SiC will
only nucleate on an exposed silicon surface which means that it will only
form in the PMOS Source/Drain regions (every other part of the wafer
consists of nitride or oxide, or is covered in SiCN).

The SiC exerts a very strong tensile strain on the NMOS channel and
enhances the mobility of electrons. This increases the Idsat of the NMOS
STI devices. As the SiC is deposited it is doped with Phosphorus to make it N-Type.
SiGe
P-Wel STI SiGe ell
l -W
N-We STI P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < Halo & Extension

m
100>

ste
N-We STI Implants

Sy
ll

ld
hos
re
Th
SiC Fill TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS

16
20
©
P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>
© 2016 Threshold Systems Inc.

The remaining SiCN hard mask is etched away in an isotropic etch.

STI SiC
SiC
P-Wel
l
STI SiGe

N-We
SiGe

ll
STI SiC
SiC P-W
ell © 2018 Threshold Systems Inc.
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100>
ste

N-We STI
Sy

ll
ld
hos
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 62

 Straining Silicon:
Appropriately straining the transistor channel dramatically
increase the transistor drive current, and with it, the transistor
speed.
The PMOS transistor channel must be placed under compressive
strain and the NMOS channel under tensile strain to achieve this S
Source Drain S
Source Drain
effect. T S T S
I T I T
Silicon I Silicon I
There are several approaches to inducing compressive or tensile Substrate Substrate
strain into a transistor channel, but the most effective way is to
replace the transistor source/Drains with a Silicon epitaxy that is
doped with atoms that have a larger or smaller lattice constant. NMOS Tensile Strain PMOS Compressive Strain
This induces compressive or tensile strain, respectively.
Source: Schubert Chu, Applied Materials 2013 Source: Schubert Chu, Applied Materials 2013

© 2018 Threshold Systems Inc.

Drive Current Vs. Node
1.5
> 60% Improvement 32nm
Strain
in Drive Current!
Hi-k/MG 45nm

IdSat (mA/µm)
1.0 Other
Classic Scaling 65nm

90nm
0.5
130nm

0.0
1,00 Gate Pitch (nm) 100
Source: Schubert Chu, Applied Materials 2013
After [Link] - Intel

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 63

 Straining the PMOS Transistor:

Source
S Drain
T S
I T
I
Silicon Subst
rate

Source: Schubert Chu, Applied Materials 2013 Source: Schubert Chu, Applied Materials 2013

The Source/Drains are selectively etched away and replaced with Silicon/Germanium. Germanium has a lattice constant
that is 4% larger than that of Silicon, and this larger lattice constant will ensure that the transistor channel is compressed,
enhancing the transistor drive current.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 64

 Optimizing PMOS Stress:
45nm PMOS

As previously mentioned, the amount of Ge in the PMOS SiGe Source/Drains is increased at each
new node to maintain the compressive stress on the transistor channel (currently 55% Ge at the
20nm node).
Another technique is to move the pointed edge of the SiGe crystal closer to the channel to
induce more stress. This was done at 32nm (refer to the accompanying TEMS).
The replacement gate also offers another method to increase PMOS strain. When the polysilicon
gate electrode is removed the spacers and associated structures move inward, compressing the
transistor channel and inducing compressive stress.

45nm PMOS Replacement Gate Stress Map

Source: C. Auth et al - Intel

At 32nm The foot of the SiGe was moved

closer to the channel to induce more stress.

32nm PMOS

Before Gate Removal

(ambient compressive stress)
Source: C. Auth et al - Intel

Source: P. Packan et al Intel

© 2018 Threshold Systems Inc.

After Gate Removal
(increased compressive stress)

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 65

 Straining the NMOS Transistor:

Straining the NMOS transistor with the replacement Source/Drain methodology

is considerable more problematic due to the difficulty in finding a material with a
smaller lattice constant than silicon that also has a high degree of stability. For Source Channel Drain
this reason NMOS tensile strain has typically been implemented using techniques
other than replacement Source/Drain.
However, recently a technology has been perfected that incorporates either
Phosphorus, or Carbon & Phosphorus, into a Silicon epitaxy. Because Carbon is
38% smaller than Silicon, Source/Drains that are replaced with this epitaxy pull
Tension
on either side of the channel and create a tensile strain on the channel. This is
Silicon P or C & P
precisely what is required to enhance the performance of the transistor (up to
20% more drive current). Carbon has a lattice constant 38% smaller than silicon
Either a Phosphorus or a Carbon/Phosphorus epitaxy can be used for this
purpose. Source: Schubert Chu, Applied Materials 2013

© 2018 Threshold Systems Inc. NMOS Strain Performance Enhancement

Source
S
T
I
S Drain
T
20%

Drive Current = Speed

Silicon

180 130 90 65 45 32 22
Node (nm)

Source: Schubert Chu, Applied Materials 2013 Source: Schubert Chu, Applied Materials 2013

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 66

 Mask-Edge Dislocation Stress (SMT):

A more specific name for Stress Memorization Technique (STM) on the NMOS device is a technique known as
“Edge Dislocation Stress”. This is a STM technique that generates a mask-edge dislocation inducing dramatic
tensile stress in the NMOS channel. It was first deployed at the 45/32nm nodes prior to the advent of P or P&C
replacement Source/Drain epitaxy for NMOS transistors.
The process involves a deep amorphization implant followed by the deposition of a stress over-liner of nitride.
Following a Rapid Thermal Anneal to induce SMT, the stress liner is removed and the mask-edge dislocations
are formed.
The initial pre-amorphization implant (PAI) for SMT creates multiple mask-edge dislocations under the
Source/Drain region which enhances short-channel mobility. Overall, a 10% increase in Idsat is achieved.
It is important to realize that different strain techniques are typically used together because their
contributions to increased performance is additive.

© 2018 Threshold Systems Inc. Source: K.Y. Kim et al - Samsung

Mask Edge Dislocation

Source: K.Y. Kim et al - Samsung

Source: C.E. Weber et al Intel

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 67

 Source /Drain Anneal:

The wafers are then undergo a Rapid Thermal Process (~950 degree C
Spike for ~ 1 second followed by a ~1,350 degrees FLASH anneal for
~1-3 milliseconds) that activates the PMOS and NMOS dopant atoms.

STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
ho
s
re
Th
16
20
©

© 2018 Threshold Systems Inc.

In some process flows the Flash anneal is

replaced by a sub-melt Laser anneal at the
same temperature of ~1,350 degrees C.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 68

 Physical Vapor Deposition (PVD):

In microelectronic fabrication it is often necessary to deposit thin films of ultra-pure metals or

metal alloys such as Nickel, Titanium, Titanium Nitride, Tantalum, Tantalum Nitride and
Copper.
This deposition process is accomplished using a technology known as Physical Vapor
Deposition (PVD).
This task is accomplished by sputtering metal atoms off of a metal target and allowing them
to be sprayed onto the wafer’s surface. The atoms of metal adhere on the surface and
eventually form a thin film that covers the entire surface of the wafer.
PVD is a valuable technology because it is capable of depositing thin layers of very pure
metals, or metal alloys, with good step coverage, in a very short time frame.

© 2018 Threshold Systems Inc. © Applied Materials

An opened PVD tool showing all of the chambers.

(-V)
The wafer is placed in an evacuated chamber Target (Ni)
on top of the anode and a small amount of
Argon gas is introduced into the chamber. A Cathode
plasma is struck and the Argon is ionized. The Plasma
positively charged Argon ions then bombard Ar+
the Cathode which consists of the target Ar+
material, and in so doing, sputter off metal
that is deposited onto the wafer. Sputtered Atom
This thin and very pure coating of metal is Wafer
rapidly deposited onto the wafer’s surface.
Anode

© Applied Materials
(+V)
An open degas chamber.

© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 69

 Nickel Salicidation Oxide Strip:

After the anneal the wafers still have a layer of poly oxide on the top of
the gate electrodes. There may also be a native oxide over the SiGe and
the SiC Source/Drain regions.

STI SiC Both of these oxides must be removed to expose a bare silicon surface
SiC
P-Wel STI SiGe
SiGe ell
for the salicidation process.
l SiC -W
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
hos
re
Th
16
20
© 2018 Threshold Systems Inc.
©

The wafers are then dipped in HF to remove all of the silicon dioxide
from tops of the gate electrodes and from the surfaces of the Source/
Drain regions. This operation prepares the wafers for the upcoming
salicidation step.

STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll
SiGe
.
nc

P-Wel STI
SiGe
sI

P+ Sil l
em

icon <
100>
st

N-We STI
Sy

ll
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 70

 Salicidation Implants:
Silicon

The wafers are implanted with a Silicon Pre-Amorphization Implant (PAI).

(1.0E15@5KeV, 0º) This amorphizes the surface of the silicon and
facilitates the formation of a more uniform, lower resistance silicide
(formed in the following operations).

STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll
© 2018 Threshold Systems Inc.

ld
ho
s
re
Th
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Aluminum

The wafers are patterned with photoresist that exposes only the P-Wells.
They are then implanted with Aluminum (~2E14@ 5KeV, 0º). The
aluminum is positioned so that it will be located at the interface between
the SiGe and the yet-to-be deposited Ni/Pt. This implant results in lower
contact resistance for the PMOS devices because the Aluminum
segregates to the top of the SiGe and being a P-Type dopant it lowers the
Schottky barrier height for holes from ~.4eV to ~.12eV and increases drive
current by up to 19%.
STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
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100>
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Sy

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ol
sh
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Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 71

 Nickel/Platinum/TiN Deposition:

The wafers are cleaned with P/SC1 and a blanket coating of ~125 Å
Nickel/Platinum and ~150 Å of TiN is deposited using Physical Vapor
Deposition. The TiN cap on top of the Nickel helps to prevent the Nickel
from diffusing away during the high-temperature salicidation process
and promotes more uniform NiSi formation. The 5-10% Platinum
Platinum helps to lower the barrier at the Ni-Si interface and establish a
STI SiC lower contact resistance. It also postpones the transformation of low
SiC
SiGe resistance NiSi into the higher resistance NiSi2.
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

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N-We STI

Sy
ll

© 2018 Threshold Systems Inc.

ld
hos
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Th
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20
©

TiN
Nickel/Platinum The adjacent 2D image illustrates the Nickel/Platinum/TiN stack after
initial deposition and prior to the anneal.

TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 72

 Salicidation Anneal:
Unreacted
Nickel Reacted
Nickel

The wafers undergo a RTA at ~250 º C for 30 seconds that converts the
nickel-Platinum into the high resistance C49 phase. A second RTA at
~390 º C for 30 seconds converts the on the wafer’s surface into the low
resistance (15 µΩ-cm) C54 NiSi phase.

NiSi is necessary because it consumes at least 30% less silicon than the
STI SiC same thickness of CoSi2. This is extremely important because the 20nm
SiC
SiGe node junctions are very shallow. In addition, NiSi has a very smooth
P-Wel STI SiGe ell
l SiC -W surface which minimizes junction leakage.
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
hos
re
© 2018 Threshold Systems Inc.
Th
16
20
©

Reacted
Nickel
Unreacted
Nickel
The adjacent 2D image illustrates the reacted and unreacted Nickel/
Platinum on the devices. In order to form a Nickel silicide, the Nickel/
TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS
Platinum layer must come into contact with an exposed Silicon surface.
The only place where exposed Silicon is located is on top of the gate
P-Well N-Well P-Well N-Well
electrodes or on the Source/Drain regions. The Nickel/Platinum on top
of the STI and on the Nitride spacers will remain unreacted.
Epitaxial Silicon
P+ Silicon <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 73

 Unreacted Nickel Strip:

Nickel Silicide

The unreacted nickel located on the spacer sidewalls and on top of the
STI is etched away with a solution of Piranha and SC1. This etch is highly
selective and leaves the reacted salicide on top of the gate electrodes
and over the Source/Drains untouched. This etch also removes the TiN
capping layer from all surfaces on the wafer.

SiC
SiC
SiGe
P-Wel STI SiGe ell
l SiC -W
N-We STI SiC P
ll

.
SiGe

nc
P-Wel STI

sI
P+ Sil l SiGe

m
icon <

ste
100>
N-We STI

Sy
ll

ld
ho
© 2018 Threshold Systems Inc.
s
re
Th
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©

Reacted
Nickel

The adjacent 2D image illustrates the fact that the Piranha solvent
TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS
readily attacked and removed the unreacted Nickel/Platinum from the
nitride spacer sidewalls and from the top of the STI.
P-Well N-Well P-Well N-Well
The Piranha does not attack the reacted NiSi over the Source/Drains or
Epitaxial Silicon on top of the Gate Electrodes.
P+ Silicon <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 74

Transistor Nomenclature:

© 2018 Threshold Systems Inc.

NMOS PMOS
AmSi Gate Electrode NiSi
NiSi Nitride Spacer
AmSi Gate
Electrode

Poly Oxide
NiSi
Extension Halo Implant
SiON Implant
SiON

TEOS SiC SiC TEOS SiGe SiGe TEOS SiC S

Halo
Extension
Implant
Extension Implant
Implant

P-Well N-Well P-Well

Epitaxial Silicon
© 2016 Threshold Systems Inc. P+ Silicon <100>

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 75

 Pre-Metal Dielectric (PMD):

Silicon Nitride
Oxide Layer
The wafers are cleaned in P/SC1 and thin 75 Å layer of silicon
dioxide followed by ~75Å of nitride is deposited. The oxide acts as a
diffusion barrier to external dopants that could contaminate the
device layer (the “active” Layer).

The silicon nitride will act as an etch-stop layer for the contact etch
STI SiC which will connect the transistor Source/Drains and gate electrodes
SiC
SiGe
P-Wel STI SiGe ell to the yet-to-be-formed Tungsten trenches.
l SiC -W
N-We STI SiC P
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI Nitride Etch Stop

Sy
ll

ld
Layer (ESL)

ho
s
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Th
16
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©

CH Chan et al, IEDM 2005 3.4

Next, 2,000 Å of a Phosphorus doped glass known as PSG (Phospho-

Silicate Glass) is deposited over the wafers using high density CVD. This
layer forms the Pre-Metal-Dielectric (PMD).

PSG
STI SiC

P-Wel
SiC

l
STI SiGe
SiGe
STI -W
ell
© 2018 Threshold Systems Inc.
SiC P
N-We SiC
ll
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100>
ste

N-We STI
Sy

ll
ld
ho
s
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Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 76

 Pre-Metal Dielectric Polish-Back:

PSG

A top-down view of the PSG layer prior or polishing. Note the humps in
the PSG caused by the underlying topography induced by the height of
the gate electrodes.

ms
In c. © 2018 Threshold Systems Inc.
te
Sys
sh old
hre
16T
20
©

The wafers are polished back using CMP to a thickness of ~1,200 Å.

PSG

STI SiC
SiC
STI SiGe
P-Wel SiGe ell
l STI SiC -W
N-We SiC P
ll STI SiGe
.
nc

P-Wel SiGe
sI

P+ Sil l
m

icon < STI

ste

100> N-We
Sy

ll
ld
hos
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16
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©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 77

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 78
 Contact Module:

The Contact Module

.
s Inc
ys tem
ld S
sho
hre
6T
201
©

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 79

 Hard Mask Patterning:

Photoresist

Next, the wafers are primed in HMDS, coated in photoresist and patterned.

The illustration to the left is a top-down view of the trench contact

photoresist pattern. Note the gate electrode contact trenches at the right of
the image.

This would be a double patterning operation.

c.
s In
em
yst
ld S
sho

©
20 1 6 Th
re
© 2018 Threshold Systems Inc.
Photoresist

The illustration to the left is a tilted front-end view of the trench contact
photoresist pattern. Note the gate electrode contact trenches at the back of
the image.

PSG

STI SiC
SiC
STI SiGe
P-Wel SiGe ell
l STI SiC -W
N-We SiC P
.

ll
nc

STI SiGe
sI

P-Wel
m

P+ Sil l SiGe
ste

icon <
STI
Sy

100>
N-We
ld

ll
hos
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 80

 Hard Mask Etch & Photoresist Strip:

The photoresist is ashed away leaving behind the patterned amorphous

carbon hard mask. The wafers are then cleaned in Piranha to remove any
sk residual photoresist.
d Ma
a r
nH
rbo
Ca PS
G
PSG
STI SiC
SiC
STI SiGe
P-Wel SiGe ell
l STI SiC -W
N-We SiC P
ll

.
nc
STI SiGe

sI
P+ Sil P-Wel

m
l SiGe
icon <

ste
100> STI

Sy
N-We

ld
ll

ho
s
© 2018 Threshold Systems Inc.
re
Th
16
20
©

Using the Amorphous Carbon Hard Mask as a pattern, a highly anisotropic

etch cuts down through the PSG to form the contact holes. The etch stops
on the Silicon Nitride located above the Source/Drains and on the top of
sk the gate electrode. The etch chemistry is then changed and the Silicon
d Ma
a r nitride and underlying oxide is etched away. The etch stops on the Nickel
nH silicide located over the Source/Drains and on top of the Gate Electrode.
rbo
Ca G
PS
STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l -W
N-We STI SiC P
ll SiC
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100>
ste

N-We STI
Sy

ll
ld
ho
s
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 81

 Hard Mask Strip & TiN Deposition:

The hardMask is etched away and the wafers are cleaned in Piranha.

G
PS
STI SiC
SiC
SiGe
P-Wel STI SiGe ell
l -W
N-We STI SiC P
ll SiC
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
ho
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Th
© 2018 Threshold Systems Inc.
16
20
©
Ti/TiN

The wafers are degassed and then exposed to a soft Argon sputter pre-
clean to remove any native oxides present on top of the NiSi at the
bottom of the contact holes.

G Next, ~60 Å of Titanium (a glue layer) is deposited by Ionized Metal

PS Plasma (IMP) PVD. This is followed by ~30 Å deposition of TiN (a barrier
STI SiC layer) deposited via IMP PVD. The TiN is re-puttered after deposition to
SiC
STI SiGe
ell
enhance sidewall coverage inside the contact.
P-Wel SiGe
W
l STI SiC P-
N-We
ll SiC
STI
The wafers are then heated to in an RTA to react the Titanium/Titanium
SiGe
.
nc

P+ Sil P-Wel
l SiGe Nitride and set the resistance of the glue layer.
sI

icon <
m

100> STI
ste
Sy
ld
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Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 82

 Tungsten Deposition & Polish-Back:
Tungsten Overburden

Next, a seed layer of Tungsten is deposited that lines the inside of the
contact holes and ensures conformal coverage of the bulk Tungsten
deposition.

Finally, ~2,500 Å of Tungsten is deposited via CVD.

G
PS
STI SiC
SiC
STI ell
SiGe
P-Wel SiGe
W
l STI SiC P-
N-We SiC
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100> STI

ste
Sy
ld
© 2018 Threshold Systems Inc.
sho
re
Th
16
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©

Tungsten
Trench
The wafers are again polished using CMP. In this operation the
Tungsten overburden is removed and the Tungsten trenches are
polished back tops of the PSG.

Next, an oxide buff operation is conducted to smooth out the surface

of the PSG oxide and ensure that the surface of the PSG is coplanar
with the top of the Tungsten trenches.
G
STI SiC
PS
SiC
STI ell
SiGe
P-Wel SiGe
W
l STI SiC P-
N-We SiC
ll
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100> STI
ste
Sy
ld
hos
re
Th
16
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©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 83

 Trench Contacts (Alternate Scheme):

Tungsten
Trench These figures illustrate what the Tungsten trenches would look like if
the PSG oxide were removed. Clearly visible are the Tungsten trenches,
clad in Ti/TiN, making electrical contact to the Source Drain regions
and to the Gate Electrodes.

These views, of course, would not be visible in a production device.

Tin
Ti/ L
CES
STI SiC tr ide
SiC Ni
SiGe
P-Wel STI SiGe ell
l W
N-We STI SiC P-
ll SiC
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
ho
s
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16
© 2018 Threshold Systems Inc.
20
©

Gate Contact

STI
P-W
ell
P+
Sili
con
<10
ell 0> STI
P-W c.
Source/Drain s In
em
Contacts yst
ld S
Inc
. sho
s hre
tem 6T
ys 201
ld S ©
e sho
6 Thr
201
©
[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 84
 Contact Module:

Contact Module:
Polished-Back

TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>

© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 85

 Plug Polish Back/Tungsten Trenches:

Polishing the Tungsten plugs down to be coplanar with the tops of the
gate electrodes is something new and was first introduced at the 32nm
Height (L)
node. Shorter Tungsten plugs have a lower contact resistance. This
feature, coupled with the raised Source/Drains for both the NMOS and
PMOS transistors, ensure that the contact resistance is kept to
TEOS SiGe SiGe TEOS SiC SiC TEOS
Poly Gate SiGe acceptableSiGe
values. TEOS
Cu Line
It is difficult to eliminate Tungsten plugs completely and adopt Cu
plugs because it is too dangerous to bring the Cu all the way down to
N-Well P-Well N-Well
the Source/Drains regions.
W Trench
© 2016 Threshold Systems Inc.
Epitaxial Silicon Source: ICE

Conductor
P+ Silicon <100> Resistance
© 2018 Threshold Systems Inc.
Length

L
R=ρ Conductor
Ax Cross-sectional The data displayed on the graph to the left makes it plain why contact
Area plugs must be polished back to such a short height at the 20nm node.
The resistivity of Tungsten is such that at the contact diameters
Resistivity required at the 20nm node the plug resistance soars to unacceptable
levels. However, because resistance is a function of length, shortening
22nm the length (i.e. the height) of the plug reduces the plugs overall
resistance.

An alternative approach to the plug resistance problem is to keep the

20nm
plugs narrow so that they fit onto the Source/Drains, but make then
very long so that they have a very high contact area, and thus, a low
overall resistance. Such contacts form trench-like structures over the
Source/Drains and are called “Trenches” because they are formed by
etching a trench in the PSG and then filling it with Tungsten.

However, the lower contact resistance of Tungsten trenches is at the

cost of higher trench-gate electrode gate capacitance.

The trend of increasing contact resistance and smaller technology

nodes appears to make Cu plugs inevitable at 7nm node.

Source: Arghavani et al., Semiconductor Fabtech

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 86

 Plug Polish Back:
Tungsten Overburden

Polished-back plugs are initially formed in the same manner as

standard plugs. After the Ti/TiN barrier metals are deposited a
Tungsten seed layer is deposited followed by the bulk CVD deposition
of 2,500Å of Tungsten.

The Tungsten overburden is then polished back until the plugs are so
short that they are coplanar with the tops of the gate electrodes.
TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well P-Well N-Well

Epitaxial Silicon
P+ Silicon <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

CMP

Exposed Polysilicon Seam

Polishing the Tungsten plugs down to be coplanar with the tops of the
gate electrodes is something new and was first introduced at the 32nm
node. Shorter Tungsten plugs have a lower contact resistance. This
feature, coupled with the raised Source/Drains for both the NMOS and
TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS PMOS transistors, ensure that the contact resistance is kept to
acceptable values.
P-Well N-Well P-Well N-Well

Epitaxial Silicon The Tungsten plugs cannot be eliminated altogether and replaced with
P+ Silicon <100> Cu plugs because it is too dangerous to bring the Cu all the way down
© 2016 Threshold Systems Inc. to the Source/Drains.

The Gate electrodes have been polished back to a thickness of ~700Å.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 87

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 88
 Device Module Gate Last:

Device Module:
Gate Last

TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 89

 Polished Back Trench Contacts:
Tungsten Overburden

Polished-back trenches are initially formed in the same manner as

standard tenches. After the Ti/TiN barrier metals are deposited a
Tungsten seed layer is deposited followed by the bulk CVD deposition
of 2,500Å of Tungsten.

The Tungsten overburden is then polished back until the trenches are
so short that they are coplanar with the tops of the gate electrodes.
G
PS
STI SiC
SiC
STI ell
SiGe
P-Wel SiGe
W
l STI SiC P-
N-We SiC
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100> STI

ste
N-We
ll

Sy
ld
hos
re
Th
© 2018 Threshold Systems Inc.
16
20
©

Gate Electrode
Tungsten Trench

Polishing the Tungsten trenches down to be coplanar with the tops of the
gate electrodes is relatively new and was first introduced at the 32nm
node. Shorter Tungsten trenches have a lower contact resistance. This
feature, coupled with the raised Source/Drains for both the NMOS and
PMOS transistors, ensure that the contact resistance is kept to acceptable
Nitride
STI values.
SiC
SiC Spacer
STI SiGe
P-Wel SiGe ell The Tungsten trenches cannot be eliminated altogether and replaced with
l -W
N-We STI SiC P
ll SiC Copper plugs because it is too dangerous to bring the Copper lines all the
STI SiGe way down to the Source/Drains because Copper is a transistor poison.
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100>
ste

N-We STI
Sy

ll
ld
sho
re
Th
16
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 90

 Gate Electrode Removal:

Gate Electrode Removal:

Once the top of the gate electrode has been opened-up, the doped
amorphous silicon gate mandrel is etched away. Thus, the gate electrode
is said to be “sacrificial”. Its only purpose was as a place-holder,
commonly referred to as a “Mandrel”.
SiC G
STI
SiC PS This etch also removes the oxide offset spacer that was grown on the
SiGe
P-Wel STI SiGe ell sidewalls of the gate cavity as well as the oxide etch stop layer at the
l -W
N-We STI SiC P bottom of the gate cavity.
ll SiC
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100>

ste
N-We STI

Sy
ll

ld
ho
s
re
Th
16
20
Gate Electrode
REMOVED! © © 2018 Threshold Systems Inc.

AmSi Gate “Mandrel”

removed

Gate Mandrel Removal:

The adjacent illustration displays a cross-sectional view of the CMOS

structure after the top of the gate electrode has been opened-up by the
TEOS SiC SiC TEOS SiGe SiGe TEOS CMP polish and the sacrificial amorphous silicon gate mandrel etched
away.

N-Well This etch also removes the oxide offset spacer that was grown on the
sidewalls of the gate cavity as well as the oxide etch stop layer at the
bottom of the gate cavity.
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 91

 Replacement Gate Process:

Before Gate Removal After Gate Removal Compressive Strain Enhancement:

The removal of the sacrificial polysilicon gate electrode dramatically

increased the amount of compressive strain in the PMOS channel region.
This occurs because the channel is already under great compressive
strain from the SiGe Source/Drains, and when the polysilicon is removed
there is less structural opposition to these compressive forces.

These factors, combined with the fact that the SiGe has been moved
closer to the gate edge, increased the PMOS drive current substantially.
Source: Intel Source: Intel

© 2018 Threshold Systems Inc.

SiON BIL

Bottom Interface Layer (BIL) growth:

Next, a layer of silicon dioxide is carefully grown and then nitrated to

TEOS SiC SiC TEOS SiGe SiGe TEOS form a thin ~10Å Bottom Interface Layer (BIL) of Silicon Oxynitride
(SiON). The formation of this layer is performed under very strict
conditions to ensure that a high mobility interface is maintained
P-Well N-Well between the SiON and the silicon surface.

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 92

 Hi-K Dielectric & PMOS WF Metal Deposition:

Hi-k (HfO2)

Hi-k Deposition:

Next, a thin ~18Å thick layer of Hafnium oxide (HfO2) is deposited using
TEOS SiC SiC TEOS SiGe SiGe TEOS ALD.

P-Well N-Well

pitaxial Silicon
con <100>
©
© 2010
2016Threshold
ThresholdSystems
Systems Inc.

© 2018 Threshold Systems Inc.

PMOS WF Metal (TiN)

PMOS WF Metal Deposition:

Next, the thin PMOS metal gate is deposited using PVD.

TEOS SiC SiC TEOS SiGe SiGe TEOS
It consists of a thin 2.0 nm layer of TiN is deposited using PVD. This is the
PMOS Work Function (WF) metal. It is a conformal layer of TiN that fills
P-Well N-Well both the PMOS and NMOS cavities as well as coats the surface of the
wafer.
pitaxial Silicon
The TiN is re-spattered after deposition to ensure good sidewall coverage
con <100> inside of the gate cavity.
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 93

 TaN & TiN Metal Deposition:

TaN ESL

TaN Etch Stop Layer Deposition:

A ~1.0 nm layer of TaN is deposited using PVD. This layer will serve as an
SiC SiC SiGe SiGe Etch Stop layer (ESL).
TEOS TEOS TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

TiN Layer

TiN Layer Deposition:

A ~5.0 nm layer of TiN is deposited using PVD. This is the first layer of
back-fill metals in the gate stack that will provide strain and electrical
TEOS SiC SiC TEOS SiGe SiGe TEOS contact to the bottom of the gate stack.

The TiN is re-sputtered to ensure good sidewall coverage inside of the

P-Well N-Well gate cavities.

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 94

 PMOS Metal Patterning & Etch:

TiN Layer Photoresist

TiN Layer Photoresist Patterning:

A layer of photoresist is spun-on and patterned. It protects only the

SiC SiC SiGe SiGe PMOS region and exposes the TiN layer over the NMOS region.
TEOS TEOS TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

Compromised
Photoresist
TaN Layer

TiN Layer Etch:

The exposed TiN layer is etched away. The TaN acts as an etch-stop layer
SiC SiC SiGe SiGe to this etch. The integrity of the very thin (<10Å) TaN layer is compromised
TEOS TEOS TEOS
by the TiN etch as indicated.

The fact that the integrity of the TaN layer is compromised is helpful when
P-Well N-Well
we diffuse Aluminum into the underlying TiN layer in the NMOS transistor
to form the NMOS TiAlN Work Function metal later in the process.
pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 95

 Photoresist Strip & TiAl Deposition:

Compromised TiN Layer

TaN Layer

Photoresist Strip:
The photoresist is stripped off and the wafers are cleaned.

TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

TiAl Layer

TiAl Layer Deposition:

A thin 4.8 nm layer of Titanium Aluminum is deposited using PVD. The

PVD process is tuned to deposit only on horizontal surfaces (this is easy to
TEOS SiC SiC TEOS SiGe SiGe TEOS do as you have to really tweak the PVD process to get it to deposit on
vertical surfaces).

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 96

 TiAl Anneal & NMOS WF Metal Formation:

TiAl

Anneal:

An anneal is then performed that causes the Aluminum in the TiAl, in

the NMOS region only, to diffuse through the TaN barrier. This creates
TEOS SiC SiC TEOS SiGe SiGe TEOS the TiAlN NMOS Work Function metal located on top of the Hi-k
dielectric.
TiAlN
P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

NMOS TiAl Layer

TaN Layer (Compromised)

Anneal:

The anneal that causes the formation of the TiAlN Work Function metal
is performed at a temperature below 400 º C. Aluminum is very
diffusive at this temperature and since the TaN which separates it from
the underlying TiN in the NMOS device was previously compromises (it
was used as an etch stop layer) the Aluminum freely diffuses into the
TiN and forms TiAlN which is the desired NMOS Work Function metal.

TEOS SiC TiAlN SiC TEOS SiGe SiGe TEOS

© 2016 Threshold Systems Inc.

[Link] P-Well N-Well

© 2018 by Threshold Systems Inc. All Rights Reserved. 97
 TiAl Backfill Deposition:

PMOS TiAl Layer

Anneal:
Thick TiN Layer
During the anneal that forms the NMOS Work Function metal the thick
TaN Layer overlaying TiN layer (which is not present in the NMOS transistor) and
the uncompromised TaN layers block the diffusion of Aluminum into
the TiN PMOS work function metal. Thus, the TiN PMOS Work Function
metal does not become TiAlN. It remains TiN, which is what is desired.

NMOS WF Metal: TiAlN

OS SiGe SiGe TEOS

PMOS WF Metal: TiN

© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

TiAl Layer

N-Well AlTi Layers Deposition:

Two thick layers (11.0nm + 7.0 nm) of Aluminum Titanium are

deposited using PVD. The PVD process is tuned to deposit only on
horizontal surfaces.

SiC SiC SiGe SiGe This metal acts as an electrical contact from the top of the gate electrode
TEOS TEOS TEOS
to the bottom.

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 98

 Metal Polish-Back:

AlTiO Layer

CMP Polish:

The metallization stack is polished back (using CMP ) so that it is

coplanar with the top of the transistor gate electrodes.
G
STI SiC
SiC
PS As part of the CMP process the uppermost layer of AlTi is oxidized to form
STI ell AlTiO.
SiGe
P-Wel SiGe
W
l STI SiC P-
N-We SiC
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100> N-We STI

ste
ll

Sy
ld
ho
s
re
Th
16
20
©
© 2018 Threshold Systems Inc.
AlTiO Layer

AlTiO Layer
TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 99

 Replacement Gate Anatomy:

NMOS PMOS
TiN
TaN TaN
TiN AlTiO

HfO2
HfO2
AlTiO
AlTi TiN WF
Metal
TiN
TiAl

TEOSTEOSSiC SiC SiC SiCTEOSTEOS SiGe SiGe SiGe SiGeTEOSTEOS

SiON BIL SiON BIL
TiALN WF
Metal

P-Well
P-Well
© 2016 Threshold Systems Inc.
N-Well
N-Well
© 2016 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

xial Silicon
licon
ncon <100>
<100>

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 100

 Strain Enhancement:

Stack of AlTiO + AiT + TiN + TiAl + TaN + TiAlN

NMOS
AlTi Layer Deposition:

Two thick layers (11.0nm + 7.0 nm) of Aluminum Titanium are

deposited using PVD. The PVD process is tuned to deposit only on
horizontal surfaces. The composition is 65% Titanium and 35%
Aluminum.

TEOS SiC SiC TEOS SiGe SiGe TEOS

NMOS Strain Enhancement:

The metal stack in both the gate cavities is very compressive in the Z-
direction. It pushes down on the transistor channel and introduces
tensile strain which enhances the drive current of the NMOS device.

P-Well
© 2016 Threshold Systems Inc.
N-Well
This tensile strain in the PMOS device degrades the drive current of the
PMOS device somewhat, but the induced tensile force is overwhelmed
© 2018 Threshold Systems Inc. by the compressive force introduced by the SiGe located in the Source/
Drains.

licon PMOS Stack of AlTiO + AiT + TiN + TiAl + TiN + TaN + TiN

n <100>
This complex metallization structure is what
makes the Replacement Gate so difficult!
TEOS SiGe SiGe TEOS

N-Well
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 101

 Nitride CESL Deposition:

Four layers of nitride (CESL)

CONTACT ETCH STOP LAYER (CESL):

Next, four layers of Silicon Nitride is deposited over the surface of the
wafer. This seals the tops of the transistors and will acts as an etch
STI SiC G stop layer for the contact trenches that have yet to be fabricated.
SiC PS ell
STI SiGe
W
P-Wel
l
SiGe P-
STI SiC
N-We SiC
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100> N-We

ste
ll

Sy
ld
hos
re
Th
16
20
©
© 2018 Threshold Systems Inc.

Four layers of nitride (CESL)

CESL

TEOS SiC SiC TEOS SiGe SiGe TEOS

P-Well N-Well

pitaxial Silicon
con <100>
© 2016 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 102

 Backend Metallization:

Wafer Fab Backend

Metallization

© 2014 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 103

 CDO/TEOS/ TiN Deposition:

TiN

TEOS
The first Inter-layer Dielectric (ILD) is deposited. It consists of a ~1,000Å
layer of Carbon Doped Oxide (CDO) that is UV cured after deposition to
bake out porogens and lower its k value.

This is followed by the deposition of a 400Å TEOS CMP stop layer and
Carbon
D CDO followed by a 300Å TiN hard mask.
oped O
xide G
STI SiC PS
SiC
P-Wel
STI SiGe ell
l
SiGe
-W
STI SiC P
N-We SiC
ll
STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon <

m
100> STI

ste
N-We
ll

Sy
ld
ho
s
re
Th
14
©
20 © 2018 Threshold Systems Inc.

Next, the wafers are primed in HMDS (to promote photoresist adhesion)
and coated with Bottom Anti-Reflective Coating (BARC) and a layer of
photoresist.

Photores
is t
O
CD
CDO
G
STI SiC PS
SiC
STI ell
SiGe
P-Wel SiGe
W
l STI SiC P-
N-We SiC
ll
STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon <
m

100> STI
ste

N-We
ll
Sy
ld
s ho
re
Th
14
20

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 104

©
 TiN Hard Mask Patterning & Etch:

The wafers are then soft-baked to give the resist a measure of structural
integrity, then the resist is exposed and developed. The resulting
TEOS photoresist pattern then undergoes a Post Exposure UV Bake (PEB) to
finalize the photoresist pattern and to turn the photoresist into a cross-
PR BARC
PR linked imidized mass that will resist etching.
PR
PR
O
CD
CDO
G
STI SiC PS
SiC
STI ell
SiGe -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We
ll

Sy
ld
hos
re
Th
14
20
© © 2018 Threshold Systems Inc.

The BARC is etched followed by an anisotropic etch of the exposed

portion of the TiN hard mask. The etch stops on the TEOS layer.

TEOS

O
CDO CD
G
STI SiC PS
SiC
STI ell
SiGe W
P-Wel SiGe P-
l STI SiC
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
ll
Sy
ld
ho
s
re
Th
14
20

105
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved.

 Photoresist Strip & Metal-1 Trench Etch:
TiN Mask

The photoresist and the BARC are stripped away and the wafers are
cleaned. The TiN hard mask has now been fully formed.

O
CDO CD
G
STI SiC PS
SiC
STI ell
SiGe W
P-Wel SiGe P-
l STI SiC
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We
ll

Sy
ld
ho
s
re
Th
14
20
©
© 2018 Threshold Systems Inc.
TiN Mask

Using the TiN hard mask as a pattern, a highly anisotropic etch cuts
through the TEOS and CDO layers to define the metal-1 trenches.
The etch stops on the SiN etch-stop layer.
Nitride
barrier

G
SiC PS
SiC
STI ell
SiGe W
STI P-Wel SiGe P-
l STI SiC
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
ll
Sy
ld
hos
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 106

 Nitride Barrier Opening TaN/Ta Deposition:

The wafers are cleaned and soft Argon sputter etch opens up the
Silicon Nitride etch stop layer at the bottom of the trench.

G Ta/TaN
STI SiC PS
SiC
STI ell
SiGe -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe CDO CDO

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We
ll

Sy
ld
BLoK

hos
re
Th
14
20
©
Source: Applied Materials

© 2018 Threshold Systems Inc.

TaN/Ta

The wafers are degassed to boil off contaminants in the trenches

and then a wet clean, followed by a soft Argon sputter, cleans out
any remaining polymeric residue and carbon contaminants from
the trenches.

Next, 80 Å of TaN followed by 30 Å of Ta are deposited using IMP

PVD. These two metals act as a barrier that will confine the not-yet-
G deposited Copper to the trenches. A re-sputter step follows both the
STI SiC PS
SiC ell Ta and TaN operations to ensure good sidewall coverage.
STI SiGe -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
Sy

ll
ld
hos
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 107

 Ta/TaN Barrier Characteristics:

The barrier material of choice is TaN to entomb the Copper in the Dual Damascene trenches and vias. Ta is the liner that
facilitates the Copper fill of these structures.
However, Ta cannot be directly deposited onto an oxide or it will configure as the high resistance beta-phase. Since the Ta
is competing with Cu for volume in the trench, the Beta phase of Ta must be avoided.

TaN adheres relatively well to oxide and is deposited first. TaN is also chemically stable and unreactive with Copper.

Ta is deposited second because when it is deposited on top of TaN it manifests itself in the low resistivity alpha phase
which is highly desirable

Copper is a transistor poison and cannot be allowed to contaminate the active layer. Therefore it must be entombed on all
sides by diffusion barriers (Ta/TaN on five sides & a SiN seal on the top).

© 2018 Threshold Systems Inc.

Tantalum has two phases, the high resistance SiCN Seal & ES Layer
Beta-phase and the low-resistance Alpha phase

TaN/Ta Diffusion
Barrier
Trench

When placed directly onto oxide Ta assumes its Via

high resistance Beta phase. Since it is desirable When placed deposited onto a TaN coated surface,
to have the Ta resistance as low as possible, this Ta assumes its low resistance Alpha phase.
phase is highly undesirable.

M. Travig et. Al. Semiconductor International © 2007 Threshold Systems

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 108

 Copper Seed & Copper Bulk Deposition:

Cu Seed

Without breaking vacuum, 300Å of Copper seed is deposited across

the wafers which lines the interior of the trenches.

The Copper seed is required to ensure conformal void-free bulk

Copper deposition and is a necessary precondition for the
electroplating process.

G
STI SiC PS
SiC
STI ell Ta/TaN
SiGe W
P-Wel SiGe P-
l STI SiC
N-We SiC
ll STI SiGe
Cu Seed

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100> N-We CDO

ste
ll

Sy
ld
hos
re
Th
14
20
©
© 2018 Threshold Systems Inc. Underlying Cu Line

Next, 6,000 Å of bulk copper is then deposited using electrochemical

deposition.

After deposition, the Copper is annealed at 300 ºC for 90 seconds in

forming gas to set its grain structure and reduce its resistance.
Electropla
ted Copp
er
Cu Overburden
G
STI SiC PS
SiC
STI ell Ta/TaN
SiGe -W
P-Wel SiGe P
l STI SiC CDO
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
ll
Sy
ld
hos
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 109

 Copper-Ta/TaN-TEOS CMP:

TEOS

The Copper is polished back using CMP. This polishing also removes the
Tantalum that was on the upper surfaces of the TEOS. The softer TEOS
acts as a polish stop for the CMP process.

Next, an oxide buff operation is conducted to smooth out the surface of

Cu the TEOS oxide and ensure that the surface of the TEOS is coplanar with
Cu the top of the Copper lines.
Cu
G
STI SiC Cu PS
SiC ell
After each CMP operation the wafers are cleaned.
STI SiGe W
P-Wel SiGe Cu P-
l STI SiC
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We

Sy
ll

ld
hos
re
Th
14
20
©
© 2018 Threshold Systems Inc.
30 Å of SRN < 30 Å of CuSix < 30 Å of SiN
The Cu surface is cleaned of organic impurities left behind from the CMP
clean. This is accomplished by employing a multiple step plasma assisted
reducing chemical that eliminates Cu oxide and other organic impurities.

Copper Copper Copper Next, a thin 30Å layer of Silicon Rich Nitride (SRN) is deposited that reacts
with the Cu to form a Cu silicide (CuSix). This is a self-limiting reaction and
the CuSix limits the Cu diffusion by locking-up the Cu on the upper surface
of the trench in the SRN matrix. The CuSix is electrically leaky so it is next
subjected to a nitridization step to convert it to SiN film.

The SRN treatment is highly effective in sealing in the Cu and enables a

CSiGe SiC SiCTEOS TEOS
SiCSiGe TEOS SiGe
SiC SiGe SiGe
SiC TEOSTEOSSiGe SiC
TEOS
SiGe SiGe SiCTEOSTEOS SiGe SiGe TEOSsealant film to be deposited. This results in a lower Keffective for
thinner SiCN
the ILD stack.
© 2011 Threshold Systems © 2011 Threshold Systems © 2011 Threshold Systems
N-Well
P-Well
P-Well N-Well N-Well
P-Well N-WellP-Well N-Well

Epitaxial Silicon Epitaxial Silicon

P+ Silicon <100> P+ Silicon <100>
[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 110
 Copper Sealing:

30 Å of SRN

A thin 30Å layer of Silicon Rich Nitride (SRN) is deposited across the wafer.

Cu
Cu
Cu
G
STI SiC Cu PS
SiC
STI ell
SiGe
Cu -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We
ll

Sy
ld
ho
s
re
Th
14
20
©
© 2018 Threshold Systems Inc.
30 Å of SRN

< 30 Å of CuSix A thin 30Å layer of Silicon Rich Nitride (SRN) reacts with the Copper metal
to form a Copper silicide (CuSix).

Cu
Cu
Cu
G
STI SiC Cu PS
SiC
STI ell
SiGe
Cu -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
ll
Sy
ld
ho
s
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 111

 Copper Sealing & Barrier Deposition:

SiN
The CuSix is then subjected to a nitridization step to convert it to SiN
film.

Cu
Cu
Cu
G
STI SiC Cu PS
SiC
STI ell
SiGe
Cu -W
P-Wel SiGe P
l STI SiC
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI

m
100>

ste
N-We
ll

Sy
ld
hos
re
Th
14
20
©
© 2018 Threshold Systems Inc.
SiCN

A 300Å etch-stop layer of SiCN is deposited to seal off the top of the

first layer of metal. The Copper in the first layer of metal is now
entombed with Ta/TaN on five sides and SiCN on the top.

Cu
Cu
Cu
G
STI SiC Cu PS
SiC
STI ell
SiGe
Cu W
P-Wel SiGe P-
l STI SiC
N-We SiC
ll STI SiGe
.
nc

P+ Sil P-Wel SiGe

l
sI

icon < STI

m

100>
ste

N-We
ll
Sy
ld
hos
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 112

 The Role of a Local Interconnect:
© 2018 Threshold Systems Inc.
Local Interconnects Cross-Sectional View

Local Interconnects enhance packing density by allowing electrical inter-connections to be made

at the device level without having to route signals to several higher levels of metal. They simplify
Gnd Vdd
signal routing and are highly desirable for devices with extremely high transistor counts. Local
Interconnect
To understand how Local Interconnects are used, consider the example of a simple inverter, the
B

© 2011 Threshold Systems

schematic of which is presented below. In this example the Drain of a NMOS device (denoted as
“A”) and the Source of a PMOS device (denoted as “C”) are joined together and pulled out to a A C
common output denoted as “B”.
TEOS SiC SiC TEOS SiGe SiGe TEOS SiC SiC TEOS SiGe SiGe TEOS
The top-down and cross-sectional view presented to the right illustrate how an inverter might be
realized in Silicon. We can see that the Drain of the NMOS device (A) is physically and electrically
P-Well N-Well P-Well N-Well
connected to the Source of the PMOS device (C) by the Cu Local Interconnect (B).
Epitaxial Silicon NMOS PMOS
P+ Silicon <100>

Schematic of an Inverter Top-Down View

Input
Vdd

© 2011 Threshold Systems

Trench Oxide

C
NMOS pulls Input
up to Vdd

NMOS Gate Electrode

PMOS Gate Electrode

Input Output B
Gnd Vdd
Local
Interconnect
P-Well N-Well
NMOS pulls Input
A down to GND A C

GND
B
Output

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 113

 Why Do We Need Low-k Dielectrics?

Cross-Talk

Dielectric Capacitance

ῖ = RC
Time Delay

Conductor
Resistance
1 2 3
© 2018 Threshold Systems Inc. Low-k Dielectric

Interconnect delay can be nearly 20 times greater than gate delay at the © 2011 Threshold Systems Inc.

22nm node. High Voltage

Copper alone is insufficient to minimize interconnect delay. Low-k Line 1 Low Voltage
dielectrics must be used between the Cu lines to minimize capacitive
coupling between adjacent metal lines, and to a lesser extent, between
Line 2 High Voltage
stacked metal lines.
Low Voltage
The use of Cu metal lines and Low-k dielectrics dramatically reduces the RC
time constant enhancing chip speed.
High Voltage
Low-k materials will not easily support an electric field, and therefore inhibit Line 3 Low Voltage
adjacent metal lines from capacitively coupling. This minimizes parasitic Time
capacitances and lowers the probability of cross-talk between adjacent
metal lines, a mechanism that can result in data corruption. Adjacent metal lines embedded in a dielectric will capacitively couple with each
other. At very small geometries, and especially at the 22nm node, this capacitive
coupling will lead to cross-talk between the lines. This results in signal distortion.
A worst case scenario occurs when one metal line is transitioning into a low
voltage state, when lines on either side of it are transitioning to a high voltage
state. The line that is attempting to enter the low-voltage state will experience
strong cross talk as a result of capacitive coupling, and will distort the digital
signal that it is carrying. A low-k dielectric is extremely helpful in avoiding this
kind of problem because it will not readily support the electric field that
facilitates cross-talk.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 114

 Kinds of Low-k Dielectrics:

The baseline generation of backend dielectrics was SiO2 which served the industry well
for several generations. It was hard, easy to etch, had good coefficients of thermal Low-K Dielectric Generations
expansion and conduction, a high breakdown voltage and was an excellent insulator.
However, with a K-value of 3.9 - 4.2 it was an unacceptable dielectric for advanced Dielectric Constant Vs. Hardness
technology nodes. 5

SiO2

Dielectric Constant (k)

The first generation of low-k dielectric to achieve widespread adoption was Fluorinated 4
Silicon Glass (FSG) which was introduced at the 130 nm node and used extensively at the FSG

90 nm node. It is simply SiO2 that has been doped with Fluorine to make it less polar and 3
OSG
reduce its k-value to ~ 3.5
!

Source: Air Products

2

UL-k
The second generation of low-k dielectrics was carbon doped oxide (CDO), which are
also known as Organo-Silicate Glass (OSG), or more specifically as SiCOH (marketed as 1
0 1 2 3 4 5
“Black Diamond”). This material has a k-value of ~ 3.0 and saw widespread use at the 90 Hardness (GPa)
nm and 65 nm nodes. The k-value can be lowered to 2.7 by increasing the Carbon
content of the film, and a porous version of this dielectric is used at the 45/32/28nm As the k-value of a dielectric film declines so does its hardness.
nodes having a k-value of ~2.5 This reduction in mechanical strength introduces a range of
serious processing issues that has become one of the biggest
A third generation of low-k dielectrics consisting of porous polymers with k-values <2.0 challenges for sub-32nm node technology.
has proven to be elusive.

© 2018 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 115

 ILD-2 Deposition:

Photoresist

Next, 7,000 Å of a Low-k SiCOH is deposited and then UV baked to

remove the porogens and lower the k-value of the dielectric. This is
followed by 400 Å of TEOS (a polish stop), followed by a 300Å layer
BARC of TiN hard mask and 300Å of BARC and a layer of photoresist.

The photoresist is then patterned.

Carbon D
o ped Oxide
(CDO)
Cu
Cu
Cu
G
PS
STI SiC

P-Wel
SiC

l
STI SiGe
SiGe
STI SiC
Cu
Cu P-
W
ell
© 2018 Threshold Systems Inc.
N-We SiC
ll STI SiGe

.
nc
P+ Sil P-Wel SiGe
l

sI
icon < STI
m
100> N-We ste
ll
Sy
ld
hos
re
Th
14
20
©

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 116

 TiN Hard Mask Etch & PR Strip:

The BARC is etched followed by an anisotropic etch of the TiN hard

mask.

Carbon
D oped O
xide (C
Cu DO)
Cu
Cu G
PS ll
e
Cu W
P-
Cu

.
nc
sI
m
ste
Sy
ld
hos
re
20
Th
14
© 2018 Threshold Systems Inc.
©

TEOS TiN Hard Mask

The BARC is etched followed by an anisotropic etch of the TiN hard
mask. The photoresist is then stripped and the wafers cleaned. The
TiN hard mask remains behind.

Carbon
D oped O
xide (C
Cu DO)
Cu
Cu G
PS l
el
Cu P-
W
Cu
.
nc
sI
m
ste
Sy

STI
ld

N-We
ho

ll
s
re
Th
14
20

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 117

©
 Via Photo & Via Partial Etch:

The wafers are then coated in BARC and Photoresist. The

photoresist is then patterned.
Photores
is t
Photores
is t
Photores
is t
Carbon
D oped O
xide (C
Cu DO)
Cu
Cu
Cu
Cu

.
nc
sI
m
ste
Sy
ld
hos
re
Th
14
20
© © 2018 Threshold Systems Inc.
The vias are partially etched in a highly anisotropic etch recipe.
They are not etched all the way down to the SiCN etch-stop layer.

Photores
ist
Photores
is t
Photores
is t x ide
dO
Via o pe
Hole nD
rbo
Cu Ca
Cu
Cu
Cu
Cu
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nc
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 118

 Photoresist Strip & Trench Etch:

The BARC and the photoresist are stripped and the wafers are
cleaned.

id e
Ox
Via
p ed
Hole Do Trench
on
Cu rb
Ca
Cu
Cu Via
Cu
Cu

.
nc
sI
m
ste
Sy
Source: Lam Research

ld
ho
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© © 2018 Threshold Systems Inc.
Using the TiN hard mask pattern as a template, the Metal-2 trenches
are etched. During this operation the vias are fully etched. The via
etch stops on the SiCN etch stop layer and may etch slightly into this
layer.

Trench ide
Ox
p ed Trench
Via Do
n
Cu
Hole
SiCN rbo
Ca
Cu Via
Cu
Cu
Cu
.
nc
sI

© 2010 Threshold Systems

m
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 119

 SiCN Barrier Opening:
TiN Hard
Mask

A head-on view of the Dual Damascene structure displaying the trench

and numerous via holes.

Note that the SiCN barrier at the bottom of the vias has not yet been
punctured.

SiCN Via Hole

Carbon Doped Oxide

Cu Cu Cu Cu Cu

© 2014 Threshold Systems Inc.

© 2018 Threshold Systems Inc.

A soft Argon sputter etch is used to open the SiCN BLOk layer at the
bottom of the vias and expose the underlying Copper line. This is a very
delicate step. To aggressive a sputter etch and Copper will be sprayed
up into the unshielded Dual Damascene structure. To mild an etch and
x ide the SiCN barrier will not be completely removed resulting in high via
dO
ope resistance.
nD
rbo
Cu Ca
.
nc

Cu
sI
m

Cu
ste
Sy
ld

Cu
hos
re

Cu
Th
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Etch-Stop
Opening

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 120

 Barrier Deposition Methodology:

O. Van der Straten et al., MRS Proc.,

The re-sputtering of TaN is essential for 32/28 nm technology because it ensures more conformal coverage of the
inside of the Dual Damascene structure.

vol 716, 2002, pg 471

PVD will continue to be the predominant technology for thin barrier deposition at the 22nm and 14nm nodes and
probably for the foreseeable future.
Although ALD technology offers vastly superior conformal coverage and can can be scaled to extremely small
dimensions, it’s deposition rates are very slow and the carbon precursor used with ALD degrades adhesion. In ALD Barriers are extremely
addition, film continuity and “steric hinderance” are problematic with ALD. It appears that PVD technology will be thin and conformal, but this
used for barrier deposition for the foreseeable future. technology will probably not
be used until the 10 nm node
or below.

© 2018 Threshold Systems Inc.

H2O CxHy Ar TaN Ar Ta Cu
Chemical
Clean

© 2007 Threshold Systems

© 2007 Threshold Systems

© 2007 Threshold Systems

© 2007 Threshold Systems

© 2007 Threshold Systems

© 2007 Threshold Systems

© 2007 Threshold Systems

Contaminants
(Cu Oxide, etch
residues)

Degas Clean Sputter Clean TaN Deposition TaN Re-sputter Ta Deposition Cu Seed Deposition
The wafers are heated up A clean is applied The bottom of the via A thin layer of TaN is The TaN is sputtered in & Re-sputter A thin ~ 300Å layer of
to ~ 200 C to boil off water (usually a HN03/HF structure is then sputter deposited using an Ar sputter etch. This A very thin Layer of Ta Cu is deposited via
and other contaminants blend) to further remove clean with a “soft” Ar Ionized Metal Plasma redistributes the TaN is then deposited via PVD
any etch residues in the sputter etch to remove (IMP) from the bottom of the IMP PVD & then re- Critical steps
Dual Damascene any residual via and trench & sputtered for 28 nm
structure. The wafers are contaminants. improves side-wall
then dried. coverage

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 121

 TaN/Ta Barrier :
Tan/Ta

The wafers are degassed to boil off contaminants in the trenches and

then a wet clean followed by a soft Argon sputter to clean out any
x ide remaining polymeric residue, CuO, and carbon contaminants.
dO
o pe Next, ~80 Å of TaN followed by ~30 Å of Ta are deposited using IMP PVD.
nD
rbo These two metals act as a barrier that will confine the not-yet-deposited
Cu Ca Copper to the trenches. A re-sputter step follows both the Ta and TaN
Cu operations.
Cu
Cu
Cu

.
nc
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© 2018 Threshold Systems Inc.
Tan/Ta
A head-on view of the Dual Damascene structure displaying the trench
and numerous via holes coated in Tan/Ta.

Like the contact holes, via holes are very tiny and difficult to fill with
barrier metal. However, this problem is especially important for via
holes since it is critical that they be continuously lined with Ta/TaN in
order to entomb the copper that will later fill them. Any discontinuity
in the Ta/TaN barrier metal will allow copper atoms to leak out of the
Via Hole via and will result in transistor poisoning.
Carbon Doped Oxide
Dedicated Ta/TaN ionized PVD tools combined with a sputter
Cu Cu Cu Cu Cu operation ensure that proper barrier coverage is achieved.

© 2014 Threshold Systems Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 122

 Cu Seed Deposition & Electroplated Copper:
Cu Seed

Without breaking vacuum, 300Å of Copper seed is deposited across the

wafers which coats the interior of the trenches.

x ide The Copper seed is required to ensure conformal void-free bulk Copper
dO deposition (the following operation) and is a necessary precondition for
o pe
nD the electroplating process.
rbo
Cu Ca
Cu
Cu
Cu
Cu

.
nc
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Next, 6,000 Å of bulk copper is deposited using electrochemical

deposition.

Electroplated After deposition, the Copper is annealed at 300 ºC for 90 seconds in

Copper forming gas to set the grain size.
id e
Ox
p ed
Do
on
rb
Ca
Cu
Cu
Cu
© 2018 Threshold Systems Inc.
Cu
.

Cu
nc
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 123

 Copper CMP Polish & Final Seal:
TEOS

The Copper is polished back using CMP. This polishing also removes the
Tantalum that was on the upper surfaces of the TEOS. The TEOS acts as a
Cu x ide polish stop for the CMP process.
Cu dO
Cu o pe Next, an oxide buff operation is conducted to smooth out the surface of the
Cu nD
rbo TEOS oxide and ensure that the surface of the TEOS is coplanar with the top
Cu Cu Ca of the Copper lines.
Cu
Cu After each CMP step the wafers are cleaned.
Cu
Cu

.
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©
© 2018 Threshold Systems Inc.
SiCN
After the same SRN layer is deposited, converted to CuSi and then to
SiN, a 300Å layer of SiCN is deposited to seal off the top of the second
layer of metal. The Copper in the second layer of metal (and its via) is
now entombed with TaN/Ta on five sides and SiCN on the top.

Cu x ide NoteUnderlying
that in thisCu
Dual
LineDamascene integration methodology the
Cu dO photoresist never touched the low-k dielectric.
Cu o pe
D
Cu
b on
r Seven further layers of metal trenches and vias are defined in a similar
Cu Cu Ca
fashion.
Cu
Cu
Cu
Cu
.
nc
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[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 124

 Backend Metallization:

Conductor
Length
Resistance
Metal 9
L © 2018 Threshold Systems Inc.
R=ρ Conductor
Ax Cross-sectional
Area

Resistivity M8

We want R to be LOW! ῖ = RC V
i V
a i
a

M7

M6

M5
© 2011 Threshold Systems

M4

M3
Trench Trench Trench Trench

V V V V V V V M2
i i i i i i i
a a a a a a a M1
Trench Trench Trench Trench

© 2014 Thre
shold Systems
Inc.
© 2011 Threshold Systems

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 125

 Metal Hierarchy:

Metal 9 © 2018 Threshold Systems Inc.

Global Wires (up to 2 layers) SiCN capping
usually 5-10 mm in length; layer
often in FSG or oxide. They
carry power, ground and M8
clock signals Carbon Doped
Oxide (CDO) Wiring Hierarchy
V
i V
a i
a

M7

Semi-Global Wires (up to 4

layers) typically 0.5-5 mm in
M6
length; usually in CDO.

M5

Intermediate Wires (up to 5 M4

layers) typically <100 µm in
Cu trench
length; usually in CDO
M3

M2 Cu via

M1 & contacts (one layer) M1

typically <50µm in length; W Trench
usually in CDO

© 2014 Thre
shold Systems
Inc.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 126

 C4 Connections to the External World:
C4 - “Controlled Collapse Chip Connection”

© 2011 Threshold Systems

Solder Balls

© 2010 Chipworks - Courtesy of Chipworks

Copper Pillars

© 2018 Threshold Systems Inc.

Copper Pillars

Cu Pillar

Cu Pillars Cu Pillars

The conventional solder balls have been replaced at the 45/32 nm node with “Copper Pillars” to
© 2010 Chipworks - Courtesy of Chipworks comply with RoHS (Restriction of Hazardous Substances) and to act as a Peltier effect cooling conduit
to drain heat away from the chip.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 127

 Characteristics of the 20nm Generation:
© 2018 Threshold Systems Inc.
Advantages Disadvantages

Incorporated 3rd generation Metal Gate High-k technology This generation of microchips demanded the extensive use of 193
with a more aggressively scaled dielectric (EOT reduced from immersion lithography and extremely sophisticated and
10Å to 9Å). expensive reticles sets.
Strained silicon continued to provided a dramatic speed boost The requirement for damascene-like replacement gates and their
and this technology node employed 4th generation strain associated complex internal metallization morphologies
technology that incorporating 40% Ge in the SiGe of the PMOS dramatically increased processing complexity.
and the use of 1st generation SiC in the NMOS Source/Drains.
Ultra-thin barriers for copper metallization faced new deposition
The lithography process moved from 193 dry litho to 193i challenges at the 20nm nodes as the metal lines scaled to
immersion lithography. extremely small dimensions.
NMOS S/D leakage has been reduced 5X; PMOS S/D leakage The extremely narrow gate electrodes present at the 20nm node
has been reduced 10X. posed special etch uniformity problems that required innovative
The use of porous CDO (Carbon Doped Oxide) significantly forward/feedback mechanisms to control.
lowered the k value of the inter-layer dielectric stack, which in
The ultra-shallow Source/Drain regions required complex and
turn permitted higher back-end speeds.
careful implant schemes and millisecond spike anneal
TiN metal hard masks substantially improved trench technology.
morphology and enabled very narrow trenches to be cleanly
defined. The cost of a manufacturing facility dedicated to the production
of 20 nm devices easily approached or exceeded seven billion+
Amorphous carbon hard masks greatly enhanced the dollars.
definition of STI, gate electrodes and narrow contact holes.
The high level of processing complexity associated with the
The use of double patterning dramatically improved gate replacement metal gate significantly increased overall cost.
electrode scaling.
There are significant questions regarding the scalability of the
Transistor counts at the 20 nm node reached 1.7+ billion.
replacement gate methodology, particularly at the 7 nm node.

[Link] © 2018 by Threshold Systems Inc. All Rights Reserved. 128