History of Instruction
Set Architectures
Presented by:
Aayam | Sandarva | Youban
Aayush | Roman | Sushan
Nishal B. | Nischal D. | Samir
Introduction to
Instruction Set
Architecture (ISA)
- An Instruction Set Architecture is a set the
language of CPU which tells what operations
that CPU can perform and how it is carried out
such as, logical operations, memory
operations, jumping to other instructions etc.
- It is set of specific instruction rules defining
how software communicates with hardware
such as instructions length, format, what type
of memory can be used, what compilers can
be used etc.
Types of ISA:
1. Complex Instruction Set Computer (CISC)
2. Reduced Instruction Set Computer (RISC)
Introduction to
CISC
- Introduced during 1960s-1970s
- Key vision to introduce was
• Simplify Programming
• Performing multi-step instruction to shorter
instructions
• Fewer instruction to remove memory constraints
(Memory was expensive at that era)
- Early Adopters: IBM's mainframes, DEC VAX, and
Motorola 68000, the Intel 8086/80x86 family.
Features and
Characteristics of CISC
- Uses variable length Instruction
- Large set of complex operations can be performed in
a single instruction
- This reduces number of instruction a program need
- Requires multiple clock cycles to execute
- Contains several special purpose registers
- Micro instructions are written to match construct of
high-level language, making compiler simpler
- Rich Instructions set
- Versatile
- Backward Compability
- Efficient on memory
- Commonly used in x86 and x64 devices
Drawbacks of CISC
- Slower execution / Multiple clock cycles
- Complex design
- High power consumption
- Inefficient pipelining
- Larger chip size due to hardware
complexity
- Limited parallelism
Introduction to
RISC
- Introduced during late 1970s–1980s
- Key vision to introduce was
• Simplify Processor Design
• Execute simple instructions faster
• Use more instructions but each completes in a
single clock cycle
• Shift complexity from hardware to software
(compiler optimization)
• Early Adopters: Berkeley RISC, IBM (801), Sun
Microsystems (SPARC), ARM
Features and
Characteristics of
RISC
- Uses fixed-length instructions
- Small set of simple instructions
- Most instructions execute in a single clock cycle
- Load/store architecture (memory accessed only
by load and store instructions)Large number of
general-purpose registers
- Simple instruction decoding
- Designed for efficient pipelining
- Compiler-based optimization
- High instruction throughput
- Energy efficient
- Commonly used in arm devices and various
micro-devices
Drawbacks of RISC
- Programs require more instructions
- Larger code size compared to CISC
- Higher dependence on compiler
efficiency
- high memory usage
- Complex compiler design
- Less efficient for certain complex
operations
Comparison of CISC and RISC
Aspect CISC RISC
Instruction Set Large and Complex Small and simple
Instruction length Variable length Fixed length
Execution time Multiple clock cycles Mostly single clock cycle
Memory access Direct access memory to Load/Store access memory only
instructions
Registers Fewer general-purpose registers More general-purpose registers
Pipelining Difficult and inefficient Easy and efficient
Parallelism Hardware-emulated and difficult Architecturally clean and
predictable
Compiler Simpler Complex
Hardware Design Complex Simple
Power Consumption Very high Lower
Chip size Relatively big Relatively small
Performance focus Minimize program size Maximize execution speed
Background Compability Strong and widely available Limited
Usage PCs, Workstations, Servers Embedded systems, mobile
devices, super computers
Examples X86/x64 family, VAX, Motorola ARM, MIPS, SPARC, RISC-V
68000
Conclusion
- RISC uses simple instructions for fast,
efficient, and parallel execution, ideal for
embedded, mobile, and low-power
systems.
- CISC uses complex instructions for
compatibility and high-performance
computing, ideal for desktops,
workstations, and legacy systems.
- Modern CPUs often blend both approaches
to achieve speed, efficiency, and versatility.