N.C.I.
T COLLEGE
Balkumari, Lalitpur.
AFFILIATED TO POKHARA UNIVERSITY
BE-COMPUTER FIFTH SEMESTER
LAB REPORT FOR EMBEDDED SYSTEM
SUBMITTED BY: SUBMITTED TO:
NIRAJ BHUSAL ER. SIMANTA KASAJU
Roll No: 221315
INDEX
S.N
LAB TOPIC DATE
1. INTRODUCTION TO VHDL 1st
Mangsir
2.
LAB 1: INTRODUCTION TO VHDL
VHDL:-
VHDL stands for Very High-Speed Integrated Circuit Hardware
Description Language. It is used to model, simulate, and implement
digital circuits and systems. Primarily utilized for designing FPGAs (Field-
Programmable Gate Arrays) and ASICs (Application-Specific Integrated
Circuits). VHDL allows for a textual representation of a circuit, enabling
designers to write and verify the functionality of complex systems before
physical implementation.
Key Components of VHDL:
a. Entity Declaration
Defines the interface of a digital circuit, specifying its inputs
and outputs.
Example:
entity AND_Gate is
Port ( A : in std_logic; -- Input signal A
B : in std_logic; -- Input signal B
Y : out std_logic -- Output signal Y );
end AND_Gate;
The entity section declares the external connections of the circuit.
b. Architecture Definition
Describes the internal behavior or structure of the circuit
defined by the entity.
Example:
architecture Behavioral of AND_Gate is
begin
Y <= A and B; -- Output Y is 1 only if both A and B are 1
end Behavioral;
The architecture block specifies the logic that drives the circuit
output.
c. Libraries and Packages
VHDL uses libraries to import standard functions and types.
Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
The IEEE.STD_LOGIC_1164 package includes common data types
such as std_logic and logical operators (and, or, not).
Fundamental Building Blocks in VHDL
Signals: Act like wires carrying data between parts of a design.
signal A, B : std_logic;
signal Y : std_logic;
Processes: Blocks of code that execute sequentially. Typically used
for conditional and sequential logic.
process (A, B)
begin
if A = '1' and B = '1' then
Y <= '1';
else Y <= '0';
end if;
end process;
Components: Reusable modules that can be instantiated in larger
designs.
Ports: Define the direction of signals:
in: Input signals
out: Output signals
inout: Bidirectional signals
VHDL Operators and Their Usage
Operator Symbol Description
Logical and, or, not, xor Performs bitwise
logical expressions
Comparison =, /=, <, >, <=, >= Comparisons
between signals
Assignment <= Assigns value to
the signal
Arithmetic +, -, *, / Performs
arithmetic
calculations
Example:
Y <= A and B; -- Logical AND operations
Data Types in VHDL
a. Basic Data Types
bit: Represents a single binary value ('0' or '1').
signal A : bit := '0';
std_logic: An enhanced type with additional states ('0', '1', 'Z', 'X',
etc.) for digital circuits.
signal B : std_logic := '1';
integer: Used for whole numbers.
signal Count : integer := 0;
boolean: Represents true or false values.
signal flag : boolean := false;
b. Composite Data Types
Arrays: Used to represent buses or collections of bits.
signal Data : std_logic_vector(7 downto 0); -- 8-bit bus
Records: Used to group different data types.
Levels of Abstraction In VHDL
In VHDL, digital systems are described using different levels of
abstraction. Each level focuses on a different aspect of the system's
design, allowing flexibility in how you approach the development of
hardware systems. These levels help in managing the complexity of
designs and facilitate verification and testing.
A. Behavioral Level:
Describes what the system does using high-level algorithms.
Uses processes, loops, and conditional statements.
Example: Writing code for a counter or state machine logic.
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
count <= 0;
else
count <= count + 1;
end if;
end if;
end process;
B. Dataflow Level:
Describes how data flows between different components.
Uses concurrent statements and operators (and, or, etc.).
Example: Y <= A and B; (AND gate logic).
C. Structural Level:
Describes the actual connections between components (like
connecting gates or modules).
Focuses on building circuits using instances of sub-components.
Example: Connecting pre-defined gates to form a full adder circuit.
S <= A xor B xor Cin;
Cout <= (A and B) or (B and Cin) or (A and Cin);
Walkthrough with model simulator
1) Opening model sim
2)Going to file
3) create project with appropriate name and leave all the
field as it is and click OK.
4) Now Click create New file
5) Now we are ready to code
OR_gate Theory:-
An OR gate is a basic logic gate in digital electronics that
outputs 1 (true) if any of its inputs are 1 (true). If all inputs are 0 (false), the
output will be 0 (false).
CODE:-
VHDL program code for Or_gate
library ieee;
Use ieee.std_logic_1164.all;
--Entity section
Entity niraj_orgate is
Port(A,B: in std_logic;
C:out std_logic);
End niraj_orgate;
--Architecture section
Architectural Behavioral of niraj_orgate is
Begin
C<=A or B;
End Behavioral ;
Output of data flow code
Wave output of above or_gate VHDL code
CONCLUSION :
By using the model-sim, we can easily
simulate(observe) the behavior about how actually different
types of gate structure works very well in an efficient way. In
this we simulate the behavior of Or_Gate.