Introduction to CMOS Circuits

Mohammed Sharaf Sayed

[Link]@[Link]
 Outline
• Introduction
• MOS transistor
• CMOS Static Gates
• CMOS Transmission Gates
• Multiplexers
• Latches and Flip-Flops
 Introduction
• Integrated circuits: many transistors on one chip.

• Very Large Scale Integration (VLSI)

• Complementary Metal Oxide Semiconductor

–Fast, cheap, low power transistors

• Objective: How to build a good CMOS chip

 A Brief History
• 1958: First integrated circuit
–Flip-flop using two transistors
–Built by Jack Kilby at Texas
Instruments Courtesy Texas Instruments

• 2010
–Intel Core i7 mprocessor
• 2.3 billion transistors
–64 Gb Flash memory
[Trinh09]
• > 16 billion transistors © 2009 IEEE
 Moore’s Law
• 1965: Gordon Moore plotted transistor number
on each chip
–Fit straight line on semilog scale
–Transistor counts have doubled every 26 months
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates

[Moore65]
Electronics Magazine
And Now…
 Feature Size
• Minimum feature size shrinking 30% every 2-3
years
 nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a capacitor
–SiO2 (oxide) is a very good insulator
–Called metal – oxide – semiconductor (MOS) capacitor
–Even though gate is no longer made of metal
Source Gate Drain
Polysilicon
SiO2

n+ n+
Body
p bulk Si
 nMOS Operation
• Body is usually tied to ground (0 V)
• When the gate is at a low voltage:
–P-type body is at low voltage
–Source-body and drain-body diodes are OFF
–No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si
 nMOS Operation Cont.
• When the gate is at a high voltage:
–Positive charge on gate of MOS capacitor
–Negative charge attracted to body
–Inverts a channel under gate to n-type
–Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si
 pMOS Transistor
• Similar, but doping and voltages reversed
–Body tied to high voltage (VDD)
–Gate low: transistor ON
–Gate high: transistor OFF
–Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si
 Power Supply Voltage
• GND = 0 V
• In 1980’s, VDD = 5V
• VDD has decreased in modern processes
–High VDD would damage modern tiny transistors
–Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
 Transistors as Switches
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to
drain g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s
 CMOS Inverter

A Y VDD
0 1
1 0 OFF
ON
0
1

A Y
ON
OFF

A Y
GND
 CMOS NAND Gate

A B Y
ON
OFF
OFF
ON OFF
ON
0 0 1
0 1 1
1
0
Y
ON
1 0 1
A OFF

1 1 0 0
1
1
0
OFF
ON
B ON
OFF
 CMOS NOR Gate

A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y
 3-input NAND Gate
• Y pulled low if ALL inputs are 1
• Y pulled high if ANY input is 0

Y
A
B
C
 CMOS Gate Design
• Activity:
–Sketch a 4-input CMOS NOR gate

A
B
C
D
Y
 Complementary CMOS
• Complementary CMOS logic gates
–nMOS pull-down network pMOS
pull-up
network
–pMOS pull-up network inputs
output
–Also known as static CMOS
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFF Z (float) 1

Pull-down ON 0 X
 Series and Parallel a a a a a
0 0 1 1
g1
g2
• nMOS: 1 = ON b
0
b
1
b
0
b
1
b
(a) OFF OFF OFF ON

• pMOS: 0 = ON a a a a
a

• Series: both must be ON g1

g2
0 0 1 1

0 1 0 1

• Parallel: either can be ON (b)

b b
ON OFF
b
OFF
b
OFF
b

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(c) OFF ON ON ON

a a a a a

g1 g2 0 0 0 1 1 0 1 1
b b b b b

(d) ON ON ON OFF
 Conduction Complement
• Complementary CMOS gates always produce 0
or 1
• Ex: NAND gate
–Series nMOS: Y=0 when both inputs are 1
–Thus Y=1 when either input is 0 Y
–Requires parallel pMOS A
B

• Rule of Conduction Complements

–Pull-up network is complement of pull-down
–Parallel -> series, series -> parallel
 Compound Gates
• Compound gates can do any inverting function
• Ex: Y  AB  CD (AND-OR-INVERTER AOI22)
A C A C
B D B D
(a) (b)

C D
A B C D
A B
(c)
(d)

C D
A
A B
B
Y Y
C
A C
D
B D
(f)

(e)
 Example:
• Y  ( A  B  C)D

A
B
C D
Y
D
A B C
 Signal Strength
• Strength of signal
–How close it approximates ideal voltage source
• VDD and GND rails are strongest 1 and 0
• nMOS pass strong 0
–But degraded or weak 1
• pMOS pass strong 1
–But degraded or weak 0
• nMOS are best for pull-down network
• pMOS are best for pull-up network
 Pass Transistors
• Transistors can be used as
switches
g g=0 Input g = 1 Output
s d 0 strong 0
s d
g=1 g=1
s d 1 degraded 1

g=0 Input Output

g g=0
s d 0 degraded 0
s d g=1
g=0
s d 1 strong 1
 Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb

g g g
a b a b a b
gb gb gb
 Tristates
• Tristate buffer produces Z when not enabled

EN
EN A Y
A Y
0 0 Z
0 1 Z
1 0 0 EN

1 1 1 Y
A

EN
 Nonrestoring Tristate
• Transmission gate acts as tristate buffer
–Only two transistors
–But nonrestoring EN
• Noise on A is passed on to Y
A Y

EN
 Tristate Inverter
• Tristate inverter produces restored output
–Violates conduction complement rule
–Because we want a Z output

A A
A
EN
Y Y Y
EN

EN = 0 EN = 1
Y = 'Z' Y=A
 Multiplexers
• 2:1 multiplexer chooses between two inputs

S
S D1 D0 Y
0 X 0 0 D0 0
0 X 1 1 Y
D1 1
1 0 X 0
1 1 X 1
 Gate-Level Mux Design
• Y  SD1  SD0 (too many transistors)
• How many transistors are needed? 20

D1
S Y
D0

D1 4 2
S 4 2 Y
D0 4 2
2
 Transmission Gate Mux
• Mux uses two transmission gates
–Only 4 transistors or 6 transistors if S is not available.

D0
S Y
D1

S
 Inverting Mux
• Inverting multiplexer
–Use compound AOI22
–Or pair of tristate inverters
–Essentially the same thing
• Noninverting multiplexer adds an inverter

D0 S D0 D1 S
S D1 S S
Y Y D0 0
S S S S Y
D1 1
 4:1 Multiplexer
• 4:1 mux chooses one of 4 inputs using two
selects
–Two levels of 2:1 muxes S1S0 S1S0 S1S0 S1S0

–Or four tristates

D0
S0 S1

D0 0
D1
D1 1
0
Y Y
1
D2 0 D2
D3 1

D3
 D Latch
• When CLK = 1, latch is transparent
–D flows through to Q like a buffer
• When CLK = 0, the latch is opaque
–Q holds its old value independent of D
• transparent latch or level-sensitive latch

CLK CLK

D
Latch

D Q
Q
 D Latch Design
• Multiplexer chooses D or old Q

CLK
CLK
D Q Q
1
Q D Q
0
CLK CLK

CLK
 D Latch Operation
Q Q
D Q D Q

CLK = 1 CLK = 0

CLK

Q
 D Flip-flop
• When CLK rises, D is copied to Q
• At all other times, Q holds its value
• positive edge-triggered flip-flop, master-slave
flip-flop
CLK
CLK
D
Flop

D Q
Q
 D Flip-flop Design
• Built from master and slave D latches

CLK CLK
CLK QM
D Q
CLK CLK CLK CLK
CLK
Latch

Latch

QM
D Q
CLK CLK
 D Flip-flop Operation
QM Q
D

CLK = 0

QM
D Q

CLK = 1

CLK

Q
 Lecture Summary
• MOS transistors are stacks of gate, oxide, silicon.
• They act as electrically controlled switches.
• Logic gates can be built out of these switches.
• Transmission gate acts as tristate buffer.
• Latches and Flip-flops can be built using
inverters and transmission gates.
 References
• CMOS VLSI Design: A Circuit and Systems Perspective
Neil H. E. Weste and David Harris