Registers and Counters

Module: 4
Flip-Flops Applications: Registers, binary ripple counters, synchronous binary counters, Counters based
on shift registers, Design of a synchronous counter, Design of a synchronous mod-n counter using clocked
T, JK, D and SR flip-flops.

Registers

A single memory element or flip flop can store a single bit of information(data). Thus, a group
of memory elements (flip flops) working in a cascaded manner can store multiple bits and is
called a register. Thus, registers are a group of flip flops used to store data.

A 4 bit register can store binary information in the range of 0000 to 1111. Four bits of data
is known as a nibble of data.

The data stored in the register is called as the state of the register.

Thus, a n bit register consist of n flip flops.

Shift registers
These are capable of moving or shifting the data stored in their flip flops in either direction.
These different types of movement possible in registers is as shown below:

Shift registers are classified based on the direction of data movement. The different types of
shift registers are as follows:
1. Serial In Serial Out (SISO)
a. Right shift
b. Left shift
c. Bidirectional shift
2. Serial In Parallel Out (SIPO)
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3. Parallel In Parallel Out (PIPO)

4. Parallel In Serial Out (PISO)

Serial In Serial Out

Here data is fed one bit at a time and data is seen on the output one bit at a time. There are
two types of SISO registers based on the direction of movement of data. They are
a) shift left and
b) shift right

SISO (Shift left)

Here data is fed in from the right end one bit at a time and the data is seen on the output
from the left side.

Initially all flip flops are cleared to 0. Thereafter the data is fed in from the left side through
D flip flop.

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Clock pulse 𝐷𝑖𝑛 𝑄𝐷 𝑄𝑐 𝑄𝐵 𝑄𝐴 (𝐷𝑜𝑢𝑡 )

Initially 0 0 0 0 0
1𝑠𝑡 1 1 0 0 0
2𝑛𝑑 1 1 1 0 0
3𝑟𝑑 1 1 1 1 0
4𝑡ℎ 1 1 1 1 1 (first bit out)
5𝑡ℎ x x 1 1 1(second bit out)
6𝑡ℎ x x x 1 1(third bit out)
7𝑡ℎ x x x x 1 (fourth bit out)

Thus, it is seen we need four clock pulses to feed the data. On the fourth pulse the first bit
is seen on the output. To see the remaining three bits three more clock pulses are required.

SISO (Shift right)

Here data is fed in from the right end one bit at a time and the data is seen on the output
from the left side.

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Clock pulse 𝐷𝑖𝑛 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷 (𝐷𝑜𝑢𝑡 )

Initially 0 0 0 0 0
1𝑠𝑡 1 1 0 0 0
2𝑛𝑑 1 1 1 0 0
3𝑟𝑑 1 1 1 1 0
4𝑡ℎ 1 1 1 1 1 (first bit out)
5𝑡ℎ x x 1 1 1(second bit out)
6𝑡ℎ x x x 1 1(third bit out)
7𝑡ℎ x x x x 1 (fourth bit out)

Here the data is fed from the left end one bit at a time. A four bit shift register requires 4
clock pulses to feed the data. On the fourth pulse the first bit can be seen on the output.
Another three more clock pulses are required to see the entire data on the output.

Parallel in Parallel out (PIPO)

Here the n bits of data is fed in simultaneously and the four bits are seen on the output at
the same time.

Clock pulse 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷
Initially 0 0 0 0
1𝑠𝑡 A B C D

The data comes in through the four inputs and is seen on the output when the active edge
of the clock pulse is applied. Since data comes in together and is seen on the output at the
same time it is known as parallel in parallel out shift register.

Serial In Parallel Out (SIPO)

Here data is fed in one bit at a time through a single input. Therefore for a 4 bit register
four clock pulses will be required to feed the data in; on the fourth pulse the data is seen
on the output.

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Clock pulse 𝐷𝑎𝑡𝑎 𝑖𝑛𝑝𝑢𝑡 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷

Initially 0 0 0 0 0
1𝑠𝑡 1 1 0 0 0
2𝑛𝑑 1 1 1 0 0
3𝑟𝑑 1 1 1 1 0
4𝑡ℎ 1 1 1 1 1

Parallel In Serial Out (PISO)

Here data is fed in fed in simultaneously but there is a single output (serial out) to see the
data. Since two types of operations are performed there is an additional control signal
̅̅̅̅̅̅̅̅). When this control is in logic 1 gates 𝐺4 , 𝐺5 and 𝐺6 are active and data is
(SHIFT/𝐿𝑂𝐴𝐷
̅̅̅̅̅̅̅̅ ) is in logic 0 gates 𝐺1 , 𝐺2 and 𝐺3 are active and data is
shifted serially. When (SHIFT/𝐿𝑂𝐴𝐷
loaded parallely using inputs ABCD.

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CP ̅̅̅̅̅̅̅̅
SHIFT/𝐿𝑂𝐴𝐷 A B C D 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷
(𝑆𝑒𝑟𝑖𝑎𝑙 𝑑𝑎𝑡𝑎 𝑜𝑢𝑡)
1st 0 A B C D A B C D
pulse
2nd 1 x x x x x A B C
pulse
3rd 1 x x x x x x A B
pulse
4th 1 x x x x x x x A
pulse

Bidirectional Shift Register

This register is capable of shifting the data either to the left or right. In order to perform the
̅̅̅̅̅̅ is used . When this signal Right/𝐿𝑒𝑓𝑡
shifting in both direction an additional input Right/𝐿𝑒𝑓𝑡 ̅̅̅̅̅̅
= 1 gates 𝐺1 𝐺2 𝐺3 𝐺4 is open and data is loaded in through the left side (Serial data in for
right shift) and for every clock pulse the data is shifted to the right. Thus four clock pulses
are required to load the four bits of data, on the fourth pulse the first bit (LSB) of data will
be seen on the 𝑄𝐷 . Another three more clock pulses will be required to see the remaining 3
bits of data.
̅̅̅̅̅̅ = 0 gates 𝐺5 𝐺6 𝐺7 𝐺8 is open and data is loaded in through the
Similarly when Right/𝐿𝑒𝑓𝑡
right side (Serial data in for left shift) and for every clock pulse the data is shifted to the left.
Thus, four clock pulses are required to load the four bits of data, on the fourth pulse the
first bit (LSB) of data will be seen on the 𝑄𝐴 . Another three more clock pulses will be required
to see the remaining 3 bits of data.

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Bidirectional Shift with Parallel Load

In this case the circuit is capable of doing 3 different operations and hence two additional
signals (𝑆𝐿1 𝑆𝐿0 ) are required. Based on the values of the 𝑆𝐿1 𝑆𝐿0 the 2:4 decoder will give
an active high output on any one of the four lines of the decoder. Thus the corresponding
gates will open up
𝑆𝐿1 𝑆𝐿0 Data Input Output Operation
0 0 Parallel input 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷 PIPO
0 1 Serial data in for 𝑄𝐴 Shift left
left shift
1 0 Serial data in for 𝑄𝐷 Shift right
right shift

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Universal Shift Register

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Questions based on shift registers

1. Incorporate a synchronous clear facility in the 4 bit serial in serial out unidirectional
shift register configured using positive edge triggered D flip flops
2. Design a 4 bit register using positive edge triggered D flip flops to operate as
shown in the table
Mode Selection Register
𝐴1 𝐴0 operation
0 0 Hold
Synchronous
0 1
clear
Complement
1 0
Contents
Circular shift
1 1
register

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Counters
• Is a cascade of flip flops configured to output a specific sequence on
application of a clock.
• Each output of the sequence is dependent on the contents of the flip flops
and is called the state of the counter.
• Modulus of a counter is the total number of states of the counter. A counter
with m states is called a MOD m counter.
• A state diagram is used to represent the operation of a counter

Asynchronous Counters
2 bit ripple up counter

• This consist of a series connection of flip flops connected in such a way that the
output of one flip flop becomes the clock for the next flip flop.
• Since the flip flops are not controlled by the same clock signal this circuit is known
as asynchronous counter
• The counter increments for every active edge of the clock signal. Hence this is called
an up Counter

CP 𝑄𝐴 𝑄𝐵
 0 0
 0 1
 1 0
 1 1

For every active edge of the clock pulse (CP) the output of flip flop (A) i.e 𝑄𝐴 will
continuously toggle. The 𝑄𝐴 output becomes the clock for the B flip flop.

Asynchronous Down Counter

• In this case the counter output decrements for every active edge of the clock pulse.
• The clock signal that is to be counted is given to the flip flop generating the LSB.
• The clock to the remaining flip flops is the output from the previous flip flops

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• The J and K inputs of all the flip flops are tied high enabling it to work as toggle flip
flops.

Asynchronous Up/Down counter

To design an up/down counter, an additional control input (mode control =M) is required.
When M=1 the counter will work as an up counter, when M=0 it will work as a down
counter.

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Decoding gates

This logic helps in detecting a particular value on the output of the counter. The simplest
decoding logic involves the use of decoding gates that gives an output high when the
particular value is generated by the counter

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Asynchronous Decade Counter

Problems associated with ripple counters

Each flip has a finite propagation delay of say 𝑡𝑝 . Due to this the output of flip flop A
triggers flip flop B after a delay of 𝑡𝑝 after the negative transition of A. Similarly C flip flop
receives the active edge of the clock pulse after 2𝑡𝑝 compared to the external pulse CP.

Observe the waveform at the point when the counter progresses from state 7 to state 0.
Thus at point X, A goes low, however due to the delay time B flip flop does not go low
until point Y. Thus between points X and Y we have C=1, B=1 and A=1. This undesirable
output is known as glitch.

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Synchronous Up Counter

2bit synchronous up counter

• In this case all the flip flops work using the same the clock pulse, CP. Hence all the
flip flops are triggered at the same time.
• The toggling of the flip flops are controlled by the inputs to J and K.

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3-bit synchronous up counter

The figure below shows the logic diagram and the timing diagram for a synchronous
counter

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Here the flip flop A is wired to work as a simple toggle flip flop for every active edge of
the clock pulse the A flip flop continuously toggles. The output of A flip flop 𝑄𝐴 becomes
the clock for B flip flop since B flip flop should toggle when 𝑄𝐴 = 1. Similarly observing
the pattern of change for the C flip flop it is seen that C flip flop should toggle when both
𝑄𝐴 = 𝑎𝑛𝑑 𝑄𝐵 = 1, hence the output of both A and B is given as input to C flip flop.

Four bit synchronous up counter

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Synchronous down counter

Synchronous up/down counter

To perform two different operations we use an additional signal the mode control, M.
When M=1, gates 1 and 2 will pass the Q as the J and K input to the next flip thus
enabling the circuit to count up. When M=0 gates 3 and 4 are open allowing the 𝑄̅ to
reach the J and K of next flip flop thus enabling the circuit to count down.

Difference between synchronous and asynchronous counters

Asynchronous counter Synchronous counter

The clock that is being counted is given All the flip flops in the circuit work using
only to the first flip flop. The clock for the the same clock
remaining flip flop is the output of the
previous flip flop.
Logic circuit is simple even for circuits that Design involves complex logic circuit as
has more number of states the number of states increases
The clock takes a long time to reach the Since the clock is given simultaneously to
last flip flop due to the propagation delay all the flip flops there is no problems due
of each of the flip flops. to the propagation delay. Hence these
circuits are much more preferred when the
number of states increases

Modulus n counter

A counter that has n states is called a modulo n counter. In case of a binary up/down
counter this can be achieved by using a decoding logic to detect the immediate next
unused state and using this to reset the circuit to the initial state.

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Design a Mod 10 synchronous counter (Decade counter)

This is a synchronous four bit counter. The counter works as synchronous up counter and
counts from 0000 to 1001. The decoding logic detects 1010 and is used to reset the
counter.

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Counters based on Shift Registers

Ring Counter

Here we start by loading a value wherein only one bit is different. This can be done by
using the asynchronous inputs of the flip flop namely preset (𝑃𝑅 ̅̅̅̅) and clear (𝐶𝐿𝑅
̅̅̅̅̅̅ ). When an
active low signal is asserted on the reset line the circuit gets loaded with the value 1000.
For active edge of the clock pulse the 1 keeps moving from one flip flop to the other.
Since the output of the last flip flop is fed as the input to the first flip flop, the bits onces
loaded moves through the circuit in a circular manner. Hence this circuit is known as ring
counter. The count of the clock pulse is equal to the count of the flip flop that has the ‘1’
on its output.
Thus on the first pulse ‘1’ is on the output of the first flipflop. On the second pulse ‘1’ is
on the output of the second flipflop. On the third pulse ‘1’ is on the output of the third
flipflop. On the fourth pulse ‘1’ is on the output of the fourth flipflop.
The limitation of this circuit is that using four flip flops we can count only 4 pulses.

Note: Draw the timing diagram

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Johnsons counter or switched tail ring counter or Twisted ring counter

In this counter circuit the 𝑄̅ output of the last flip flop is fed as the input to the first flip
flop. Initially the circuit is loaded with the value 0000 by asserting asynchronous clear
inputs of the flip flops. This circuit is capable of counting 8 clock pulses. The pattern of
values displayed on the output of the counter is as follows. In order to identify the count of
the clock pulse a set of decoding gates are used on the output.

Decoding
CP 𝑄𝐴 𝑄𝐵 𝑄𝐶 𝑄𝐷
logic
0 0 0 0 0 𝑄̅𝐴 𝑄̅𝐵
1 1 0 0 0 𝑄𝐴 𝑄̅𝐵
2 1 1 0 0 𝑄𝐵 𝑄̅𝐶
3 1 1 1 0 𝑄𝐶 𝑄̅𝐷
4 1 1 1 1 𝑄𝐴 𝑄𝐷
5 0 1 1 1 𝑄̅𝐴 𝑄𝐵
6 0 0 1 1 𝑄̅𝐵 𝑄𝐶
7 0 0 0 1 𝑄̅𝐶 𝑄𝐷

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Thus, a Johnsons counter that has the output of last flip flop feedback as the input counts
2n clock pulses or it is a Mod 2n counter; where n is the number of flip flops used.

Ques: Design a Mod 7 Johnsons counter

In this case the 𝑄̅ of the last two flip flops are fed back as the input to the first flip. In this
type of counter if there are n flip flops there will be 2n-1 states (2n-1 different values)
hence this circuit is known as Mod 2n-1 counter. For example if there are 4 flip flops there
will be 7 states and hence this is known as Mod 7 Johnsons counter.

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Design of synchronous counter

Steps involved in the design of synchronous counter

1. Obtain the transition table from the given circuit information

2. Determine the required number of flip flops
a. Count the total number of states and round it of to the nearest higher 2𝑛 .
b. Number of flip flops required will be n
3. Choose the type of flip flop based on the required pattern of change
4. From the transition table derive the circuit excitation table
5. Use K map or any other simplification method to derive the flip flop input equation
6. Draw the logic diagram

Transition Table

The table that represents the relationship between the present states and the next states
of the flip flop is known as transition table.

Clock Present State Next State

𝐶𝑛 𝐵𝑛 𝐴𝑛 𝐶𝑛+1 𝐵𝑛+1 𝐴𝑛+1
 0 0 0 0 0 1
 0 0 1 0 1 0
 0 1 0 1 0 0
 1 0 0 1 1 0
 1 1 0 1 1 1
 1 1 1 0 0 0

Flip Flop Excitation Table

It is the table that shows the inputs to be given to a particular flip flop to cause a
particular change of state in the flip flop.

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RS flip flop

Truth Table Excitation Table

R S 𝑄𝑛 𝑄𝑛+1 𝑄𝑛 𝑄𝑛+1 R S
0 0 0 0 0 0 x 0
0 0 1 1 0 1 0 1
0 1 0 1 1 0 1 0
0 1 1 1 1 1 0 x
1 0 0 0
1 0 1 0
1 1 0 *
1 1 1 *

D flip flop

Truth Table Excitation Table

D 𝑄𝑛 𝑄𝑛+1 𝑄𝑛 𝑄𝑛+1 D
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 0
1 1 1 1 1 1

JK flip flop
Truth Table Excitation Table
J K 𝑄𝑛 𝑄𝑛+1 𝑄𝑛 𝑄𝑛+1 J K
0 0 0 0 0 0 0 x
0 0 1 1 0 1 1 x
0 1 0 0 1 0 x 1
0 1 1 0 1 1 x 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

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T flip flop

Truth Table Excitation Table

T 𝑄𝑛 𝑄𝑛+1 𝑄𝑛 𝑄𝑛+1 T
0 0 0 0 0 0
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 1 1 0

Design a MOD 6 synchronous counter using JK flip flop

Step 1: Total number of states – 6

Number of flip flops required = 3 (Nearest 2𝑛 𝑣𝑎𝑙𝑢𝑒)

Step 2: State diagram

0
0
1 0
0 0

1 0
0 1
0
1
Step 3: Flip Flop Excitation Table

Excitation Table
𝑄𝑛 𝑄𝑛+1 J K
0 0 0 x
0 1 1 x
1 0 x 1
1 1 x 0

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Step 4: Transition Table

Step 5: Use K map to simplify and obtain the flip flop input equation

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Step 6: Draw the logic diagram

Question: Design a synchronous counter using clocked D flip flop

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Question: Design a synchronous counter using clocked RS flip flop

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Question: Design a synchronous counter using clocked T flip flop

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