Sequential Circuits

Digital System Design

Module 3
Syllabus:
 Flip-Flops:
 Basic Bistable elements, Latches, Timing considerations, The master-slave flip-
flops (pulse triggered flip-flops): SR flip-flops, JK flip-flops, Edge triggered flip-
flops, Characteristic equations.
Sequential Circuits
Is a circuit in which the output at any given time depends not only on the inputs at that
instant but also on the previous output. Thus, sequential circuits have a memory element
associated with it. These memory elements store the binary information in the circuit.
Examples: flip flops, registers, counters, serial adder e.t.c.

The operation of sequential circuit is expressed in terms of state. The state of a sequential
circuit refers to the value of the signals associated with the sequential circuit at any given
instance of time. Thus, the value stored in the memory elements at any given instance is
known as the state of the sequential circuit.
There are two basic types of sequential circuits – synchronous and asynchronous sequential
circuits.
Synchronous sequential circuits are controlled by a master clock. Here the inputs are
sampled at discrete instances of these clock pulses. Thus, in these circuits changes in input
signal is transmitted to the output only at discrete instance of time.
Asynchronous sequential circuits are those which the changes in output signal changes as
soon as the inputs change. These circuits do not have a master clock signal.
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 Sequential Circuits

The basic memory element of a sequential circuit is the flip flops. A flip flop can store a 1 or
0. This is referred to as the state of the flip flop. Thus, they have two stable states.

Bistable elements
The central element of a flip flop is the bistable element. The simplest bistable consist of
two inverters. This circuit can indefinitely store 1 or 0. Hence the name bistable element.

The circuit has 2 outputs which are complementary in nature ( Q and 𝑄 ̅ or Q’). This circuit
does not have any inputs. Hence the values available at the outputs of the inverter on power
up remains until power is removed. Assume on power up
 Case1:
 if Q=0 then Q’ will be 1
 The circuit will indefinitely hold these values until powered up again
 Case2:
 if Q=1 then Q’ will be 0
 The circuit will indefinitely hold these values until powered up again
Thus the circuit can reliably store the two values and hence called a bistable element. The 1
or 0 stored in the bistable element is known as state of the element. When Q=1 , the circuit
is said to be in the SET state and when Q=0 the circuit is said to be in the RESET state.
Besides the two stable states, the circuit can also be in the metastable state. This occurs
when the output signals are about halfway between logic 0 and logic 1. However, a slight
disturbance in any of the internal signals will cause the circuit to leave the metastable state
and settle at either 1 or 0.

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 Sequential Circuits

For the circuit to be useful, we should be able to change the outputs. This is achieved by
adding additional inputs and replacing the NOT gates. Thus, a flip flop is a bistable element
with outputs that remains in a particular state until power is switched off or inputs changes.
Flip flops have two types of inputs – synchronous and asynchronous inputs. Synchronous
inputs cause changes in the state of the flip flop only when a control signal called as enable
or clock comes into action. Asynchronous or direct inputs causes immediate change in the
state of the flip flop.
Latches
This is a class of flip flops whose input changes causes immediate change in the output of
the flip flops although some of them has a control signal called enable or clock.
SR Latch

Logic Circuit

Logic Symbol

It consist of cross coupled NOR gates. It has two inputs, S and R referred to as SET and RESET inputs and
gives two outputs Q and Q’ (𝑄̅ ). The output of the latch before the input changes is denoted as
𝑄𝑝𝑟𝑒𝑠𝑒𝑛𝑡 𝑜𝑟 𝑄. The outputs of the latch changes when the inputs changes. The new outputs of the latch
is denoted as 𝑄𝑛𝑒𝑥𝑡 𝑜𝑟 𝑄 + and 𝑄𝑛𝑒𝑥𝑡
′
𝑜𝑟 𝑄̅ + 𝑜𝑟 𝑄̅𝑛𝑒𝑥𝑡 .

Case 1:

Assume S=0, R=0 , Q =0 and 𝑄̅ =1; then 𝑄 + = 0 𝑎𝑛𝑑 𝑄̅ + = 1 , i.e. the latch holds state.

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 Sequential Circuits

̅
Q

Case 2:

Assume S=0, R=0 , Q =1 and 𝑄̅ =0; then 𝑄 + = 1 𝑎𝑛𝑑 𝑄̅ + = 0 , i.e. the latch holds state.

Case 3:
Assume S=0, R=1 , Q =0 and 𝑄̅ =1; then 𝑄 + = 0 𝑎𝑛𝑑 𝑄̅ + = 1

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 Sequential Circuits

Case 4: Assume S=0, R=1 , Q =1 and 𝑄̅ =0; then 𝑄 + = 0 𝑎𝑛𝑑 𝑄̅ + = 1

Case 5: Assume S=1, R=0 , Q =0 and 𝑄̅ =1; then 𝑄 + = 1 𝑎𝑛𝑑 𝑄̅ + = 0

Case 6: Assume S=1, R=0 , Q =1 and 𝑄̅ =0; then 𝑄 + = 1 𝑎𝑛𝑑 𝑄̅ + = 0

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 Sequential Circuits

Case 7: Assume S=1, R=1 , Q =0 and 𝑄̅ =1; then 𝑄 + = 0∗ 𝑎𝑛𝑑 𝑄̅ + = 0∗

Case 8: Assume S=1, R=1 , Q =1 and 𝑄̅ =0; then 𝑄 + = 0∗ 𝑎𝑛𝑑 𝑄̅ + = 0∗

S R Q 𝑄+ 𝑄̅ +
0 0 0 0 1 Holds state
0 0 1 1 0
0 1 0 0 1 Reset state
0 1 1 0 1
1 0 0 1 0 Set state
1 0 1 1 0
1 1 0 0∗ 0∗ Indeterminate/forbidden
1 1 1 0∗ 0∗ state

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 Sequential Circuits

Application of SR latch – As switch debouncer

One of the common problems associated with switches is the contact bounce. With the center
contact of the switch in its lower position, voltage at terminal B is +V volts, while voltage at
terminal A is zero. Now if the center contact is moved from its lower position to upper
position then voltage at B first becomes zero followed by voltage at A becoming +V volts
when the contact reaches the upper terminal. However, because of contact bounce, the
switch bounces a few times before settling at the terminals causing the voltage to swing
between +V volts and zero.
A simple application of the SR latch is to eliminate the effect of contact bounce. A switch
debouncer circuit consist of a SR latch connected as shown. Assume +V volts corresponds
to logic 1 and zero volts corresponds to logic 0. Two pull down resistors connected to
terminals A and B ensures that the terminals are at logic zero when the contact is broken at
termnals A or B. Thus when the center contact moves from its lower position (terminal B) to
terminal A the output of the SR latch remains in its reset state until the center contact reaches

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 Sequential Circuits

terminal A at which time the Q output of the SR latch becomes 1. If the switch opens now,
as a result of the contact bounce, S=0 and R=0 hence the output of the SR latch remains
unchanged. Thus, eliminating the effect of contact bounce. Similarly the contact bounce is
eliminated when the switch moves from its upper position (terminal A ) to lower position
(terminal B).
SR latch using NAND gates

In this case the latch is implemented using NAND gates. The gate that receives the S input
generates the Q output and the gate that receives the R input generates the 𝑄̅ output.
Case 1: When 𝑆̅ =0, 𝑅̅ =0 , Q=0, 𝑄̅ = 1, then 𝑄 + = 1∗ and Q
̅ + = 1∗

Case 2: 𝑆̅ = 0, 𝑅̅ =0, Q=1, 𝑄̅ =0, then 𝑄 + = 1∗ and Q

̅ + = 1∗

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Case 3: 𝑆̅ =0, 𝑅̅ =1 , Q=0, 𝑄̅ = 1, then 𝑄 + = 1and Q

̅+ = 0

Case 4: 𝑆̅ = 0, 𝑅̅ =1, Q=1, 𝑄̅ =0, then 𝑄 + = 1and Q

̅+ = 0

Case 5: 𝑆̅ =1, 𝑅̅ =0 , Q=0, 𝑄̅ = 1, then 𝑄+ = 0 and Q

̅+ = 1

Case 6: 𝑆̅ = 1, 𝑅̅ =0, Q=1, 𝑄̅ =0, then 𝑄 + = 0 and Q

̅+ = 1

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 Sequential Circuits

̅ =1, 𝑹
Case 7: 𝑺 ̅ =1 , Q= 0, 𝑸
̅ = 𝟏, then 𝑸+ = 𝟎 and 𝐐
̅+ = 𝟏

̅ = 1, 𝑹
Case 8: 𝑺 ̅ =1, Q=1, 𝑸
̅ =0, then 𝑸+ = 1 and 𝐐
̅+ = 𝟎

̅
𝑺 ̅
𝑹 Q 𝑸+ ̅+
𝑸

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 Sequential Circuits

0 0 0 𝟏∗ 𝟏∗ Forbidden
state or
0 0 1 𝟏∗ 𝟏∗ indeterminate
0 1 0 1 0 Set state
0 1 1 1 0
1 0 0 0 1 Reset state

1 0 1 0 1
1 1 0 𝟎 𝟏 No change

1 1 1 𝟏 𝟎

̅
𝑺 ̅
𝑹 Q 𝑸+ ̅+
𝑸

Forbidden
0 0 x 𝟏 ∗
𝟏 ∗ state or
indeterminate

0 1 x 1 0 Set state

Reset state
1 0 x 0 1

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 Sequential Circuits

1 1 0 𝟎 𝟏 No change

1 1 1 𝟏 𝟎

NAND based SR latch

To overcome the inversion of output in the truth table NAND base SR latches were
implemented as

S Q

R 𝑄̅

S R Q 𝑄+ 𝑄̅ +

0 0 0 0 1 No change

0 0 1 1 0

0 1 0 0 1 reset state

0 1 1 0 1

1 0 0 1 0 Set state

1 0 1 1 0

1 1 0 𝟏∗ 𝟏∗ Forbidden
state or
1 1 1 indeterminate
𝟏∗ 𝟏∗

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Gated Latches
• SR latch is sensitive to changes in input
• as soon as S or R is asserted the output changes.
• To avoid the change in output due to change in input a signal called enable is added.
• Such latches are called SR latch with enable or gated SR latch
• There are two types of enable signals
• Allows the change in S and R values to be transmitted to the output when
E=1 (active high enable)
• Allows the change in S and R values to be transmitted to the output when
E=0 (active low enable)
• In this case an additional control signal called enable is present
• Changes in S and R inputs are allowed to pass through gates 1 and 2 only when E=1
• Hence this circuit is referred to as active high enable SR latch
• When E=0, the output of gates 1 and 2 is logic 1 and hence the latch retains its
previous output

Logic Circuit

Logic Symbol

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 Sequential Circuits

When enable, E is in logic 0 changes in S and R input are not detected and hence the output remains
unchanged

The latch starts working when E=1 ,

̅ = 𝟏, then 𝑸+= 𝟎 and 𝐐
Case 1: When E=1 and 𝑺=0, R = 0 , Q = 0, 𝑸 ̅+ = 𝟏

̅ = 𝟎, then 𝑸+= 𝟏 and 𝐐

Case 2: When E=1 and 𝑺=0, R = 0 , Q = 1, 𝑸 ̅+ = 𝟎

̅ = 𝟏, then 𝑸+ = 𝟎 and 𝐐
Case 3: When E=1 and 𝑺=0, R = 1, Q = 0, 𝑸 ̅+ = 𝟏

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 Sequential Circuits

̅ = 𝟎, then 𝑸+ = 𝟎 and 𝐐
Case 4: When E=1 and 𝑺=0, R = 1, Q = 1, 𝑸 ̅+ = 𝟏

̅ = 𝟏, then 𝑸+ = 𝟏 and 𝐐
Case 5: When E=1 and 𝑺=1, R = 0, Q = 0, 𝑸 ̅+ = 𝟎

̅ = 𝟎, then 𝑸+ = 𝟏 and 𝐐
Case 6: When E=1 and 𝑺=1, R = 0, Q = 1, 𝑸 ̅+ = 𝟎

̅ = 𝟏, then 𝑸+ = 𝟏 ∗ and 𝐐
Case 7: When E=1 and 𝑺=1, R = 1, Q = 0, 𝑸 ̅+ = 𝟏 ∗

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 Sequential Circuits

̅ = 𝟎, then 𝑸+ = 𝟏 ∗ and 𝐐
Case 8: When E=1 and 𝑺=1, R = 1, Q = 1, 𝑸 ̅+ = 𝟏 ∗

E S R Q 𝑸+ ̅+
𝑸

0 x x 0 0 1 Unchanged

0 x x 1 1 0

1 0 0 0 0 1 Holds state

1 0 0 1 1 0

1 0 1 0 0 1 reset state

1 0 1 1 0 1

1 1 0 0 1 0 Set state

1 1 0 1 1 0

1 1 1 0 𝟏∗ 𝟏∗ Forbidden
state or
1 1 1 1 𝟏∗ 𝟏∗ indeterminate

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Gated D Latch

One of the major disadvantages of the SR latch is that when S=R =1 the latch goes into forbidden state.

E D Q 𝑸+ ̅+
𝑸

0 x 0 0 1 Unchanged

0 x 1 1 0

1 0 0 0 1 reset state

1 0 1 0 1

1 1 0 1 0 Set state

1 1 1 1 0

Gated JK latch

In J K latch the problem of forbidden state has been overcome by feeding the output back to the input.

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 Sequential Circuits

E J K Q 𝑸+ ̅+
𝑸

0 x x 0 0 1 Unchanged

0 x x 1 1 0

1 0 0 0 0 1 Holds state

1 0 0 1 1 0

1 0 1 0 0 1 reset state

1 0 1 1 0 1

1 1 0 0 1 0 Set state

1 1 0 1 1 0

1 1 1 0 𝟏 𝟎 Toggle

1 1 1 1 𝟎 𝟏

It was seen when the clock pulse, J=K=1 and C is in the ON state for a time greater than the propagation
delay of the latch the output continuously toggles between logic 1 and logic 0 without any change in the
input. This is known as race around condition in flip flops. (as indicated by a, b, c, d,e). The solution to
this problem was to create edge triggered circuits or pulse triggered (known as flip flops)

Clock
The clock signal is generally a rectangular pulse train or square wave. The clock signal is
distributed to all parts of the system, and most (if not all) of the system outputs can change
state only when the clock makes a transition. When the clock changes from a 0 to a 1, this
is called the positive edge or rising edge; when the clock goes from 1 to 0, this is the
negative edge or trailing edge or falling edge. Most digital systems are principally
synchronous (although there are always some asynchronous parts), since synchronous
circuits are easier to design and troubleshoot. They are easier to troubleshoot because the
circuit outputs can change only at specific instants of time.
In other words, almost everything is synchronized to the clock-signal transitions. The
synchronizing action of the clock signals is accomplished through the use of clocked flipflops
that are designed to change states on one or the other of the clock’s transitions. There are

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 Sequential Circuits

types of clocked Flip-flops that are used in a wide range of applications. There are some
principal ideas that are common to all of them.
• Clocked Flip-Flops have a clock input that is typically labeled CLK, CK or CP.
Triggering circuits

In case of latches with enable signal (gated latches), any change in the input signal gets
transmitted to the output when the enable is in its active logic. This was not desirable for
certain circuits. In order to ensure that the changes in the input is transmitted to the output
at precise instance of time, master slave (pulse triggered) flip flops or edge triggered flip
flops were used.

There are different types of enable signals that are used to transfer changes in input to the
output side.
1. High Level triggering
Here the changes in input are transmitted to the output when the control signal is in
logic 1 state

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2. Low Level triggering

Here the changes in input are transmitted to the output when the control signal is in
logic 0 state

3. Rising edge or Positive edge triggering

Here the changes in the input are transmitted to the output when the control signal
(clock) transitions from logic 0 to logic 1

4. Falling edge or Negative edge triggering

Here the changes in the input are transmitted to the output when the control signal
(clock) transitions from logic 0 to logic 1

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Timing Considerations
The function tables of the various latches specify the state outputs obtain as a result of
changes in the input signals. However, the responses of these circuits are not immediate are
affected by the propagation delay of the gates. A convenient way of representing the
behavior of these circuits is using Timing Diagrams.
Timing Diagram is a graph that depicts the input and output transitions of the flip flops as
a function of time.

Propagation Delay is the time between an input signal and output signal measured at 50%
points. There are two types of propagation delay: 𝑡𝑝𝐿𝐻 , delay as the output switches from
low to high and 𝑡𝑝𝐻𝐿 ,the delay as output switches from high to low.

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Another specification associated with the working of the latches is minimum pulse width.
This is the minimum amount of time a signal must be applied in order to produce a desired
result. Failure to satisfy this constraint may cause the latch to not cause the intended change
or the latch may even enter metastable state. Thus, the output of the latch becomes
unpredictable.

In the above timing diagram, it is seen at time 𝑡10 when both S=R=1 both Q and 𝑄̅ =0. At
time 𝑡15 when both S and R becomes 1 at the same instance of time the output becomes
unpredictable i.e. it may become 0 or 1 or output of the latch may go into the metastable
state.

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Setup time, is the minimum time that the data on the excitation inputs to a flip flop device
must remain stable prior to the arrival of the clock edge that triggers the device so that the
inputs are reliably clocked by the flip flops.
Hold time, is the minimum time that the data on the excitation inputs of the flip flops should
remain stable after the clock edge has occurred to ensure that the data is reliably clocked.

Master Slave SR Flip Flops

Major drawback of latches is that the output changes immediately as the input changes. This
property of the latches is known as transparency of the latches.

Master slave flip flops has a master latch and a slave latch that is cascaded together. The
master registers the data on one logic of the control signal. The slave transfers the output
of the master on the opposite logic of the control signal.

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Flip flop action during the control signal

The transition of the control signal from low to high is known as rising, leading or positive edge of
the control signal. The transition of the control signal from high to low is called falling, trailing or
negative edge of the control signal.
In the above circuit diagram master is enabled when C=1 at this time slave will inactive since C=0.
When C=1, the output of the master (𝑄𝑀 𝑎𝑛𝑑 𝑄̅𝑀 ) will change depending on S and R value. When C
becomes 0 master will become inactive and the slave will come to active state. The pulse symbol in
C column indicates that the master is active when the control signal is high and that the state of the
master is transferred to the output of the slave at the end of the pulse period. When the slave
wakeups it will copy the output the output of the master. Thus, we can see the output
(𝑄𝑠 𝑜𝑟 𝑄 𝑎𝑛𝑑 𝑄̅𝑠 𝑜𝑟 𝑄̅ ). Thus, the output of the master slave flip flop will be seen when C changes
from 1 to 0 i.e. during the falling edge of C. Since the behavior of the master slave flip flops is
dependent on the rising and falling edges of the control signals as well as the period of time in which
the control signal is high they are also referred to as pulse triggered flip flops.
Inputs Outputs
S R C 𝑄+ 𝑄̅ +
0 0 Q 𝑄̅
0 1 0 1
1 0 1 0
1 1 indeterminate indeterminate
x x 0 Q 𝑄̅

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Logic Symbols
C S R 𝑄𝑛 𝑄𝑀+1 𝑄𝑛+1
1 0 0 0 0 NC
0 0 0 0 NC 0
1 0 0 1 1 NC
0 0 0 1 NC 1
1 0 1 0 0 NC
0 0 1 0 NC 0
1 0 1 1 0 NC
0 0 1 1 NC 0
1 1 0 0 1 NC
0 1 0 0 NC 1
1 1 0 1 1 NC
0 1 0 1 NC 1
1 1 1 0 1* NC
0 1 1 0 NC 1*
1 1 1 1 1* NC
0 1 1 1 NC 1*

S
SS 𝑄𝑀 P a g e 25 | 35
S
𝑄𝑆
𝑄

C C
C
 Sequential Circuits

Master Slave JK flip flop

The output of the master slave SR flip flop is undefined (both Q and 𝑄̅ will go into the
same logic ) when S=R=1 this condition should be avoided. This is achieved in JK flip flop.
In JK flip flop when J=K=1, the output continuously changes from 0 to 1 i.e. the output
toggles.

𝑸𝑴 𝑸𝑺 Q
J S Q S Q

C C C

̅𝑴 ̅𝑆
𝑸 ̅
K 𝑸 𝑸
R ̅
𝑸 R ̅
𝑸

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Case:1
Assume , J=K=0, 𝑄𝑛 = 0 , 𝑄̅𝑛 = 1 when C=1, the output of the master latch will become
𝑄𝑚+1 = 0 , 𝑄̅𝑚+1 =1. At this time slave latch will be inactive since the clock is at logic 0.
When C changes from logic 1 to logic 0, slave wakes up and copies the output of the
master, thus 𝑄𝑛+1 will become 0 and 𝑄̅𝑛+1 = 1.
Case:2
Assume , J=0 , K=1, 𝑄𝑛 = 0 , 𝑄̅𝑛 = 1 when C=1, the output of the master latch will
become 𝑄𝑚+1 = 0 , 𝑄̅𝑚+1 =1. At this time slave latch will be inactive since the clock is at
logic 0. When C changes from logic 1 to logic 0, slave wakes up and copies the output of
the master, thus 𝑄𝑛+1 will become 0 and 𝑄̅𝑛+1 = 1.
Case:3
Assume , J=1 , K=0, 𝑄𝑛 = 0 , 𝑄̅𝑛 = 1 when C=1, the output of the master latch will
become 𝑄𝑚+1 = 1 , 𝑄̅𝑚+1 = 0. At this time slave latch will be inactive since the clock is at
logic 0. When C changes from logic 1 to logic 0, slave wakes up and copies the output of
the master, thus 𝑄𝑛+1 will become 1 and 𝑄̅𝑛+1 = 0.
Case:2
Assume , J=1 , K=1, 𝑄𝑛 = 0 , 𝑄̅𝑛 = 1 when C=1, the output of the master latch will
become 𝑄𝑚+1 = 1 , 𝑄̅𝑚+1 = 0. At this time slave latch will be inactive since the clock is at

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 Sequential Circuits

logic 0. When C changes from logic 1 to logic 0, slave wakes up and copies the output of
the master, thus 𝑄𝑛+1 will become 1 and 𝑄̅𝑛+1 = 0.
Thus in the master slave flip flop master works when C=1 and slave when C=0 thus the
output is seen when C changes from 1 to 0 i.e falling edge of C. Hence this flip flop is said
to be negative edge or falling edge triggered.

C J K 𝑄𝑛 𝑄𝑀+1 𝑄𝑛+1
1 0 0 0 0 NC
0 0 0 0 NC 0
1 0 0 1 1 NC
0 0 0 1 NC 1
1 0 1 0 0 NC
0 0 1 0 NC 0
1 0 1 1 0 NC
0 0 1 1 NC 0
1 1 0 0 1 NC
0 1 0 0 NC 1
1 1 0 1 1 NC
0 1 0 1 NC 1
1 1 1 0 1 NC
0 1 1 0 NC 1
1 1 1 1 0 NC
0 1 1 1 NC 0

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C J K 𝑄𝑛 𝑄𝑛+1

0 0 0 0
Hold State
0 0 1 1

0 1 0 0
Reset
0 1 1 0

1 0 0 1
Set
1 0 1 1

1 1 0 1
Toggle
State
1 1 1 0

0’s and 1’s catching problem

In master slave JK flip flop master latch is enabled when the clock is in logic 1. Any changes
in the input during this period will cause the output of master 𝑄𝑀 to change. During this
period slave latch is disabled since the clock is inverter and given to the slave latch. For
example, assume Q was 0 and C changed to logic 1. While C=1 if J and K becomes 1 then
𝑄𝑀 will become 1. But at this time slave is disabled hence Q will continue to be zero. Now
while C=1 if J changes back to 0 while K=1 then 𝑄𝑀 will become 0 again. Now if C becomes
0 slave will wake up and copy the output of the master therefore Q will continue to be 0.
This is known as 1’s catching problem.

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Similarly assume C=1, Q was 1 and J=0, K=1 this will cause 𝑄𝑀 to become 0. This will not
be seen at Q since slave is disabled. Now if C continues to be 1 and J=1, K=0 then 𝑄𝑀 will
become 1 again. If now C becomes 0 then slave will wake up and copy this output causing
Q to continue to remain at 1. This is known as 0’s catching problem.
This can be avoided by making sure that the input change only when master is in the inactive
logic.

Master Slave D flip flop

C D 𝑄𝑛 𝑄𝑛+1
0 0 0
Reset
0 1 1

1 0 1
Set
1 1 1

D flip flop is known as data transfer flip flop since it transfers the data on the D input to its
output when the clock transitions from high to low. In this case if D=0 and the control
pulse, C transitions from 1 to 0 (since the master latch is active when C=1 and slave latch
works when C=0) the output becomes 0 i.e the data is transferred to the output. Similarly,
when D=1 and C transitions from 1 to 0 the output will become 1.

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 Sequential Circuits

Master Slave T flip flop

C T 𝑄𝑛 𝑄𝑛+1
Hold state
0 0 0

0 1 1
Toggle
1 0 1

1 1 0

Toggle flip flops are fundamentally JK flip flops when J=K=1. When T=1 the output
continuously toggles for every active edge of the clock (in general for every active edge of
the clock). Since the output is continuously changing between logic 0 and logic 1 it is
known as a toggle flip flop.

Edge triggered flip flops

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 Sequential Circuits

The 0’s and 1’s catching problem can be overcome if master slave respond to the either
the positive edge or negative edge of the control pulse. Such latches that work on the
edge of the control pulse are known as edge triggered flip flops

Negative edge triggered SR flip flop

Inputs Outputs
S R C 𝑄+ 𝑄̅ +
0 0 Q 𝑄̅

0 1 0 1

1 0 1 0

1 1 indeterminate indeterminate
x x 0 Q 𝑄̅

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 Sequential Circuits

Positive edge triggered JK flip flop

C J K 𝑄𝑛 𝑄𝑛+1

0 0 0 0
Hold State
0 0 1 1

0 1 0 0
Reset
0 1 1 0

1 0 0 1
Set
1 0 1 1

1 1 0 1
Toggle State
1 1 1 0

Asynchronous or direct inputs of flip flops

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 Sequential Circuits

Logic Circuit

C ̅̅̅̅
𝑃𝑅 ̅̅̅̅̅̅
𝐶𝐿𝑅 D 𝑄𝑛 𝑄𝑛+1
1 1 1 0 0 0
Reset
1 1 1 0 1 1
1 1 1 1 0 1
Set
1 1 1 1 1 1
x 0 1 x x 1 Preset
x 1 0 x x 0 Clear

Logic Symbol

Flip flops are circuits that changes state at a particular time (either at the positive edge or
negative edge) of the control signal. Sometimes it is necessary to initialize a circuit to a
known state before the application of the control signal. This is achieved with the help of
signals known as asynchronous inputs or direct inputs. These inputs are generally used in
flip flops and latches to set or reset (clear) the storage elements independent of the clock.
̅̅̅̅ = 0)the output of the D latch
In the above D latch when preset is asserted (𝑃𝑅
̅̅̅̅̅̅ =
immediately becomes logic 1 independent of D. Similarly, when clear is asserted (𝐶𝐿𝑅
0)the output of the D latch immediately becomes zero independent of D.
Note: These asynchronous inputs are directly given to the gates of the latch or flip flop
that generates the output as seen in the above circuit.

Characteristics Equation

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 Sequential Circuits

Flip flop Truth Table Characteristics Equation

C S R 𝑄𝑛 𝑄𝑛+1 R𝑄𝑛 00 01 11 10
0 0 0 0 S
0 0 1 1 0 0 0 0
0 1 0 0 1
0 1 1 0 1 1 1 * *
1 0 0 1
1 0 1 1 ̅ 𝑸𝒏
𝑸𝒏+𝟏 = 𝑺 + 𝑹
1 1 * *

D 𝑄𝑛 0 1
C D 𝑄𝑛 𝑄𝑛+1
0
0 0 0 0 0
Reset
0 1 1 1 1 1
1 0 1
Set
1 1 1 𝑸𝒏+𝟏 = 𝑫
C J K 𝑄𝑛 𝑄𝑛+1 𝐾𝑄𝑛
0 0 0 0 Hold J 00 01 11 10
State
0 0 1 1 0 0 0 0
1
0 1 0 0 Reset
0 1 1 0 1 1 1 0 1
1 0 0 1 Set
1 0 1 1
Toggle ̅𝒏 + 𝑲
𝑸𝒏+𝟏 = 𝑱𝑸 ̅ 𝑸𝒏
1 1 0 1 State
1 1 1 0
𝑄𝑛
C T 𝑄𝑛 𝑄𝑛+1 T 0 1
0 0 0 Hold 0 0
state 1
0 1 1
1 0 1 Toggle 1 1 0

1 1 0 𝑸𝒏+𝟏 = 𝑻𝑄̅𝑛 + 𝑻
̅ 𝑸𝒏

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