11/19/25, 4:01 PM Google Gemini
Focusing on a complete, functional RISC-V Microcontroller (MCU) style SOC for flight control,
excluding a separate accelerator, is the perfect scope for a "1 Tapeout Per Student" contest. It
demonstrates mastery of core digital design, integration, and a real-time application.
Your final SOC is essentially a customized Flight Control Unit (FCU) chip. Here are the essential
blocks you must integrate:
🚁 1. The Core Processing Subsystem
This is the brain of your drone controller, responsible for running the PID (Proportional-Integral-
Derivative) loop and the flight control firmware (likely an RTOS or bare-metal code).
RISC-V Core (RV32IM/C):
RV32I (Base Integer ISA): The fundamental instruction set.
M Extension (Multiplication/Division): Essential for efficient PID loop calculations and
vector math required for rotation matrices.
C Extension (Compressed Instructions): Highly recommended for MCUs. It reduces
code size, which is critical for smaller on-chip memory.
Local Memory:
Instruction/Data Cache (Optional/Small): May be included if the core is fast enough to
benefit.
Tightly Coupled Memory (TCM) / SRAM: Critical. Fast, single-cycle access memory for
the main flight control variables and stack. This ensures deterministic, low-
latency execution for the PID loop.
Interrupt Controller (PLIC/CLIC): Manages all peripheral interrupts (timers, sensors,
communication). Low interrupt latency is non-negotiable for a flight controller.
💾 2. The Memory Subsystem & Bus Architecture
This ensures data moves quickly and reliably between all components.
Bus Interconnect: A simple, high-speed on-chip bus (like Wishbone or a lightweight AXI-
Lite) to connect the CPU, memories, and peripherals.
Non-Volatile Memory Interface (Flash/ROM):
Interface to external SPI Flash (for storing firmware) or on-chip Flash/ROM (if fabrication
allows).
DMA Controller (Direct Memory Access):
Crucial for efficiency. Allows peripherals (like SPI for sensors or UART for telemetry) to
transfer data directly to/from SRAM without burdening the CPU. The CPU should be
focused on the PID calculation.
⚙️ 3. Real-Time Flight Peripherals
These are the specialized hardware blocks that interface with the physical drone components.
They must be designed for real-time constraints.
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11/19/25, 4:01 PM Google Gemini
Peripheral Drone Application Key Design Feature
PWM/Timer Unit Motor/ESC Must have many
Control. Generates the independent
high-frequency Pulse Width channels (e.g., 4-8) and
Modulation signals to control support high-resolution
the Electronic Speed (e.g., 500 Hz to 1 kHz
Controllers (ESCs) for the update rates).
motors.
SPI/I²C Sensor Connectivity. Used Must support high-speed
Interfaces to read data from the Inertial master mode (e.g.,
Measurement Unit (IMU - 10 MHz+ SPI) for fetching
gyro/accelerometer), real-time sensor data at
barometer, and high rates (e.g., 1 kHz).
magnetometer.
ADC (Analog-to- Battery Monitoring & Requires high
Digital Analog Sensors. Reads resolution (12-bit or more)
Converter) battery voltage/current and and fast conversion
other analog signals. rate for timely power
monitoring.
UART (Universal Telemetry & Requires multiple
Asynchronous GPS. Communication with instances and high baud
Receiver- the radio link (telemetry), rates for reliable data
Transmitter) GPS receiver (GNSS), and transmission.
debug consoles.
GPIO (General Status LEDs, Buzzer control, Basic configuration, but
Purpose I/O) simple sensor inputs. essential for debugging
and user feedback.
🛡️ 4. Security, Safety, and Debug
For any embedded system, especially a flight controller, these are required for reliability and
development.
Watchdog Timer: A hardware timer that automatically resets the entire SOC if the software
(the PID loop) hangs or fails to "feed the dog" within a set period. Essential for flight safety.
JTAG/Debug Unit: Provides an interface for debugging the RISC-V core in real-time, allowing
you to stop execution and inspect registers/memory. This is mandatory for testing your
tapeout.
Clock and Reset Generator: Manages the system clock domains and ensures a clean,
reliable reset sequence for the entire SOC.
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11/19/25, 4:01 PM Google Gemini
This architecture forms a complete, verifiable, and highly functional SOC that fits perfectly within
the scope of a competition focusing on tapeout completion.
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