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Simple RISC Computer Architecture Overview

The document provides an overview of a Simple RISC Computer (SRC) architecture, detailing its components such as a 32-bit register and memory organization. It outlines instruction formats, memory access methods, arithmetic and logical instructions, and examples of SRC code implementations for various operations. Additionally, it covers shift and rotate instructions, as well as branch instructions with practical exercises for coding in SRC assembly language.

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0% found this document useful (0 votes)
9 views31 pages

Simple RISC Computer Architecture Overview

The document provides an overview of a Simple RISC Computer (SRC) architecture, detailing its components such as a 32-bit register and memory organization. It outlines instruction formats, memory access methods, arithmetic and logical instructions, and examples of SRC code implementations for various operations. Additionally, it covers shift and rotate instructions, as well as branch instructions with practical exercises for coding in SRC assembly language.

Uploaded by

ayaanwarabd
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

COMPUTER ARCHITECTURE

LECTURE 3: SIMPLE RISC COMPUTER (SRC)


DR. RASHA MONTASER
SIMPLE RISC COMPUTER (SRC)
 It has the following
 a 32bit, 32 general purpose register
 Program counter (PC)
 Instruction register (IR)
 Main memory is organized as an array of bytes
 Only 32-bit words can be fetched or stored into main memory
 Memory access is done using load/store instruction only
 A word address A is defined as 4 bytes at that address and succeeding three
addresses
 The byte at the lowest address contains the most significant 8 bits, the byte at the
next address contain the next most significant 8 bits, and so on
INSTRUCTION FORMAT

 SRC has 23 instruction in 8 different formats


 Load (ld, ldr, la, lar) and and store (st and str)
 Branch (br, brl)
 Arithmetic instruction (add, addi,sub, and neg)
 Logical and shift instruction (and, andi, or, ori, shr, shl, shc)
 Miscellaneous instructions: nop and stop
INSTRUCTION FORMAT

 All instruction are 32 bits long


 All instructions have 5 bits opcode field allowing 32 different instructions
 We define only 23 instructions
 The ra,rb,rc fields are 5-bit fields that specify one of the 32 general purpose registers
 Constant c1,c2,c3, Cond and Counter are used in various ways
 The notation M[x] means the value stored at memory space
 The notation R[x] means the value stored at register
 The register to be loaded or stored is specified in the 5- bit field ra.
 The address is specified as the 17-bit values in the c2 field
ACCESSING MEMORY

 ld ra,c2 ; direct addressing: R[ra] =M[c2]


 ld ra,c2(rb) ; index addressing (rb<> 0) : R[ra] =M[c2+R[rb]]
 st ra,c2 ; direct addressing: M[c2] =R[ra]
 st ra,c2(rb) ; index addressing (rb<> 0) : M[c2+R[rb]]=R[ra]
 la ra,c2 ; load displacement address : R[ra] =c2
 la ra,c2(rb) ; load displacement address : R[ra] =c2+R[rb]
LOAD AND STORE RELATIVE

 ldr ra,c1 ; load register relative : R[ra] =M[PC+c1]


 str ra,c1 ; store register relative : M[PC+c1]= R[ra]
 lar ra,c1 ; load relative address : R[ra] =PC+c1
EXAMPLE OF SRC LOAD AND STORE INSTRUCTIONS
EXERCISE

 Write the SRC code to implement the C code statement:


 X=5
 Solution:
.org 1000 ; Next word will be added at address 1000
x: .dw 1 ; Reverse 1 word for variable x
.org 5000 ; Program will be loaded at location 5000
la r1,5; R[r1]=5
st r1,x; M[x] = R[r1]
EXERCISE (BINARY ENCODING)

 Encode the following instruction ld r22, 24(r4), knowing that


the opcode of the instruction ld is 1.
 Solution:
 00001 10110 00100 00000000000011000 = 0x0D880018
ARITHMETIC AND LOGIC INSTRUCTIONS
 Operand 1- operand instructions
 neg ra, rc ; Negate : R[ra] = - R[rc]
 not ra, rc ; Not : R[ra] = ! R[rc]

 Operand 2-operands instructions


 add ra, rb, rc ; 2’s complement addition: R[ra] = R[rb] + R[rc]
 sub ra, rb, rc ; 2’s complement subtraction: R[ra] = R[rb] - R[rc]
 and ra, rb, rc ; Logical AND: R[ra] = R[rb] ˆ R[rc]
 or ra, rb, rc ; Logical OR : R[ra] = R[rb] ˇ R[rc]

 Immediate Addressing ALU instructions


 addi ra, rb, c2 ; immediate 2’s comp addition R[ra] = R[rb] + c2
 andi ra, rb, c2 ; immediate logic al AND R[ra] = R[rb] ˆ c 2
 ori ra, rb, c2 ; immediate logical OR = R[rb] ˇ c2
EXERCISE
 Write the SRC code to implement the C code statement:
 x = 5; y=2; z=x+y;
 Solution:
.org 1000 ; Next word will be added at address 1000
x: .dw 1 ; Reverse 1 word for variable x
y: .dw 1 ; Reverse 1 word for variable y
z: .dw 1 ; Reverse 1 word for variable z
.org 5000 ; Program will be loaded at location 5000
la r1,5; R[r1]=5
st r1,x; M[x] = R[r1]
la r2,2; R[r2]=2
st r2,y; M[y] = R[r2]
add r3,r1,r2; R[r3]=R[r1]+R[r2]
st r3,z; M[z]=R[r3]
EXERCISE

 Write the SRC to implement the expression, assume that SRC has a multiply instruction:
 A=(B-C)*D
Solution:
Ld r0,B
Ld r1,C
Ld r2,D
Sub r0,r0,r1
Mpy r0,r0,r2
Str r0,A
SHIFT INSTRUCTIONS

 Shr ra, rb, rc ;shift R[rb] right into R[ra] by count in R[rc] , add zeros to right
 Shr ra, rb, count ;shift R[rb] right into R[ra] by count in c3 , add zeros to right
 Shra ra, rb, rc ;A shift R[rb] right into R[ra] by count in R[rc], copies the msb
 Shra ra, rb, count ;A shift R[rb] right into R[ra] by count in c3 , copies the msb
 Shl ra, rb, rc ;shift R[rb] left into R[ra] by count in R[rc]
 Shl ra, rb, count ;shift R[rb] left into R[ra] by count in c3
 Shc ra, rb, rc ;shift R[rb] circ (left) into R[ra] by count in R[rc]
 Shc ra, rb, count ;shift R[rb] circ (left) into R[ra] by count in c3
NON CIRCULAR SHIFT (SHL)

 Logic Shift 10110010


 Shift left: push the pattern to the left and ADD 0 to the least
significant bit
LEFT SHIFT

 Multiplication with 2n where n is the number of bits to shift.


 Ex1: 3 X 8 = 3 X 23 = 24
 (3 bits shift)
 0000 0011
 0000 0110
 0000 1100
 0001 1000 ➔16+8=24
LEFT SHIFT

 Multiplication with 2n where n is the number of bits to shift.


 Ex2: 5 X 16 = 5 X 24 = 80
 (4 bits shift)
 0000 0101
 0000 1010
 0001 0100
 0010 1000
 0101 0000 ➔64+16=80
EXERCISE

 Write the SRC to implement the expression, apply multiplication


using shift operations.
 A= B*16;
 Solution
 Ld r0,B
 Shl r1,r0,4
 Str r1,A
NON CIRCULAR SHIFT (SHR)

 Logic Shift 01011001


 Shift right: push the pattern to the right and add zero to the most
significant bit
RIGHT SHIFT

 Division with 2n where n is the number of bits to shift.


 Ex1: 16/4 = 16 X 22 = 4
 (2 bits shift)
 0001 0000
 0000 1000
 0000 0100 ➔4
EXERCISE

 Write the SRC to implement the expression, apply division using


shift operations.
 A= B/4;
 Solution
 Ld r0,B
 Shr r1,r0,2
 Str r1,A
NON CIRCULAR SHIFT (SHRA )

 Arithmetic Shift: Arithmetic shift is used in signed numbers to


maintain the sign 11011001
 Shift right
EXERCISE

 Write the SRC to implement the expression, apply division using


shift operations(assume that the number is signed number).
 A= B/4;
 Solution
 Ld r0,B
 Shra r1,r0,2
 Str r1,A
ROTATION (SHC)

 Circular shift
1011001 0110011
 Example: 1011001
 left Rotate 1 bit
LEFT ROTATE

 Left Rotate the following pattern 3 times:


 1110 1010
 1101 0101
 1010 1011
 0101 0111
BRANCH INSTRUCTIONS
EXERCISE

 Write the SRC code to implement the C code statement:


# define cost 125
If(x<0) x=-x;
 Solution
Cost: .equ 125
.org 1000
X: .dw 1
.org 5000
ld r1, X
ld r0, over
brpl r0, r1
neg r1,r1
Over:
EXERCISE
 Write the SRC code to implement the C code statement:
If(a<0) a=-a; else a=0;
Solution:
.org 1000
a: .dw 1
.org 5000
ld r1, a
ld r0, over
ld r2, else
brpl r2, r1
neg r1,r1
br r0
else: la r1,0
Over: st r1,a
EXERCISE
 Write the SRC code to implement the C code statement:
For (i=0; i<10,i++) ndigit[i]= i+1;
Solution:
la r0,0
ld r1, ndigit
ld r3,loop
Loop: addi r1,r0,1
st r1, 0(r1)
addi r1,r1,4
addi r0,r0,1
subi r2,r0,10
brim r3, r2

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