Dual, 12-/14-/16-Bit nanoDACs® with

5 ppm/°C On-Chip Reference, I2C® Interface

Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
FEATURES FUNCTIONAL BLOCK DIAGRAMS
VDD VREFIN/VREFOUT
Low power, smallest pin-compatible, dual nanoDACs GND

AD5627R/AD5647R/AD5667R AD5627R/AD5647R/AD5667R 1.25V/2.5V REF

12-/14-/16-bit ADDR
BUFFER

On-chip 1.25 V/2.5 V, 5 ppm/°C reference INPUT DAC STRING VOUTA

INTERFACE
REGISTER REGISTER DAC A

LOGIC
AD5627/AD5667 SCL
BUFFER
12-/16-bit INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTB

External reference only SDA

3 mm x 3 mm LFCSP and 10-lead MSOP POWER-ON

RESET
POWER-DOWN
LOGIC
2.7 V to 5.5 V power supply

06342-001
Guaranteed monotonic by design LDAC CLR

Power-on reset to zero scale Figure 1. AD5627R/AD5647R/AD5667R

Per channel power-down VDD GND VREFIN

Hardware LDAC and CLR functions AD5627/AD5667

I2C-compatible serial interface supports standard (100 kHz), BUFFER
ADDR
fast (400 kHz), and high speed (3.4 MHz) modes INPUT DAC STRING VOUTA

INTERFACE
REGISTER REGISTER DAC A

LOGIC
APPLICATIONS SCL
BUFFER
INPUT DAC STRING VOUTB
Process control SDA
REGISTER REGISTER DAC B

Data acquisition systems POWER-ON POWER-DOWN

Portable battery-powered instruments RESET LOGIC

06342-002
Digital gain and offset adjustment LDAC CLR
Programmable voltage and current sources Figure 2. AD5627/AD5667
Programmable attenuators

GENERAL DESCRIPTION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 members The device contains a per-channel power-down feature that
of the nanoDAC family are low power, dual, 12-, 14-, 16-bit reduces the current consumption of the device to 480 nA at 5 V
buffered voltage-out digital-to-analog converters (DACs) and provides software-selectable output loads while in power-
with/without on-chip reference. All devices operate from a single down mode. The low power consumption of this device in
2.7 V to 5.5 V supply, are guaranteed monotonic by design, and normal operation makes it ideally suited to portable battery-
have an I2C-compatible serial interface. operated equipment. The on-chip precision output amplifier
The AD5627R/AD5647R/AD5667R have an on-chip reference. enables rail-to-rail output swing.
The AD5627RBCPZ, AD5647RBCPZ, and AD5667RBCPZ have a The AD5627R/AD5647R/AD5667R, AD5627/AD5667 use a
1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V; 2-wire I2C-compatible serial interface that operates in standard
the AD5627RBRMZ and AD5667RBRMZ have a 2.5 V, 5 ppm/°C (100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes.
reference, giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external Table 1. Related Devices
reference. The internal reference is enabled via a software write. Part No. Description
The AD5667 and AD5627 require an external reference voltage AD5663 2.7 V to 5.5 V, dual 16-bit DAC,
external reference, I2C interface
to set the output range of the DAC.
AD5623R/AD5643R/AD5663R 2.7 V to 5.5 V, dual 12-, 14-, 16-
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 bit DACs, internal reference,
incorporate a power-on reset circuit that ensures the DAC I2C interface
output powers up to 0 V, and remains there until a valid write AD5625R/AD5645R/AD5665R, 2.7 V to 5.5 V, quad 12-, 14-, 16-
takes place. AD5625/AD5665 bit DACs, with/without internal
reference, I2C interface

Rev. B Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved.
Trademarks and registered trademarks are the property of their respective owners. Technical Support [Link]

[Link]
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Write Operation.......................................................................... 21
Applications ....................................................................................... 1 Read Operation........................................................................... 21
Functional Block Diagrams ............................................................. 1 High Speed Mode ....................................................................... 21
General Description ......................................................................... 1 Input Shift Register .................................................................... 23
Revision History ............................................................................... 2 Multiple Byte Operation ............................................................ 23
Specifications..................................................................................... 3 Broadcast Mode .......................................................................... 23
AC Characteristics ........................................................................ 5 LDAC Function .......................................................................... 23
I C Timing Specifications ............................................................ 6
2
Power-Down Modes .................................................................. 25
Absolute Maximum Ratings ............................................................ 8 Power-On Reset and Software Reset........................................ 26
ESD Caution .................................................................................. 8 Clear Pin (CLR) .......................................................................... 26
Pin Configuration and Function Descriptions ............................. 9 Internal Reference Setup (R Versions) .................................... 26
Typical Performance Characteristics ........................................... 10 Application Information ................................................................ 28
Terminology .................................................................................... 18 Using a Reference as a Power Supply for the
Theory of Operation ...................................................................... 20 AD5627R/AD5647R/AD5667R, AD5627/AD5667 .................. 28
D/A Section ................................................................................. 20 Bipolar Operation Using the AD5627R/AD5647R/AD5667R,
AD5627/AD5667 ......................................................................... 28
Resistor String ............................................................................. 20
Power Supply Bypassing and Grounding ................................ 28
Output Amplifier ........................................................................ 20
Outline Dimensions ....................................................................... 29
Internal Reference ...................................................................... 20
Ordering Guide .......................................................................... 30
External Reference...................................................................... 20
Serial Interface ............................................................................ 21

REVISION HISTORY
9/2016—Rev. A to Rev. B
Changed SPI to I2C ........................................................ Throughout

2/2016—Rev. 0 to Rev. A
Changes to Internal Reference Section ............................................. 20
Changes to Power-On Reset and Software Reset Section ........... 26
Updated Outline Dimensions .............................................................. 29
Changes to Ordering Guide .................................................................. 30

1/2007—Revision 0: Initial Version

Rev. B | Page 2 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667

SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments 1
STATIC PERFORMANCE 2
AD5667R/AD5667
Resolution 16 Bits
Relative Accuracy ±8 ±12 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic by design
AD5647R
Resolution 14 Bits
Relative Accuracy ±2 ±4 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
AD5627R/AD5627
Resolution 12 Bits
Relative Accuracy ±0.5 ±1 LSB
Differential Nonlinearity ±0.25 LSB Guaranteed monotonic by design
Zero-Code Error 2 10 mV All 0s loaded to DAC register
Offset Error ±1 ±10 mV
Full-Scale Error −0.1 ±1 % of FSR All 1s loaded to DAC register
Gain Error ±1.5 % of FSR
Zero-Code Error Drift ±2 µV/°C
Gain Temperature Coefficient ±2.5 ppm Of FSR/°C
DC Power Supply Rejection Ratio −100 dB DAC code = midscale ; VDD = 5 V ± 10%
DC Crosstalk (External Reference) 15 µV Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
10 µV/mA Due to load current change
8 µV Due to powering down (per channel)
DC Crosstalk (Internal Reference) 25 µV Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
20 µV/mA Due to load current change
10 µV Due to powering down (per channel)
OUTPUT CHARACTERISTICS 3
Output Voltage Range 0 VDD V
Capacitive Load Stability 2 nF RL = ∞
10 nF RL = 2 kΩ
DC Output Impedance 0.5 Ω
Short-Circuit Current 30 mA VDD = 5 V
Power-Up Time 4 µs Coming out of power-down mode; VDD = 5 V
REFERENCE INPUTS
Reference Current 110 130 µA VREF = VDD = 5.5 V
Reference Input Range 0.75 VDD V
Reference Input Impedance 50 kΩ
REFERENCE OUTPUT
(LFCSP_WD PACKAGE)
Output Voltage 1.247 1.253 V At ambient
Reference TC3 ±10 ppm/°C
Output Impedance 7.5 kΩ
REFERENCE OUTPUT (MSOP PACKAGE)
Output Voltage 2.495 2.505 V At ambient
Reference TC3 ±5 ±10 ppm/°C
Output Impedance 7.5 kΩ

Rev. B | Page 3 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments 1
LOGIC INPUTS (ADDR, CLR, LDAC)3
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.15 × VDD V
VINH, Input High Voltage 0.85 × VDD V
CIN, Pin Capacitance 2 pF ADDR
20 pF CLR, LDAC
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC INPUTS (SDA, SCL)
IIN, Input Current ±1 µA
VINL, Input Low Voltage 0.3 × VDD V
VINH, Input High Voltage 0.7 × VDD V
CIN, Pin Capacitance 2 pF
VHYST, Input Hysteresis 0.1 × VDD V
LOGIC OUTPUTS (OPEN-DRAIN)
VOL, Output Low Voltage 0.4 V ISINK = 3 mA
0.6 V ISINK = 6 mA
Floating-State Leakage Current ±1 µA
Floating-State Output Capacitance 2 pF
POWER REQUIREMENTS
VDD 2.7 5.5 V
IDD (Normal Mode) 4 VIH = VDD, VIL = GND
VDD = 4.5 V to 5.5 V 0.4 0.5 mA Internal reference off
VDD = 2.7 V to 3.6 V 0.35 0.45 mA Internal reference off
VDD = 4.5 V to 5.5 V 0.95 1.15 mA Internal reference on
VDD = 2.7 V to 3.6 V 0.8 0.95 mA Internal reference on
IDD (All Power-Down Modes) 5 0.48 1 µA VIH = VDD, VIL = GND
1
Temperature range: B grade: −40°C to +105°C.
2
Linearity calculated using a reduced code range: AD5667R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to Code 4064).
Output unloaded.
3
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down.

Rev. B | Page 4 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1

Table 3.
Parameter 2 Min Typ Max Unit Test Conditions/Comments 3
Output Voltage Settling Time
AD5627R/AD5627 3 4.5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5647R 3.5 5 µs ¼ to ¾ scale settling to ±0.5 LSB
AD5667R/AD5667 4 7 µs ¼ to ¾ scale settling to ±2 LSB
Slew Rate 1.8 V/µs
Digital-to-Analog Glitch Impulse 15 nV-s 1 LSB change around major carry transition
Digital Feedthrough 0.1 nV-s
Reference Feedthrough −90 dB VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk 0.1 nV-s
Analog Crosstalk 1 nV-s External reference
4 nV-s Internal reference
DAC to DAC Crosstalk 1 nV-s External reference
4 nV-s Internal reference
Multiplying Bandwidth 340 kHz VREF = 2 V ± 0.1 V p-p
Total Harmonic Distortion −80 dB VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density 120 nV/√Hz DAC code = midscale, 1 kHz
100 nV/√Hz DAC code = midscale, 10 kHz
Output Noise 15 µV p-p 0.1 Hz to 10 Hz

1
Guaranteed by design and characterization, not production tested.
2
See the Terminology section.
3
Temperature range is −40°C to +105°C, typical at 25°C.

Rev. B | Page 5 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1

Table 4.
Parameter Test Conditions/Comments 2 Min Max Unit Description
fSCL 3 Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode, CB = 100 pF 3.4 MHz
High speed mode, CB = 400 pF 1.7 MHz
t1 Standard mode 4 μs tHIGH, SCL high time
Fast mode 0.6 μs
High speed mode, CB = 100 pF 60 ns
High speed mode, CB = 400 pF 120 ns
t2 Standard mode 4.7 μs tLOW, SCL low time
Fast mode 1.3 μs
High speed mode, CB = 100 pF 160 ns
High speed mode, CB = 400 pF 320 ns
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t4 Standard mode 0 3.45 μs tHD;DAT, data hold time
Fast mode 0 0.9 μs
High speed mode, CB = 100 pF 0 70 ns
High speed mode, CB = 400 pF 0 150 ns
t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition
Fast mode 0.6 μs
High speed mode 160 ns
t6 Standard mode 4 μs tHD;STA, hold time (repeated) start condition
Fast mode 0.6 μs
High speed mode 160 ns
t7 Standard mode 4.7 μs tBUF, bus free time between a stop and a start condition
Fast mode 1.3 μs
t8 Standard mode 4 μs tSU;STO, setup time for a stop condition
Fast mode 0.6 μs
High speed mode 160 ns
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
Fast mode 300 ns
High speed mode, CB = 100 pF 10 80 ns
High speed mode, CB = 400 pF 20 160 ns

Rev. B | Page 6 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
Parameter Test Conditions/Comments 2 Min Max Unit Description
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 300 ns
High speed mode, CB = 100 pF 10 40 ns
High speed mode, CB = 400 pF 20 80 ns
t13 Standard mode 10 ns LDAC pulse width low
Fast mode 10 ns
High speed mode 10 ns
t14 Standard mode 300 ns Falling edge of 9th SCL clock pulse of last byte of valid write to LDAC
falling edge
Fast mode 300 ns
High speed mode 30 ns
t15 Standard mode 20 ns CLR pulse width low
Fast mode 20 ns
High speed mode 20 ns
tSP 4 Fast mode 0 50 ns Pulse width of spike suppressed
High speed mode 0 10 ns
1
See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7.
2
CB refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the device.
4
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.

t11 t12 t6
t2
SCL
t6 t1 t5 t8
t4 t3 t10 t9
SDA
t7
P S S t14 P

t13
LDAC*

t15
CLR

06342-003
*ASYNCHRONOUS LDAC UPDATE MODE.

Figure 3. 2-Wire Serial Interface Timing Diagram

Rev. B | Page 7 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
Table 5. stress rating only; functional operation of the product at these
Parameter Rating or any other conditions above those indicated in the operational
VDD to GND −0.3 V to +7 V section of this specification is not implied. Operation beyond
VOUT to GND −0.3 V to VDD + 0.3 V
the maximum operating conditions for extended periods may
VREFIN/VREFOUT to GND −0.3 V to VDD + 0.3 V
affect product reliability.
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range, Industrial −40°C to +105°C ESD CAUTION
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ maximum) 150°C
Power Dissipation (TJ max − TA)/θJA
θJA Thermal Impedance
LFCSP_WD Package (4-Layer Board) 61°C/W
MSOP Package 150.4°C/W
Reflow Soldering Peak Temperature, Pb-Free 260°C ± 5°C

Rev. B | Page 8 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VOUTA 1 10 VREFIN VOUTA 1 10 VREFIN/VREFOUT

VOUTB 2 AD5627/ 9 VDD VOUTB 2 AD5627R/ 9 VDD

AD5667 AD5647R/
GND 3 8 SDA GND 3 AD5667R 8 SDA
LDAC 4 TOP VIEW 7 SCL LDAC 4 TOP VIEW 7 SCL
(Not to Scale) (Not to Scale)
CLR 5 6 ADDR CLR 5 6 ADDR

06342-101

06342-102
EXPOSED PAD TIED TO GND EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE. ON LFCSP PACKAGE.

Figure 4. AD5627/AD5667 Pin Configuration Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration

Table 6. Pin Function Descriptions

Pin
No. Mnemonic Description
1 VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
2 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
3 GND Ground reference point for all circuitry on the device.
4 LDAC Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows
simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
5 CLR Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The device exits
clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a
write sequence, the write is aborted. If CLR is activated during high speed mode the device will exit high speed mode.
6 ADDR Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
7 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
9 VDD Power Supply Input. These devices can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
10 VREFIN/VREFOUT The AD5627R/AD5647R/AD5667R have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference input. (The internal reference and reference output are only available on R
suffix versions.) The AD5627/AD5667 have a reference input pin only.

Rev. B | Page 9 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

10 1.0
VDD = VREF = 5V VDD = VREF = 5V
8 TA = 25°C 0.8 TA = 25°C

6 0.6

4 0.4

DNL ERROR (LSB)

INL ERROR (LSB)

2 0.2

0 0

–2 –0.2

–4 –0.4

–6 –0.6

–8 –0.8

–10 –1.0

06342-007
06342-005
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k 0 10k 20k 30k 40k 50k 60k
CODE CODE

Figure 6. AD5667 INL, External Reference Figure 9. AD5667 DNL, External Reference

4 0.5
VDD = VREF = 5V VDD = VREF = 5V
TA = 25°C 0.4 TA = 25°C
3
0.3
2
0.2
DNL ERROR (LSB)
INL ERROR (LSB)

1
0.1

0 0

–0.1
–1
–0.2
–2
–0.3
–3
–0.4

–4 –0.5
06342-006

06342-008
0 2500 5000 7500 10000 12500 15000 0 2500 5000 7500 10000 12500 15000
CODE CODE

Figure 7. AD5647R INL, External Reference Figure 10. DNL AD5647R, External Reference

1.0 0.20
VDD = VREF = 5V VDD = VREF = 5V
0.8 TA = 25°C TA = 25°C
0.15
0.6
0.10
0.4
DNL ERROR (LSB)
INL ERROR (LSB)

0.05
0.2

0 0

–0.2
–0.05
–0.4
–0.10
–0.6
–0.15
–0.8

–1.0 –0.20
06342-009
06342-100

0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
CODE CODE

Figure 8. AD5627 INL, External Reference Figure 11. AD5627 DNL, External Reference

Rev. B | Page 10 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
10 1.0
VDD = 5V VDD = 5V
8 VREFOUT = 2.5V 0.8 VREFOUT = 2.5V
TA = 25°C TA = 25°C
6 0.6

4 0.4

DNL ERROR (LSB)

INL ERROR (LSB)

2 0.2

0 0

–0.2
–2
–0.4
–4
–0.6
–6
–0.8
–8
–1.0
–10

5000

10000

15000

20000

25000

30000

35000

40000

45000

50000

55000

60000

65000
0

5000

10000

15000

20000

25000

30000

35000

40000

45000

50000

55000

60000

65000

06342-013
06342-010
CODE
CODE

Figure 12. AD5667R INL, 2.5 V Internal Reference Figure 15. AD5667R DNL, 2.5 V Internal Reference
4 0.5
VDD = 5V VDD = 5V
VREFOUT = 2.5V 0.4 VREFOUT = 2.5V
3
TA = 25°C TA = 25°C
0.3
2
0.2

DNL ERROR (LSB)

INL ERROR (LSB)

1
0.1

0 0

–0.1
–1
–0.2
–2
–0.3
–3
–0.4

–4 –0.5
0

1250

2500

3750

5000

6250

7500

8750

11250
10000

12500

13750

15000

16250

1250

2500

3750

5000

6250

7500

8750

11250
10000

12500

13750

15000

16250
06342-011

06342-014
CODE CODE

Figure 13. AD5647R INL, 2.5 V Internal Reference Figure 16. AD5647R DNL, 2.5 V Internal Reference

1.0 0.20
VDD = 5V VDD = 5V
0.8 VREFOUT = 2.5V VREFOUT = 2.5V
0.15
TA = 25°C TA = 25°C
0.6
0.10
0.4
DNL ERROR (LSB)
INL ERROR (LSB)

0.05
0.2

0 0

–0.2 –0.05
–0.4
–0.10
–0.6
–0.15
–0.8

–1.0 –0.20
06342-015
06342-012

0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
CODE CODE

Figure 14. AD5627R INL, 2.5 V Internal Reference Figure 17. AD5627R DNL, 2.5 V Internal Reference

Rev. B | Page 11 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
10 1.0
VDD = 3V VDD = 3V
8 VREFOUT = 1.25V 0.8 VREFOUT = 1.25V
TA = 25°C TA = 25°C
6 0.6

4 0.4

DNL ERROR (LSB)

INL ERROR (LSB)

2 0.2

0 0

–2 –0.2

–4 –0.4

–6 –0.6

–8 –0.8

–10 –1.0
0

0
5000

5000
10000

15000

20000

25000

30000

35000

40000

45000

50000

55000

60000

65000

10000

15000

20000

25000

30000

35000

40000

45000

50000

55000

60000

65000
06342-016

06342-019
CODE CODE

Figure 18. AD5667R INL,1.25 V Internal Reference Figure 21. AD5667R DNL,1.25 V Internal Reference
4 0.5
VDD = 3V VDD = 3V
VREFOUT = 1.25V 0.4 VREFOUT = 1.25V
3
TA = 25°C TA = 25°C
0.3
2
0.2
DNL ERROR (LSB)
INL ERROR (LSB)

1
0.1

0 0

–0.1
–1
–0.2
–2
–0.3
–3
–0.4

–4 –0.5
0

0
1250

2500

3750

5000

6250

7500

8750

1250

2500

3750

5000

6250

7500

8750
10000

11250

12500

13750

15000

16250

10000

11250

12500

13750

15000

16250
06342-017

06342-020
CODE CODE

Figure 19. AD5647R INL, 1.25 V Internal Reference Figure 22. AD5647R DNL,1.25 V Internal Reference
1.0 0.20
VDD = 3V VDD = 3V
0.8 VREFOUT = 1.25V VREFOUT = 1.25V
0.15
TA = 25°C TA = 25°C
0.6
0.10
0.4
DNL ERROR (LSB)
INL ERROR (LSB)

0.05
0.2

0 0

–0.2
–0.05
–0.4
–0.10
–0.6
–0.15
–0.8

–1.0 –0.20
06342-018

06342-021

0 500 1000 1500 2000 2500 3000 3500 4000 0 500 1000 1500 2000 2500 3000 3500 4000
CODE CODE

Figure 20. AD5627R INL,1.25 V Internal Reference Figure 23. AD5627R DNL, 1.25 V Internal Reference

Rev. B | Page 12 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
8 0
VDD = 5V
–0.02
6 MAX INL
VDD = VREF = 5V –0.04
4 GAIN ERROR
–0.06

ERROR (% FSR)
2
ERROR (LSB)

–0.08
MAX DNL
0 –0.10
MIN DNL
–0.12
–2
–0.14 FULL-SCALE ERROR
–4
MIN INL –0.16
–6
–0.18

–8 –0.20

06342-022

06342-025
–40 –20 0 20 40 60 80 100 –40 –20 0 20 40 60 80 100
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 24. INL Error and DNL Error vs. Temperature Figure 27. Gain Error and Full-Scale Error vs. Temperature

10 1.5

8 MAX INL
1.0 ZERO-SCALE ERROR
6
VDD = 5V 0.5
4 TA = 25°C
0
ERROR (LSB)

ERROR (mV)
2
MAX DNL
0 –0.5
MIN DNL
–2
–1.0
–4
–1.5
–6 OFFSET ERROR
MIN INL
–2.0
–8

–10 –2.5

06342-026
06342-023

0.75 1.25 1.75 2.25 2.75 3.25 3.75 4.25 4.75 –40 –20 0 20 40 60 80 100
VREF (V) TEMPERATURE (°C)

Figure 25. INL and DNL Error vs. VREF Figure 28. Zero-Scale Error and Offset Error vs. Temperature
8 1.0

6 MAX INL
TA = 25°C 0.5
4
GAIN ERROR
0
ERROR (% FSR)

2
ERROR (LSB)

MAX DNL FULL-SCALE ERROR

0 –0.5
MIN DNL
–2
–1.0
–4
MIN INL –1.5
–6

–8 –2.0
06342-024

06342-027

2.7 3.2 3.7 4.2 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2
VDD (V) VDD (V)

Figure 26. INL and DNL Error vs. Supply Figure 29. Gain Error and Full-Scale Error vs. Supply

Rev. B | Page 13 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
1.0 0.5
TA = 25°C DAC LOADED WITH DAC LOADED WITH
0.4 FULL-SCALE ZERO-SCALE
0.5 ZERO-SCALE ERROR SOURCING CURRENT SINKING CURRENT
0.3
0 0.2

ERROR VOLTAGE (V)

ERROR (mV)

0.1 VDD = 3V
–0.5 VREFOUT = 1.25V
0
–1.0
–0.1

–1.5 –0.2

–0.3 VDD = 5V
–2.0 OFFSET ERROR VREFOUT = 2.5V
–0.4
–2.5 –0.5

06342-028

06342-031
2.7 3.2 3.7 4.2 4.7 5.2 –10 –8 –6 –4 –2 0 2 4 6 8 10
VDD (V) CURRENT (mA)

Figure 30. Zero-Scale Error and Offset Error vs. Supply Figure 33. Headroom at Rails vs. Source and Sink

18 6
VDD = 3.6V VDD = 5V FULL SCALE
16 VDD = 5.5V VREFOUT = 2.5V
5 TA = 25°C
14
4 3/4 SCALE
NUMBER OF DEVICES

12

3
VOUT (V)

10 MIDSCALE

8
2
1/4 SCALE
6
1
4

0 ZERO SCALE
2

0 –1
06342-029

06342-046
0.30 0.32 0.34 0.36 0.38 0.40 0.42 0.44 –30 –20 –10 0 10 20 30
IDD (mA) CURRENT (mA)
Figure 31. IDD Histogram with External Reference Figure 34. AD5627R/AD5647R/AD5667R with 2.5 V Reference, Source and
Sink Capability
14
VDD = 3.6V 4
VREFOUT = 1.25V VDD = 3V
VDD = 5.5V
12 VREFOUT = 1.25V
TA = 25°C
3
10 FULL SCALE
NUMBER OF DEVICES

8 3/4 SCALE
2
VREFOUT = 2.5V
VOUT (V)

MIDSCALE
6
1
1/4 SCALE
4

0 ZERO SCALE
2

0 –1
06342-047
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04

06342-030

–30 –20 –10 0 10 20 30

IDD (mA) CURRENT (mA)

Figure 32. IDD Histogram with Internal Reference Figure 35. AD5627R/AD5647R/AD5667R with 1.25 V Reference, Source and
Sink Capability

Rev. B | Page 14 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
0.9
TA = 25°C
0.8
VDD = 5V, VREFOUT = 2.5V
0.7
VDD = VREF = 5V
0.6
TA = 25°C
FULL-SCALE CODE CHANGE
IDD (mA)

0.5 0x0000 TO 0xFFFF

VDD = VREF = 5V
OUTPUT LOADED WITH 2kΩ
0.4 AND 200pF TO GND

0.3
VOUT = 909mV/DIV
0.2
1
0.1

06342-048
0

06342-060
512 10512 20512 30512 40512 50512 60512 TIME BASE = 4µs/DIV
CODE

Figure 36. Supply Current vs. Code Figure 39. Full-Scale Settling Time, 5 V

0.40
VDD = VREF = 5V
TA = 25°C
0.35

0.30

0.25
IDD (mA)

0.20
VDD
1
0.15

0.10 MAX(C2)
420.0mV
2
0.05 VOUT
TA = 25°C

06342-049
0 CH1 2.0V CH2 500mV M100µs 125MS/s 8.0ns/pt
06342-061

2.7 3.2 3.7 4.2 4.7 5.2 A CH1 1.28V

SUPPLY VOLTAGE (V)

Figure 37. Supply Current vs. Supply Voltage Figure 40. Power-On Reset to 0 V

0.45
SYNC
0.40 VDD = VREFIN = 5V
1
0.35 SLCK
3
VDD = VREFIN = 3V
0.30
IDD (mA)

0.25

0.20

0.15
VOUT
0.10 VDD = 5V
2
0.05
06342-050

0 CH1 5.0V CH2 500mV M400ns A CH1 1.4V

06342-063

–40 –20 0 20 40 60 80 100 CH3 5.0V

TEMPERATURE (°C)

Figure 38. Supply Current vs. Temperature Figure 41. Exiting Power-Down to Midscale

Rev. B | Page 15 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
2.538
VDD = VREF = 5V VDD = VREF = 5V
2.537
TA = 25°C TA = 25°C
2.536 DAC LOADED WITH MIDSCALE
5ns/SAMPLE NUMBER
2.535 GLITCH IMPULSE = 9.494nV
2.534 1LSB CHANGE AROUND
2.533 MIDSCALE (0x8000 TO 0x7FFF)
2.532
2.531

2µV/DIV
VOUT (V)

2.530 1
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522

06342-051
2.521

06342-058
0 50 100 150 200 250 300 350 400 450 512 4s/DIV
SAMPLE NUMBER

Figure 42. Digital-to-Analog Glitch Impulse (Negative) Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

2.498
VDD = VREF = 5V VDD = 5V
TA = 25°C VREFOUT = 2.5V
2.497 5ns/SAMPLE NUMBER TA = 25°C
ANALOG CROSSTALK = 0.424nV DAC LOADED WITH MIDSCALE

2.496

10µV/DIV
2.495
VOUT (V)

2.494

2.493

2.492

06342-052
2.491
06342-059

0 50 100 150 200 250 300 350 400 450 512 5s/DIV
SAMPLE NUMBER
Figure 43. Analog Crosstalk, External Reference Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
2.496
VDD = 3V
2.494
VREFOUT = 1.25V
2.492
TA = 25°C
2.490
DAC LOADED WITH MIDSCALE
2.488
2.486
2.484
2.482
2.480
5µV/DIV
VOUT (V)

2.478
2.476 1
2.474
2.472
2.470
2.468
2.466 VDD = 5V
2.464 VREFOUT = 2.5V
2.462 TA = 25°C
2.460 5ns/SAMPLE NUMBER
2.458
06342-053

ANALOG CROSSTALK = 4.462nV

2.456
06342-062

0 50 100 150 200 250 300 350 400 450 512 4s/DIV
SAMPLE NUMBER
Figure 44. Analog Crosstalk, Internal Reference Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference

Rev. B | Page 16 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
800 16
TA = 25°C VREF = VDD
MIDSCALE LOADED TA = 25°C
700
14

600
OUTPUT NOISE (nV/√Hz)

VDD = 3V
12
500

TIME (µs)
400 10

300
8 VDD = 5V
VDD = 5V
200 VREFOUT = 2.5V

6
100 VDD = 3V
VREFOUT = 1.25V
0 4

06342-054

06342-056
100 1k 10k 100k 1M 0 1 2 3 4 5 6 7 8 9 10
FREQUENCY (Hz) CAPACITANCE (nF)

Figure 48. Noise Spectral Density, Internal Reference Figure 50. Settling Time vs. Capacitive Load
–20 5
VDD = 5V VDD = 5V
TA = 25°C TA = 25°C
–30 0
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3V p-p
–5
–40
–10
–50
–15
(dB)

(dB)
–60
–20
–70
–25

–80 –30

–90 –35

–100 –40
06342-055

06342-057
2k 4k 6k 8k 10k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 49. Total Harmonic Distortion Figure 51. Multiplying Bandwidth

Rev. B | Page 17 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL) Output Voltage Settling Time
For the DAC, relative accuracy or integral nonlinearity is a Output voltage settling time is the amount of time it takes for
measurement of the maximum deviation, in LSBs, from a straight the output of a DAC to settle to a specified level for a ¼ to ¾
line passing through the endpoints of the DAC transfer function. full-scale input change and is measured from the rising edge of
Differential Nonlinearity (DNL) the stop condition.
Differential nonlinearity is the difference between the measured Digital-to-Analog Glitch Impulse
change and the ideal 1 LSB change between any two adjacent codes. Digital-to-analog glitch impulse is the impulse injected into the
A specified differential nonlinearity of ±1 LSB maximum ensures analog output when the input code in the DAC register changes
monotonicity. This DAC is guaranteed monotonic by design. state. It is normally specified as the area of the glitch in nV-s, and is
Zero-Code Error measured when the digital input code is changed by 1 LSB at
Zero-code error is a measurement of the output error when the major carry transition (0x7FFF to 0x8000) (see Figure 42).
zero scale (0x0000) is loaded to the DAC register. Ideally, the Digital Feedthrough
output should be 0 V. The zero-code error is always positive in Digital feedthrough is a measure of the impulse injected into
the AD5667R because the output of the DAC cannot go below the analog output of the DAC from the digital inputs of the
0 V due to a combination of the offset errors in the DAC and DAC, but is measured when the DAC output is not updated. It
the output amplifier. Zero-code error is expressed in mV. is specified in nV-s, and measured with a full-scale code change
Full-Scale Error on the data bus, that is, from all 0s to all 1s and vice versa.
Full-scale error is a measurement of the output error when full- Reference Feedthrough
scale code (0xFFFF) is loaded to the DAC register. Ideally, the Reference feedthrough is the ratio of the amplitude of the signal
output should be VDD − 1 LSB. Full-scale error is expressed in % at the DAC output to the reference input when the DAC output
of full-scale range (FSR). is not being updated. It is expressed in dB.
Gain Error Output Noise Spectral Density
Gain error is a measure of the span error of the DAC. It is the Output noise spectral density is a measurement of the internally
deviation in slope of the DAC transfer characteristic from ideal generated random noise. Random noise is characterized as a
expressed in % of FSR. spectral density. It is measured by loading the DAC to midscale
Zero-Code Error Drift and measuring noise at the output. It is measured in nV/√Hz. A
Zero-code error drift is a measurement of the change in zero- plot of noise spectral density can be seen in Figure 48.
code error with a change in temperature. It is expressed in µV/°C. DC Crosstalk
Gain Temperature Coefficient DC crosstalk is the dc change in the output level of one DAC in
Gain temperature coefficient is a measurement of the change in response to a change in the output of another DAC. It is measured
gain error with changes in temperature. It is expressed in ppm with a full-scale output change on one DAC (or soft power-down
of FSR/°C. and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
Offset Error
Offset error is a measure of the difference between VOUT (actual) DC crosstalk due to load current change is a measure of the
and VOUT (ideal) expressed in mV in the linear region of the impact that a change in load current on one DAC has to
transfer function. Offset error is measured on the AD5667R another DAC kept at midscale. It is expressed in µV/mA.
with code 512 loaded in the DAC register. It can be negative or Digital Crosstalk
positive. Digital crosstalk is the glitch impulse transferred to the output
DC Power Supply Rejection Ratio (PSRR) of one DAC at midscale in response to a full-scale code change
DC PSRR indicates how the output of the DAC is affected by (all 0s to all 1s and vice versa) in the input register of another
changes in the supply voltage. PSRR is the ratio of the change in DAC. It is measured in standalone mode and is expressed in nV-s.
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied by ±10%.

Rev. B | Page 18 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
Analog Crosstalk Multiplying Bandwidth
Analog crosstalk is the glitch impulse transferred to the output The multiplying bandwidth is a measure of the finite bandwidth
of one DAC due to a change in the output of another DAC. It is of the amplifiers within the DAC. A sine wave on the reference
measured by loading one of the input registers with a full-scale (with full-scale code loaded to the DAC) appears on the output.
code change (all 0s to all 1s and vice versa), then executing a The multiplying bandwidth is the frequency at which the output
software LDAC and monitoring the output of the DAC whose amplitude falls to 3 dB below the input.
digital code was not changed. The area of the glitch is expressed Total Harmonic Distortion (THD)
in nV-s. THD is the difference between an ideal sine wave and the
DAC-to-DAC Crosstalk attenuated version using the DAC. The sine wave is used as the
DAC-to-DAC crosstalk is the glitch impulse transferred to the reference for the DAC, and the THD is a measurement of the
output of one DAC due to a digital code change and subsequent harmonics present on the DAC output. It is measured in dB.
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa) with LDAC low while monitoring the output of
the victim channel that is at midscale. The energy of the glitch is
expressed in nV-s.

Rev. B | Page 19 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

THEORY OF OPERATION
D/A SECTION R
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs are
fabricated on a CMOS process. The architecture consists of a
R
string DAC followed by an output buffer amplifier. Figure 52
shows a block diagram of the DAC architecture.
R TO OUTPUT
VDD AMPLIFIER
OUTPUT
AMPLIFIER
GAIN = +2
REF (+)
DAC RESISTOR
REGISTER VOUT
STRING
REF (–) R

06342-032
GND
R
Figure 52. DAC Architecture

06342-033
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by Figure 53. Resistor String

D INTERNAL REFERENCE
VOUT = VREFIN ×  N  The AD5627R/AD5647R/AD5667R feature an on-chip reference.
2 
Versions without the R suffix require an external reference. The
The ideal output voltage when using the internal reference is
on-chip reference is off at power-up and enabled via a write to a
given by
control register. See the Internal Reference Setup section for details.
D
VOUT = 2 × VREFOUT ×  N  Versions packaged in a 10-lead LFCSP package have a 1.25 V
2  reference, giving a full-scale output of 2.5 V. These devices can
where: operate with a VDD supply of 2.7 V to 5.5 V. Versions packaged
in a 10-lead MSOP package have a 2.5 V reference, giving a full-
D is the decimal equivalent of the binary code that is loaded to scale output of 5 V. The devices are functional with a VDD supply
the DAC register: of 4.5 V to 5.5 V, but with a VDD supply of less than 5 V, the output
0 to 4095 for AD5627R/AD5627 (12-bit). is clamped to VDD. See the Ordering Guide for a full list of
0 to 16,383 for AD5647R (14-bit). models. The internal reference associated with each device is
0 to 65,535 for AD5667R/AD5667 (16-bit). available at the VREFOUT pin.
N is the DAC resolution. A buffer is required if the reference output drives external loads.
When using the internal reference, it is recommended that a
RESISTOR STRING
100 nF capacitor be placed between the reference output and
The resistor string is shown in Figure 53. It is simply a string of GND for reference stability.
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off EXTERNAL REFERENCE
to be fed into the output amplifier. The voltage is tapped off by The AD5627/AD5667 require an external reference, which is
closing one of the switches connecting the string to the amplifier. applied at the VREFIN pin. The VREFIN pin on the AD5627R/
Because it is a string of resistors, it is guaranteed monotonic. AD5647R/AD5667R allows the use of an external reference if
the application requires it. The default condition of the on-chip
OUTPUT AMPLIFIER
reference is off at power-up. All devices can be operated from a
The output buffer amplifier can generate rail-to-rail voltages on single 2.7 V to 5.5 V supply.
the output, which gives an output range of 0 V to VDD. It can drive a
load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 33
and Figure 34. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale
settling time of 7 µs.

Rev. B | Page 20 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
SERIAL INTERFACE WRITE OPERATION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have 2- When writing to the AD5627R/AD5647R/AD5667R,
wire I2C-compatible serial interfaces (refer to I2C-Bus AD5627/AD5667, the user must begin with a start command
Specification, Version 2.1, January 2000, available from Philips followed by an address byte (R/W= 0), after which the DAC
Semiconductor). The AD5627R/AD5647R/AD5667R, acknowledges that it is prepared to receive data by pulling SDA
AD5627/AD5667 can be connected to an I2C bus as a slave low. The AD5627R/AD5647R/AD5667R, AD5627/AD5667
device, under the control of a master device. See Figure 3 for a requires two bytes of data for the DAC and a command byte
timing diagram of a typical write sequence. that controls various DAC functions. Three bytes of data must
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 support therefore be written to the DAC, the command byte followed by
standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz) the most significant data byte and the least significant data byte,
data transfer modes. High speed operation is only available on as shown in Figure 54. All these data bytes are acknowledged by
select models. See the Ordering Guide for a full list of models. the AD5627R/AD5647R/AD5667R, AD5627/AD5667. A stop
Support is not provided for 10-bit addressing and general call condition follows.
addressing. READ OPERATION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 each have When reading data back from the AD5627R/AD5647R/AD5667R,
a 7-bit slave address. The five MSBs are 00011 and the two LSBs AD5627/AD5667, the user begins with a start command
(A1, A0) are set by the state of the ADDR address pin. The followed by an address byte (R/W = 1), after which the DAC
facility to make hardwired changes to ADDR allows the user to acknowledges that it is prepared to transmit data by pulling
incorporate up to three of these devices on one bus, as outlined SDA low. Three bytes of data are then read from the DAC,
in Table 7. which are acknowledged by the master, as shown in Figure 55.
A stop condition follows.
Table 7. Device Address Selection
ADDR Pin Connection A1 A0 HIGH SPEED MODE
VDD 0 0 The AD5627RBRMZ and the AD5667RBRMZ offer high speed
No Connection 1 0 serial communication with a clock frequency of 3.4 MHz. See
GND 1 1 the Ordering Guide for details.
High speed mode communication commences after the master
The 2-wire serial bus protocol operates as follows:
addresses all devices connected to the bus with the Master Code
1. The master initiates data transfer by establishing a start 00001XXX to indicate that a high speed mode transfer is to begin
condition when a high-to-low transition on the SDA line (see Figure 56). No device connected to the bus is permitted to
occurs while SCL is high. The following byte is the address acknowledge the high speed master code. Therefore, the code is
byte, which consists of the 7-bit slave address. The slave followed by a no acknowledge. The master must then issue a
address corresponding to the transmitted address responds repeated start followed by the device address. The selected
by pulling SDA low during the 9th clock pulse (this is termed device then acknowledges the address.
the acknowledge bit). At this stage, all other devices on the All devices continue to operate in high speed mode until the
bus remain idle while the selected device waits for data to master issues a stop condition. When the stop condition is
be written to, or read from, the shift register. issued, the devices return to standard/fast mode. The device
2. Data is transmitted over the serial bus in sequences of nine
also returns to standard/fast mode when CLR is activated while
clock pulses (eight data bits followed by an acknowledge
the device is in high speed mode.
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
3. When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the 9th clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, and then high during the 10th
clock pulse to establish a stop condition.

Rev. B | Page 21 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
1 9 1 9

SCL

SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
START BY ACK. BY ACK. BY
MASTER AD56x7 AD56x7
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND BYTE
1 9 1 9
SCL
(CONTINUED)

SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(CONTINUED)
ACK. BY ACK. BY STOP BY
AD56x7 AD56x7 MASTER
FRAME 3 FRAME 4

06342-103
MOST SIGNIFICANT LEAST SIGNIFICANT
DATA BYTE DATA BYTE

Figure 54. I2C Write Operation

1 9 1 9

SCL

SDA 0 0 0 1 1 A1 A0 R/W DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
START BY ACK. BY ACK. BY
MASTER AD56x7 MASTER
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND BYTE
1 9 1 9
SCL
(CONTINUED)

SDA DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
(CONTINUED)
ACK. BY NO ACK. STOP BY
MASTER MASTER
FRAME 3 FRAME 4

06342-104
MOST SIGNIFICANT LEAST SIGNIFICANT
DATA BYTE DATA BYTE
Figure 55. I2C Read Operation
FAST MODE HIGH-SPEED MODE
1 9 1 9
SCL

SDA 0 0 0 0 1 X X X 0 0 0 1 1 A1 A0 R/W

START BY NO ACK SR ACK. BY

MASTER AD56x7 06342-105
HS-MODE
MASTER CODE SERIAL BUS
ADDRESS BYTE
Figure 56. Placing the AD5627RBRMZ-2/AD5667RBRMZ-2 in High Speed Mode

Rev. B | Page 22 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
INPUT SHIFT REGISTER Table 9. DAC Address Command
The input shift register is 24 bits wide. Data is loaded into the A2 A1 A0 ADDRESS (n)
device as a 24-bit word under the control of a serial clock input, 0 0 0 DAC A
SCL. The timing diagram for this operation is shown in Figure 3. 0 0 1 DAC B
The 8 MSBs make up the command byte. DB23 is reserved and 1 1 1 Both DACs
should always be set to 0 when writing to the device. DB22 (S)
selects multiple byte operation The next three bits are the LDAC FUNCTION
command bits (C2, C1, C0) that control the mode of operation of
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs
the device. See Table 8 for details. The last 3 bits of first byte are
have double-buffered interfaces consisting of two banks of
the address bits (A2, A1, A0). See Table 9 for details. The rest of
registers, input registers and DAC registers. The input registers
the bits are the 16-, 14-, 12-bit data word. The data word
are connected directly to the input shift register, and the digital
comprises the 16-, 14-, 12-bit input code followed by two or four
code is transferred to the relevant input register on completion
don’t cares for the AD5647R and the AD5627R/AD5627,
of a valid write sequence. The DAC registers contain the digital
respectively (see Figure 59 through Figure 61).
codes used by the resistor strings.
MULTIPLE BYTE OPERATION
Access to the DAC registers is controlled by the LDAC pin.
Multiple byte operation is supported on the AD5627R/AD5647R/ When the LDAC pin is high, the DAC registers are latched and
AD5667R, AD5627/AD5667. A 2-byte operation is useful for the input registers can change state without affecting the contents
applications that require fast DAC updating and do not need to of the DAC registers. When LDAC is brought low, however, the
change the command byte. The S bit (DB22) in the command DAC registers become transparent and the contents of the input
register can be set to 1 for 2-byte mode of operation (see Figure 57). registers are transferred to them. The double-buffered interface
For standard 3-byte and 4-byte operation, the S bit (DB22) in is useful if the user requires simultaneous updating of all DAC
the command byte should be set to 0 (see Figure 58). outputs. The user can write to one of the input registers
BROADCAST MODE individually and then, by bringing LDAC low when writing to
Broadcast addressing is supported on the AD5627R/AD5647R/ the other DAC input register, all outputs update simultaneously.
AD5667R, AD5627/AD5667. Broadcast addressing can be These devices each contain an extra feature whereby a DAC register
synchronously update or power down multiple AD5627R/ is not updated unless the input register has been updated since
AD5647R/AD5667R, AD5627/AD5667 devices. Using the the last time LDAC was brought low. Normally, when LDAC is
broadcast address, the AD5627R/AD5647R/AD5667R, AD5627/ brought low, the DAC registers are filled with the contents of the
AD5667 responds regardless of the states of the address pins. input registers. In the case of the AD5627R/AD5647R/AD5667R,
Broadcast is supported only in write mode. The AD5627R/ AD5627/AD5667, the DAC register updates only if the input
AD5647R/AD5667R, AD5627/AD5667 broadcast address is register has changed since the last time the DAC register was
00010000. updated, thereby removing unnecessary digital crosstalk.
Table 8. Command Definition The outputs of all DACs can be simultaneously updated, using
C2 C1 C0 Command the hardware LDAC pin.
0 0 0 Write to input register n
0 0 1 Update DAC register n
0 1 0 Write to input register n, update all (software LDAC)
0 1 1 Write to and update DAC channel n
1 0 0 Power up/power down
1 0 1 Reset
1 1 0 LDAC register setup
1 1 1 Internal reference setup (on/off )

Rev. B | Page 23 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
BLOCK 1 BLOCK 2 BLOCK n
S=1 S=1 S=1

06342-106
SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT STOP
ADDRESS BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE DATA BYTE

Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1)
BLOCK 1 BLOCK 2 BLOCK n
S=0 S=0 S=0

06342-107
SLAVE COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP
ADDRESS BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE BYTE DATA BYTE DATA BYTE

Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0)
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S C2 C1 C0 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SELECTION
RESERVED

BYTE

COMMAND DAC ADDRESS DAC DATA DAC DATA

06342-108
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S C2 C1 C0 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

SELECTION
RESERVED

BYTE

COMMAND DAC ADDRESS DAC DATA DAC DATA

06342-109
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

Figure 60. AD5647R Input Shift Register (14-Bit DAC)

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R S C2 C1 C0 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X
SELECTION
RESERVED

BYTE

COMMAND DAC ADDRESS DAC DATA DAC DATA

06342-110
COMMAND BYTE DATA HIGH BYTE DATA LOW BYTE

Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC)

Rev. B | Page 24 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
Synchronous LDAC POWER-DOWN MODES
The DAC registers are updated after new data is read in. LDAC Command 100 is reserved for the power-up/down function.
can be permanently low or pulsed. The power-up/down modes are programmed by setting Bit DB5
Asynchronous LDAC and Bit DB4. This defines the output state of the DAC amplifier,
as shown in Table 11. Bit DB1and Bit DB0 determine to which
The outputs are not updated at the same time that the input
DAC or DACs the power-up/down command is applied. Setting
registers are written to. When LDAC goes low, the DAC
one of these bits to 1 applies the power-up/down state defined by
registers are updated with the contents of the input register.
DB5 and DB4 to the corresponding DAC. If a bit is 0, the state
The LDAC register gives the user full flexibility and control over of the DAC is unchanged. Figure 65 shows the contents of the
the hardware LDAC pin. This register allows the user to select input shift register for the power up/down command.
which combination of channels to simultaneously update when When Bit DB5 and Bit DB4 are set to 0, the deice works normally
the hardware LDAC pin is executed. Setting the LDAC bit with the normal power consumption of 400 μA at 5 V. However,
register to 0 for a DAC channel means that the update of this for the three power-down modes, the supply current falls to 480 nA
channel is controlled by the LDAC pin. If this bit is set to 1, this at 5 V. Not only does the supply current fall, but the output stage is
channel synchronously updates, that is, the DAC register is also internally switched from the output of the amplifier to a
updated after new data is read in, regardless of the state of the resistor network of known values. This allows the output
LDAC pin. It effectively sees the LDAC pin as being pulled low. impedance of the device to be known while the device is in
See Table 10 for the LDAC register mode of operation. This power-down mode. The outputs can either be connected
flexibility is useful in applications when the user wants to internally to GND through a 1 kΩ or 100 kΩ resistor, or left
simultaneously update select channels while the rest of the open-circuited (three-state) as shown in Figure 62.
channels are synchronously updating.
Table 11. Modes of Operation for the
Writing to the DAC using Command 110 loads the 2-bit LDAC AD5627R/AD5647R/AD5667R, AD5627/AD5667
register [DB1:DB0]. The default for each channel is 0, that is, DB5 DB4 Operating Mode
the LDAC pin works normally. Setting the bits to 1 means the 0 0 Normal operation
DAC register is updated, regardless of the state of the LDAC Power-down modes
pin. See Figure 63 for contents of the input shift register during 0 1 1 kΩ pull-down to GND
the LDAC register setup command. 1 0 100 kΩ pull-down to GND
1 1 Three-state, high impedance
Table 10. LDAC Register Mode of Operation:
Load DAC Register
LDAC Bits RESISTOR
LDAC Pin LDAC Operation AMPLIFIER VOUT
(DB1 to DB0) STRING DAC

0 1/0 Determined by LDAC pin.

1 x = don’t care The DAC registers are updated
after new data is read in. POWER-DOWN
CIRCUITRY RESISTOR
NETWORK

06342-038
Figure 62. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when power-
down mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for VDD = 5 V.
R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X 1 1 0 A2 A1 A0 X X X X X X X X X X X X X X DACB DACA
RESERVED

DON’T
CARE

COMMAND DAC ADDRESS DON’T CARE DON’T CARE

(DON’T CARE)
06342-111

DAC SELECT
(0 = LDAC PIN ENABLED)

Figure 63. LDAC Setup Command

Rev. B | Page 25 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
POWER-ON RESET AND SOFTWARE RESET CLEAR PIN (CLR)
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 contain a The AD5627R/AD5647R/AD5667R, AD5627/AD5667 has an
power-on reset circuit that controls the output voltage during asynchronous clear input. The CLR input is falling edge sensitive.
power-up. The device powers up to 0 V and the output remains While CLR is low, all LDAC pulses are ignored. When CLR is
powered up at this level until a valid write sequence is made to activated, zero scale is loaded to all input and DAC registers.
the DAC. This is useful in applications where it is important to This clears the output to 0 V. The device exits clear code mode
know the state of the output of the DAC while it is in the process on the on the falling edge of the ninth clock pulse of the last
of powering up. Any events on LDAC or CLR during power-on byte of valid write. If CLR is activated during a write sequence,
reset are ignored. the write is aborted. If CLR is activated during high speed mode,
There is also a software reset function. Command 101 is the the device exits high speed mode to standard/fast mode.
software reset command. The software reset command contains
INTERNAL REFERENCE SETUP (R VERSIONS)
two reset modes that are software programmable by setting Bit DB0
in the input shift register. The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
Table 12 shows how the state of the bit corresponds to the setting DB0 in the input shift register. Table 13 shows how the
software reset modes of operation of the devices. Figure 64 state of the bit corresponds to the mode of operation. See Figure 66
shows the contents of the input shift register during the for the contents of the input shift register during the internal
software reset mode of operation. reference setup command.
After a full software reset (DB0 = 1), there must be a short time
delay, approximately 5 µs, to complete the reset. During the Table 13. Reference Setup Command
reset, a low pulse can be observed on the CLR line. If the next DB0 Action
I2C transaction commences before the CLR line returns high, 0 Internal reference off (default)
that I2C transaction is ignored. 1 Internal reference on

Table 12. Software Reset Modes for the

AD5627R/AD5647R/AD5667R, AD5627/AD5667
DB0 Registers Reset to Zero
0 DAC register
Input shift register
1 (Power-On Reset) DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register

Rev. B | Page 26 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667
X S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X 1 0 1 X X X X X X X X X X X X X X X X X X RST
RESERVED

RESET
MODE
DON’T
CARE

COMMAND DAC ADDRESS DON’T CARE DON’T CARE

(DON’T CARE)

06342-113
Figure 64. Software Reset Command

R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X 1 0 0 X X X X X X X X X X X X X PD1 PD0 X X DACB DACA

RESERVED

DON’T
CARE

COMMAND DAC ADDRESS DON’T CARE DON’T CARE POWER- DON’T CARE
(DON’T CARE) DOWN MODE

06342-112
DAC SELECT
(1 = DAC SELECTED)

Figure 65. Power Up/Down Command

R S C2 C1 C0 A2 A1 A0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 X 1 1 1 X X X X X X X X X X X X X X X X X X REF

REFERENCE
RESERVED

MODE
DON’T
CARE

COMMAND DAC ADDRESS DON’T CARE DON’T CARE

(DON’T CARE)

06342-114
Figure 66. Reference Setup Command

Rev. B | Page 27 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet

APPLICATION INFORMATION
USING A REFERENCE AS A POWER SUPPLY FOR THE This is an output voltage range of ±5 V, with 0x0000 corre-
AD5627R/AD5647R/AD5667R, AD5627/AD5667 sponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
Because the supply current required by the AD5627R/AD5647R/
R2 = 10kΩ
AD5667R, AD5627/AD5667 is extremely low, an alternative option
is to use a voltage reference to supply the required voltage to the +5V
R1 = 10kΩ
device (see Figure 67). This is especially useful if the power supply
is quite noisy, or if the system supply voltages are at some value AD820/ VO
±5V
OP295
other than 5 V or 3 V, for example, 15 V. The voltage reference +5V VDD VOUT
outputs a steady supply voltage for the AD5627R/AD5647R/ 10µF 0.1µF AD5627R/
–5V
AD5647R/
AD5667R, AD5627/AD5667. If the low dropout REF195 is used, it AD5667R/
must supply 450 µA of current to the AD5627R/AD5647R/ AD5627/
AD5667
AD5667R, AD5627/AD5667 with no load on the output of the
GND SCL SDA
DAC. When the DAC output is loaded, the REF195 must also
supply the current to the load. The total current required (with
a 5 kΩ load on the DAC output) is

06342-044
2-WIRE
SERIAL
450 µA + (5 V/5 kΩ) = 1.45 mA INTERFACE

Figure 68. Bipolar Operation with the AD5627R/AD5647R/AD5667R,

The load regulation of the REF195 is typically 2 ppm/mA, AD5627/AD5667
resulting in a 2.9 ppm (14.5 µV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error. POWER SUPPLY BYPASSING AND GROUNDING
15V When accuracy is important in a circuit, it is helpful to carefully
5V consider the power supply and ground return layout on the board.
REF195
The printed circuit board containing the AD5627R/AD5647R/
AD5667R, AD5627/AD5667 should have separate analog and
VDD digital sections, each having its own area of the board. If the
SCL AD5627R/
2-WIRE
SERIAL AD5647R/
VOUT = 0V TO 5V
AD5627R/AD5647R/AD5667R, AD5627/AD5667 are in a system
INTERFACE
SDA AD5667R/ where other devices require an AGND to DGND connection, the
AD5627/
AD5667 connection should be made at one point only. This ground point
GND should be as close as possible to the AD5627R/AD5647R/
06342-043

AD5667R, AD5627/AD5667.
Figure 67. REF195 as Power Supply to the AD5627R/AD5647R/AD5667R, The power supply to the AD5627R/AD5647R/AD5667R,
AD5627/AD5667 AD5627/AD5667 should be bypassed with 10 µF and 0.1 µF
BIPOLAR OPERATION USING THE capacitors. The capacitors should be located as close as possible
to the device, with the 0.1 µF capacitor ideally right up against the
AD5627R/AD5647R/AD5667R, AD5627/AD5667
device. The 10 µF capacitor should be the tantalum bead type. It
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 has been is important that the 0.1 µF capacitor have low effective series
designed for single-supply operation, but a bipolar output range resistance (ESR) and effective series inductance (ESI), for example,
is also possible using the circuit in Figure 68. The circuit gives an common ceramic types of capacitors. This 0.1 µF capacitor
output voltage range of ±5 V. Rail-to-rail operation at the amplifier provides a low impedance path to ground for high frequencies
output is achieved using an AD820 or an OP295 as the output caused by transient currents due to internal logic switching.
amplifier.
The power supply line itself should have as large a trace as
The output voltage for any input code can be calculated as possible to provide a low impedance path and to reduce glitch
follows: effects on the supply line. Clocks and other fast switching
  D   R1 + R2   R2  digital signals should be shielded from other devices of the
VO = V DD ×  ×   − V DD ×   board by digital ground. Avoid crossover of digital and analog
  65,536   R1   R1 
signals if possible. When traces cross on opposite sides of the
where D represents the input code in decimal (0 to 65535). board, ensure that they run at right angles to each other to
With VDD = 5 V, R1 = R2 = 10 kΩ, reduce feedthrough effects through the board. The best board
 10 × D  layout technique is the microstrip technique where the
VO =  −5 V component side of the board is dedicated to the ground plane
 65,536 
only and the signal traces are placed on the solder side.
However, this is not always possible with a two-layer board.
Rev. B | Page 28 of 30
Data Sheet AD5627R/AD5647R/AD5667R, AD5627/AD5667

OUTLINE DIMENSIONS
2.48
2.38
3.10
2.23
3.00 SQ
2.90 0.50 BSC
6 10

PIN 1 INDEX EXPOSED 1.74

AREA PAD
1.64
0.50 1.49
0.40
0.30
5 1 0.20 MIN
TOP VIEW BOTTOM VIEW PIN 1
INDICATOR
(R 0.15)
0.80 FOR PROPER CONNECTION OF
0.75 0.05 MAX THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
0.70 0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08

02-05-2013-C
0.30
PLANE 0.25 0.20 REF
0.20

Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90

10 6 5.15
3.10 4.90
3.00 4.65
2.90 1
5

PIN 1
IDENTIFIER

0.50 BSC

0.95 15° MAX

0.85 1.10 MAX
0.75
0.70
0.15 6° 0.23
0.30 0.55
0.05 0° 0.13 0.40
COPLANARITY 0.15
0.10
091709-A

COMPLIANT TO JEDEC STANDARDS MO-187-BA

Figure 70. 10-Lead Mini Small Outline Package [MSOP]

(RM-10)
Dimensions shown in millimeters

Rev. B | Page 29 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667 Data Sheet
ORDERING GUIDE
Temperature On-Chip Max I2C Package Package
Model 1 Range Accuracy Reference Speed Description Option Branding
AD5627BCPZ-R2 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 DA1
AD5627BCPZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 DA1
AD5627BRMZ −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1
AD5627BRMZ-REEL7 −40°C to +105°C ±1 LSB INL None 400 kHz 10-Lead MSOP RM-10 DA1
AD5627RBCPZ-R2 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J
AD5627RBCPZ-REEL7 −40°C to +105°C ±1 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9J
AD5627RBRMZ-1 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7
AD5627RBRMZ-1REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA7
AD5627RBRMZ-2 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8
AD5627RBRMZ-2REEL7 −40°C to +105°C ±1 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA8
AD5647RBCPZ-R2 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9G
AD5647RBCPZ-REEL7 −40°C to +105°C ±4 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D9G
AD5647RBRMZ −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G
AD5647RBRMZ-REEL7 −40°C to +105°C ±4 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 D9G
AD5667BCPZ-R2 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z
AD5667BCPZ-REEL7 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead LFCSP_WD CP-10-9 D9Z
AD5667BRMZ −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z
AD5667BRMZ-REEL7 −40°C to +105°C ±12 LSB INL None 400 kHz 10-Lead MSOP RM-10 D9Z
AD5667RBCPZ-R2 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X
AD5667RBCPZ-REEL7 −40°C to +105°C ±12 LSB INL 1.25 V 400 kHz 10-Lead LFCSP_WD CP-10-9 D8X
AD5667RBRMZ-1 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5
AD5667RBRMZ-1REEL7 −40°C to +105°C ±12 LSB INL 2.5 V 400 kHz 10-Lead MSOP RM-10 DA5
AD5667RBRMZ-2 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6
AD5667RBRMZ-2REEL7 −40°C to +105°C ±12 LSB INL 2.5 V 3.4 MHz 10-Lead MSOP RM-10 DA6
EVAL-AD5667RSDZ Evaluation Board
1
Z = RoHS Compliant Part.

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06342-0-9/16(B)

Rev. B | Page 30 of 30