COAL Long Question Answers
Q1. Segmented vs Linear Memory Organization
Segmented Memory Model (8086):
• Intel 8086 uses segmentation to access memory beyond 64KB (since address bus = 20
bits → 1 MB memory).
• Memory is divided into segments of 64KB each.
• Segments: CS (Code), DS (Data), SS (Stack), ES (Extra).
• A memory location is addressed using Segment:Offset.
• Physical Address = (Segment × 10h) + Offset
Example:
• Segment Register = 1000h, Offset = 2000h
• Physical Address = (1000h × 10h) + 2000h
= 10000h + 2000h
= 12000h
Linear Memory Model:
• Every address is directly referenced as a single address space (no segmentation).
• Simpler to program but not supported by 8086.
• Modern processors (32/64-bit) use linear or flat memory.
Comparison:
Segmented Model Linear Model
Complex addressing Simple addressing
Allows modularity (code, data, stack separated) Everything in one space
Used in 8086 Used in modern systems
Q2. Registers & Flags in 8086
Registers:
1. General Purpose Registers (16-bit, can be split into 8-bit high/low):
• AX (Accumulator), BX (Base), CX (Counter), DX (Data).
• Example: AX = AH (high byte) + AL (low byte).
2. Segment Registers (16-bit):
• CS (Code), DS (Data), SS (Stack), ES (Extra).
3. Pointer & Index Registers:
• SP (Stack Pointer), BP (Base Pointer), SI (Source Index), DI (Destination Index).
4. Instruction Pointer (IP): Holds address of next instruction.
FLAGS Register (16-bit, shows CPU status):
• Carry Flag (CF): Set if arithmetic carry/borrow occurs.
• Zero Flag (ZF): Set if result = 0.
• Sign Flag (SF): Set if result is negative.
• Overflow Flag (OF): Set if signed overflow occurs.
• Parity Flag (PF): Set if result has even number of 1s.
Q3. Categories of Instructions
1. Data Transfer Instructions: Move data between registers/memory.
• Example: MOV AX, BX
2. Arithmetic Instructions: Perform addition, subtraction, etc.
• Example: ADD AX, BX
3. Logical Instructions: Perform AND, OR, XOR, NOT.
• Example: AND AL, BL
4. Program Control Instructions: Alter program flow.
• Example: JZ LABEL, CALL SUBROUTINE, RET
Q4. Stack & Subroutines
Stack:
• Works on LIFO (Last In, First Out) principle.
• Controlled by SS (Stack Segment) and SP (Stack Pointer).
• PUSH → SP decreases, value stored in stack.
• POP → Value retrieved, SP increases.
Diagram:
Top → [Data Last Pushed]
[Previous Data]
Bottom → [Oldest Data]
Subroutine Example (Add Two Numbers):
MOV AX, 05H ; first number
MOV BX, 03H ; second number
CALL ADDNUM ; call subroutine
HLT
ADDNUM PROC
ADD AX, BX ; add AX + BX
RET ; return to main
ADDNUM ENDP
Q5. Interrupts
Definition: Signal to CPU that temporarily halts current execution to handle a task.
Types:
• Hardware Interrupts: From external devices (keyboard, timer).
• Software Interrupts: Triggered by program using INT instruction.
Steps of Interrupt Handling:
1. CPU saves current state (IP, FLAGS).
2. Jumps to Interrupt Vector Table.
3. Executes ISR (Interrupt Service Routine).
4. Returns to program with IRET.
Program – Print HELLO using INT 21h:
MOV AH, 09H
LEA DX, MSG
INT 21H
MOV AH, 4CH
INT 21H
MSG DB "HELLO$"
Q6. Addressing Modes with Examples
1. Immediate: Operand is constant.
• MOV AX, 05H
2. Register: Operand in register.
• MOV AX, BX
3. Direct: Operand from memory address.
• MOV AX, [1234H]
4. Indirect: Address stored in register.
• MOV AX, [BX]
5. Indexed: Uses base + displacement.
• MOV AX, [SI+05H]
Q7. Program – Add Two Numbers (User Input)
MOV AH, 01H ; input first number
INT 21H
SUB AL, 30H ; convert ASCII to number
MOV BL, AL ; store first number
MOV AH, 01H ; input second number
INT 21H
SUB AL, 30H
ADD BL, AL ; BL = sum
ADD BL, 30H ; convert back to ASCII
MOV DL, BL
MOV AH, 02H ; display result
INT 21H
MOV AH, 4CH
INT 21H
Q8. Program – Display String
MOV AH, 09H
LEA DX, MSG
INT 21H
MOV AH, 4CH
INT 21H
MSG DB "WELCOME TO GCUF$"
• 09H function → Display string until $ is found.
Q9. Conditional Jumps & Loop Example
Conditional Jumps:
• JZ – Jump if Zero flag = 1
• JNZ – Jump if Zero flag = 0
• JC – Jump if Carry = 1
• JNC – Jump if Carry = 0
• JL – Jump if Less (signed)
• JG – Jump if Greater (signed)
Program – Print Numbers 1 to 10:
MOV CX, 0AH ; counter = 10
MOV BL, 1 ; start number = 1
PRINT_LOOP:
MOV DL, BL
ADD DL, 30H ; convert to ASCII
MOV AH, 02H
INT 21H
INC BL ; next number
LOOP PRINT_LOOP
MOV AH, 4CH
INT 21H
Q10. Importance of Assembly in Real-time Applications
• Efficiency: Direct hardware access, very fast.
• Compact Code: Less memory usage, important in microcontrollers.
• Precise Timing: Useful in real-time systems (e.g., robotics).
• Device Drivers: Assembly is needed for direct hardware communication.
• Embedded Systems: Limited resources → Assembly still preferred.
• Robotics & Control Systems: Require predictable execution speed.
Conclusion:
Even though high-level languages exist, Assembly is essential where performance, size, and
timing are critical.
1) Segmented vs Linear Memory + Physical
Addressing (with sums) — (Full answer)
Short idea (one line):
• Linear memory: one flat list of addresses.
• Segmented memory: memory divided into segments; an address is
Segment:Offset → physical address = Segment × 16 + Offset.
Derive formula:
Segment register contains a 16-bit value. The physical base address = Segment << 4 (i.e.
multiply by 16). Add offset to get the physical address:
Physical=(Segment×16)+Offset
Worked examples (show steps):
1. 3000:0040
• 3000H × 10H = 30000H
• 30000H + 0040H = 30040H → Physical = 30040H
2. 74F0:2123
• 74F0H × 10H = 74F00H
• 74F00H + 2123H = 77023H → Physical = 77023H
3. FFFF:0010
• FFFFH × 10H = FFFF0H
• FFFF0H + 0010H = 100000H → Physical = 100000H
• Note: 8086 has a 20-bit physical address bus (max FFFFFH). 100000H wraps
around modulo 1 MB to 00000H. Mention this wrap if asked about overflow.
Comparison (short table):
Feature Segmented Linear
Addressing Segment:Offset Single address
Flexibility Allows many 64KB segments Simpler
Complexity More math (segment*16 + offset) Less math
Needed to address 1MB with 16-bit
Use (8086) Used in flat address CPUs (more modern)
regs
2) Registers & FLAGS (list + evaluate after
ops)
Register groups (short list):
• General: AX, BX, CX, DX (AX = accumulator)
• Pointer/Index: SP (stack pointer), BP (base pointer), SI (source index), DI (destination
index)
• Segment: CS, DS, SS, ES
• Instruction pointer: IP
• Flags register: status bits (CF, PF, AF, ZF, SF, TF, IF, DF, OF, …)
FLAGS (important ones):
• CF (Carry Flag) — unsigned carry/borrow.
• ZF (Zero Flag) — 1 if result = 0.
• SF (Sign Flag) — 1 if result negative (most significant bit = 1).
• OF (Overflow Flag) — signed overflow (result doesn't fit signed range).
• PF (Parity Flag) — parity of low byte.
Evaluate flags — 3 sample ops (showing how to write in answer):
1. ADD AL, 01H when AL = 7FH
• 7FH + 01H = 80H (binary 1000 0000)
• CF = 0 (no unsigned carry out of MSB)
• ZF = 0 (result ≠ 0)
• SF = 1 (MSB = 1 → negative in signed)
• OF = 1 (signed overflow: +127 → -128)
• Answer: CF=0, ZF=0, SF=1, OF=1
2. SUB AL, BL where AL=40H (64), BL=50H (80)
• 64 - 80 = -16 → result F0H
• CF = 1 (borrow happened)
• ZF = 0 (result not zero)
• SF = 1 (negative)
• OF = 0 (no signed overflow here)
• Answer: CF=1, ZF=0, SF=1, OF=0
3. INC AL when AL = 7FH
• 7FH + 1 = 80H
• ZF = 0, SF = 1
• OF = 1 (7F → 80 crosses signed positive→negative boundary)
• CF unchanged by INC (note: INC does not affect CF)
• Answer: ZF=0, SF=1, OF=1, CF unchanged
Always explain rules: ADD affects CF/OF/ZF/SF; INC affects OF/ZF/SF but not CF;
SUB affects CF as borrow.
3) Addressing Modes with Examples
(identify + effective address)
Short definitions & examples:
1. Immediate: operand is a constant value.
• MOV AX, 5 → immediate mode (value 5 used directly).
2. Register: operand is in a register.
• MOV AX, BX → register mode.
3. Direct (Absolute): memory at fixed address.
• MOV AX, [2000H] → direct mode; effective address 2000H.
4. Register-Indirect: register contains memory address.
• MOV AX, [BX] → read from memory at address in BX.
5. Indexed: address formed with index register + displacement.
• MOV AX, [SI+10H] → effective address = SI + 10H.
6. Based+Indexed: combine base and index: [BX+SI+disp]
• MOV AX, [BX+SI] → effective address = BX + SI.
Exam example block (identify):
• MOV AX, 5 → Immediate.
• MOV AX, BX → Register.
• MOV AX, [2000H] → Direct (effective 2000H).
• MOV AX, [BX] → Register-indirect (address stored in BX).
• MOV AX, [BX+SI] → Based+Indexed (effective = BX+SI).
• MOV AX, [SI+10H] → Indexed with displacement.
4) String Instructions & REP (theory +
micro-routines)
Short theory (one line each):
• MOVSB — move byte from DS:SI → ES:DI, then SI/DI adjust
(auto-increment/decrement according to DF).
• CMPSB — compare byte at DS:SI with ES:DI, set flags accordingly, advance SI/DI.
• LODSB — load byte from DS:SI → AL.
• STOSB — store AL → ES:DI.
• SCASB — compare AL with byte at ES:DI.
• REP / REPE / REPNE — repeat string instruction CX times; REPE/REPZ repeats while
ZF=1, REPNE/REPNZ while ZF=0.
Copy N bytes routine (use CX count):
; Copy CX bytes from DS:SI to ES:DI
CLD ; direction forward (SI/DI increment)
REP MOVSB ; repeat MOVSB CX times
Explain: DS:SI source, ES:DI dest, CX = count. REP MOVSB copies CX bytes and auto-
increments SI & DI.
Compare two strings (return ZF=1 if equal):
; Compare CX bytes at DS:SI and ES:DI
CLD
REPE CMPSB ; compare until mismatch or CX=0
; after REPE CMPSB:
; if CX = 0 and no mismatch → strings equal (ZF=1)
; if mismatch occurred → ZF = 0
5) Interrupts (Hardware vs Software) + ISR
flow + INT 21h demo
Short definition:
• Interrupt: event that suspends normal execution to handle important task.
• Hardware interrupt: from device (timer, keyboard).
• Software interrupt: initiated by program (INT n).
ISR flow (steps):
1. CPU completes current instruction.
2. CPU pushes FLAGS, CS, IP onto stack (saves state).
3. CPU loads new CS:IP from interrupt vector table (jumps to ISR).
4. ISR runs (service routine).
5. ISR executes IRET → CPU pops IP, CS, FLAGS and resumes.
Small DOS assembly program — print HELLO and exit:
.MODEL SMALL
.STACK 100h
.DATA
MSG DB 'HELLO$'
.CODE
MAIN PROC
MOV AX,@DATA
MOV DS,AX
LEA DX,MSG ; DX = address of MSG
MOV AH,09h ; DOS print string
INT 21h
MOV AH,4Ch ; DOS terminate
XOR AL,AL
INT 21h
MAIN ENDP
END MAIN
Comments: AH=09h prints $ terminated string; AH=4Ch exits.
6) Stack & Subroutines (CALL/RET) +
AddTwo via Stack Frame
Short concept: Stack = LIFO. CALL pushes return IP, RET pops it. Use BP to create a stack
frame for parameters/local vars.
AddTwo(a,b) — pass parameters on stack (caller cleans):
.MODEL SMALL
.STACK 100h
.DATA
A DW 0012h
B DW 0009h
SUM DW 0
.CODE
MAIN PROC
MOV AX,@DATA
MOV DS,AX
PUSH WORD PTR B ; push second param
PUSH WORD PTR A ; push first param
CALL AddTwo
ADD SP,4 ; clean parameters (2 words)
MOV SUM, AX
MOV AH,4Ch
XOR AL,AL
INT 21h
MAIN ENDP
AddTwo PROC
PUSH BP
MOV BP,SP
MOV AX,[BP+4] ; first param (A)
ADD AX,[BP+6] ; AX = A + B
POP BP
RET
AddTwo ENDP
END
Notes to write in exam: show stack layout and explain [BP+4] [BP+6].
7) Instruction Pipelining (5 stages) +
hazards & fixes
5 stages (short): Fetch → Decode → Execute → Memory → Write-Back
Timing diagram (example):
Time → T1 T2 T3 T4 T5 T6
I1 [F] [D] [E] [M] [W]
I2 [F] [D] [E] [M] [W]
I3 [F] [D] [E] [M] [W]
How performance improves: overlapping stages increases instruction throughput.
Hazards:
• Data hazard: instruction needs result of previous instruction (fix: forwarding/bypass or
stall).
• Control hazard: branch changes flow (fix: branch prediction, delayed branch, flush
pipeline).
• Structural hazard: two stages need same hardware (fix: resource duplication or stall).
Exam tip: draw small timing chart + list one fix per hazard.
8) CISC vs RISC (comparative essay)
Definitions (short):
• CISC (Complex Instruction Set Computer): many complex instructions — one
instruction can do multi-step tasks (x86 is CISC).
• RISC (Reduced Instruction Set Computer): small set of simple instructions, each
executes quickly (ARM is RISC-like).
Comparison table (concise):
Aspect CISC (x86) RISC (ARM)
Instruction length variable fixed
Complexity complex instructions simple instructions
Microcode often used typically hardwired
high (more work per
Code density lower (more instructions)
instruction)
Pipeline friendliness harder (variable exec times) easier (uniform exec)
Example use desktop CPUs embedded/mobile CPUs
Conclusion: For COAL, mention x86 as CISC and ARM as RISC and give 2-3 practical
differences.
9) Program: Largest of Three Numbers
(branching/flags) — (exam code +
explanation)
Assume numbers at memory N1,N2,N3 or in registers. Here example with registers
AX,BX,CX and result in DX:
; AX = num1, BX = num2, CX = num3
MOV DX, AX ; assume AX biggest
CMP BX, DX
JLE CHECK_C ; if BX <= DX skip
MOV DX, BX ; else DX = BX
CHECK_C:
CMP CX, DX
JLE DONE
MOV DX, CX
DONE:
; DX holds largest
Explain: Use CMP then conditional jumps (JLE jump if less or equal). Show flags usage: CMP
sets ZF/SF/CF and jump uses those.
10) Program: Sum of Array Elements using
LOOP / Bubble Sort
(a) Sum 5 elements (array at ARR, count=5), result in SUMWORD:
MOV SI, OFFSET ARR
XOR AX,AX ; AX=0 accumulator
MOV CX,5 ; count
SUM_LOOP:
ADD AX, [SI] ; add word at [SI]
ADD SI, 2 ; next word (assuming words)
LOOP SUM_LOOP
MOV SUMWORD, AX
Explain: SI points, CX is loop counter, LOOP decrements CX and jumps if CX ≠ 0.
(b) Bubble Sort (pseudo assembly for N elements):
; Outer loop for passes
MOV CX, N
DEC CX ; N-1 passes
OUTER:
MOV SI, OFFSET ARR
MOV DX, N
DEC DX ; DX = comparisons per pass
INNER:
MOV AX, [SI]
CMP AX, [SI+2]
JLE NOSWAP
; swap
XCHG AX, [SI+2]
MOV [SI], AX
NOSWAP:
ADD SI, 2
DEC DX
JNZ INNER
LOOP OUTER
Explain: Two nested loops: outer reduces passes, inner compares neighbors and swaps if out
of order.