VLSI Testing: Introduction

EE-6-53(TO): Test and Verification of SoCs

History of Electronics

➢ Electronics is the most important invention of the

20th century

Electronic Circuits in 100 years
– Vacuum tube => VLSI (Very Large Scale Integrated circuits)

20 years ago, it was the 100 year anniversary

1904

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Electronic Computer

➢ First electronic computer ENIAC (1946)

– Large number of vacuum tubes: 18000
– Very high power consumption: 150kW
– Short life time filament
– Big Size: 27 Tons

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Moore’s Law: Growth of VLSI Circuits

➢ Complexity of modern VLSI chips has increased

tremendously in terms of size and functionality

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Chip Realisation Process

Customer’s need

Determine requirements

Write specifications

Design synthesis and Verification

Test development
Fabrication
Manufacturing test

Chips to customer

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VLSI Fabrication Flow

➢ Hundreds of chip/die fabricated on each wafer by

photolithography in batch process
➢ Defective parts must be identified and scrapped

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Why Testing?


The complexity of modern VLSI chips has increased
tremendously in terms of size as well as functionality
– #Transistors (Intel Hashwell@22nm) ~ 5.6Billion in 662mm2
– NVIDIA-A100 (Ampere @ TSMC-7nm) ~ 54.2 Billion in 862mm2
– Tr. density (Intel 22nm/14/10nm) ~ 15.3/37.5/100.8 Mtr/mm2

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Why Testing?


The complexity of modern VLSI chips has increased
tremendously in terms of size as well as functionality
– #Transistors (Intel Hashwell@22nm) ~ 5.6Billion in 662mm2
– NVIDIA-A100 (Ampere @ TSMC-7nm) ~ 54.2 Billion in 862mm2
– Tr. density (Intel 22nm/14/10nm) ~ 15.3/37.5/100.8 Mtr/mm2
– Fabricated in clean rooms with 99.999999999% pure Silicon
– 193nm Immersion Lithography (30 layers, 80 Lithgraphy steps,
1000 processes, >2000 DRC)
– EUVL (13.5nm) is already in production; #DRC has exploded1
– Probability of occurence of defects has increased

1 [Link]
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Why Testing?


The complexity of modern VLSI chips has increased
tremendously in terms of size as well as functionality
– #Transistors (Intel Hashwell@22nm) ~ 5.6Billion in 662mm2
– NVIDIA-A100 (Ampere @ TSMC-7nm) ~ 54.2 Billion in 862mm2
– Tr. density (Intel 22nm/14/10nm) ~ 15.3/37.5/100.8 Mtr/mm2
– Fabricated in clean rooms with 99.999999999% pure Silicon
– 193nm Immersion Lithography (30 layers, 80 Lithgraphy steps,
1000 processes, >2000 DRC)
– EUVL (13.5nm) is already in production; #DRC has exploded1
– Probability of occurence of defects has increased

Need to test every chip after fabrication to ruleout the
possibility of occurence of defects
1 [Link]
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Test Economics

➢ Manufacturing testing is very crucial from product

quality and economic point of view

Yield => 20%1 (new process) to 70% (mature process)

1. Silicon VLSI Technology: Fundamentals, Practice, and Modeling by James D. Plummer and Michael D. Deal and Peter B. Griffin

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Test Economics

➢ Manufacturing testing is very crucial from product

quality and economic point of view

Yield => 20% (new process) to 70% (mature process)

Cost of Testing will EXCEED cost of design/manufacture

Source:
ITR-Semiconductor 2002

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Why VLSI Testing ?

➢ At the end of manufacturing process, Testing

isolates Good chips from Bad chips

How to test a chip?

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 Why VLSI Testing ?

➢ At the end of manufacturing process, Testing

isolates Good chips from Bad chips

How to test a chip?
Test Vectors Test Responses
----1100 ----1000
----1010 ----0010
----------- DIGITAL ----------- Test
COMPARATOR
----------- CIRCUIT ----------- Result
----1011 ----1110
----0010 ----0110

Golden
Responses

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 Why VLSI Testing ?

➢ At the end of manufacturing process, Testing

isolates Good chips from Bad chips

How to test a chip?
Test Vectors Test Responses
----1100 ----1000
----1010 ----0010
----------- DIGITAL ----------- Test
COMPARATOR
----------- CIRCUIT ----------- Result
----1011 ----1110
----0010 ----0110


Qualities of a Good Test
Golden
– Assures detection of all modeled defects Responses
– Economical test development and application time

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VLSI Testing is a Difficult Problem

➢ Functional test gurantees 100% defect coverage


2N tests for N-input combinational circuit
– 24 = 16 test for the 4-input NAND gate A
B
Y
C
D

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VLSI Testing is a Difficult Problem

➢ Functional test gurantees 100% defect coverage


2N tests for N-input combinational circuit
– 24 = 16 test for the 4-input NAND gate A
B
Y

Many IC’s have >> 100 inputs C
D
– 2100 = 1.27 x 1030 tests
– 1030 tests @ 1GHz (109 tests/sec)=1021 sec ~ 400billion centuries

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VLSI Testing is a Difficult Problem

➢ Functional test gurantees 100% defect coverage


2N tests for N-input combinational circuit
– 24 = 16 test for the 4-input NAND gate A
B
Y

Many IC’s have >> 100 inputs C
D
– 2100 = 1.27 x 1030 tests
– 1030 tests @ 1GHz (109 tests/sec)=1021 sec ~ 400billion centuries

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VLSI Testing is a Difficult Problem

➢ Functional test gurantees 100% defect coverage


2N tests for N-input combinational circuit
– 24 = 16 test for the 4-input NAND gate A
B
Y

Many IC’s have >> 100 inputs C
D
– 2100 = 1.27 x 1030 tests
– 1030 tests @ 1GHz (109 tests/sec)=1021 sec ~ 400billion centuries

Functional test is practically not viable !!!

Only a few input combinations can be applied in practice
– tester time is very costly

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IC Testing in Practice

➢ A few seconds of test time on very expensive

production testers
➢ Many thousand test patterns applied
➢ Test patterns carefully chosen to detect likely
faults
➢ High economic impact

test costs are approaching manufacturing costs
➢ Despite the costs, testing is always imperfect !!!

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Problems of Ideal Tests

➢ Ideal tests detect all defects produced in the

manufacturing process
➢ Ideal tests pass all functionally good devices
➢ Very large numbers and varieties of possible
defects need to be tested
➢ Difficult to generate tests for some real defects

Defect-oriented testing is an open problem

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Real Tests

➢ Based on analyzable fault models, which may not

map on real defects
➢ Incomplete coverage of modeled faults due to high
complexity
➢ Some good chips are rejected. The fraction (or
percentage) of such chips is called the `Yield loss’
➢ Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing chips is
called the `Defect level’

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Testing as Filtering Process

Good Chips prob(pass_test) = high

prob(good) = y Mostly Good Chips
pr
ob
(f
ai
l_
t es
t)
=
lo
Fabricated w Tested
Chips Chips
w
lo
=
t)
t es
s s_
a
b(p
o
pr
Bad Chips Mostly Bad Chips
prob(bad) = 1-y prob(fail_test) = high

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Testing as Filtering Process

– PQ: chip is pass quality P: chip passes the test

– FQ: chip is fail quality F: chip fails the test
For example, if prob(PQ) = 0.7, then prob(FQ) = 0.3
If the test is such that
prob(P|PQ) = 0.95, then prob(F|PQ) = 0.05
Similarly,
prob(F|FQ) = 0.95, then prob(P|FQ) = 0.05
prob(P) = prob(P|PQ) x prob(PQ) + prob(P|FQ) x prob(FQ)
= (0.95 x 0.7) + (0.05 x 0.3) = 0.68
Similarly,
prob(F) = prob(F|FQ) x prob(FQ) + prob(F|PQ) x prob(PQ)
= 0.95 x 0.3) + (0.05 x 0.7) = 0.32

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Testing as Filtering Process

70% Pass Quality prob(P/PQ) = 0.95

prob(P) = 0.68
prob(PQ) = 0.70 pr
ob
(F
/P
Q)
=
0.
05
Fabricated Tested
Chips 05 Chips
0.
=
)
/FQ
P
o b(
pr

30% Fail Quality

prob (F) = 0.32
prob(FQ) = 0.30 prob(F/FQ) = 0.95

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Testing as Filtering Process

– prob(P) = 0.68 (Are all passed chips of good quality?)

– prob(FQ|P): conditional probability of a chip belonging
to the group “bad chip”, given that the chip
has passed the test
– prob(FQ,P): joint probability of FQ and P
prob(FQ,P) = prob(FQ|P) x prob(P)
By Bayes theorem
prob(FQ,P) = prob(FQ|P) x prob(P) = prob(P|FQ) x prob(FQ)
prob(FQ|P) = prob(P|FQ) x prob(FQ) / prob(P)
= 0.05 x 0.3 / 0.68 = 0.022 = 2.2%
– 2.2% pass chips are of bad quality
– This is called “Defect Level”

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Testing as Filtering Process

– prob(F) = 0.32 (Are all failed chips of bad quality?)

– prob(PQ|F): conditional probability of a chip belonging
to the group “good chip”, given that the
chip has failed the test
– prob(PQ,F): joint probability of PQ and F
prob(PQ,F) = prob(PQ|F) x prob(F)
By Bayes theorem
prob(PQ,F) = prob(PQ|F) x prob(F) = prob(F|PQ) x prob(PQ)
prob(PQ|F) = prob(F|PQ) x prob(PQ) / prob(F)
= 0.05 x 0.7 / 0.32 = 0.011 = 1.1%
– 1.1% failed chips are of good quality
– This is called “Yield loss”

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Testing as Filtering Process

70% Pass Quality prob(P/PQ) = 0.95

prob(P) = 0.68
prob(PQ) = 0.70 Pr
ob (2.2% bad chips)
(F DL
/P
Q)
=
0.
05
Fabricated Tested
Chips 05 Chips
0.
=
)
/FQ
P
o b(
pr

30% Fail Quality

prob(F) = 0.32
prob(FQ) = 0.30 prob(F/FQ) = 0.95 (1.1% good chips)
Yield loss

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How well must we test?

➢ Approximate order of magnitude estimates


Number of parts per typical system : 100

Acceptable system defect rate: 1% (1 per 100)

Therefore, required part reliability
– 1 defect in 10,000
– 100 Defects Per Million (100 DPM)

Requirement
– ~100 DPM for commercial ICs
– ~1000 DPM for ASICs
– “Zero Defect” target for Automotive

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Test Coverage for 100 DPM

➢ Assume 2 million ICs manufactured with 50% yield


1 million GOOD >> shipped

1 million BAD >> Test escapes cause defective parts to
be shipped

For 100 BAD parts in 1M shipped parts (DPM=100)
– Test must detect 999,900 out of the 1,000,000 BAD

For 100 DPM, needed Test Coverage = 99.99%

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DPM and System Failure Probability

➢ Defective Parts per Million shipped parts:


~ 100 DPM (0.01%) for commercial ICs
– System with 10 ICs => 0.1% Failure Probability
– System with 100 ICs => 1.0% Failure Probability
– System with 500 ICs => 5.0% Failure Probability

< 10 DPM for Automotive Industry
– Target : “Zero” defects!

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Classical Yield Models

➢ Two classes of Manufacturing Defects


Gross or area defects

Random spot defects

In mature well controlled processes, die yield is mostly
limited by random spot defects
– impossible to completely eliminate

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Yield and Defect Density

➢ The simplest defect distribution model for

semiconductor wafers assumes that random spot
defects are uniformly distributed
x
x x
x
x x x
x

x x

Die Yield = e-λ
x
– λ = Average number of defects per Die
= Defect Density (~ 0.2 - 1.0 per cm2) x Die Area
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Yield and Die Size

➢ Die yield = e-λ


λ = Average number of defects per Die
= Defect Density x Die Area
x
x x
x
x x x

Yield = 1/e (37%) for λ = 1 x

– Defect density ~ 0.5 defect/sq-cm x x

– Largest die area ~ 2 sq-cms
x

2X area increase reduces yield by 50%

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Defect Tolerant ICs: Memory IC

➢ Most ICs must be scrapped even for single defect

Spare row

It limits the yield and die area D ~
E

Memories are designed to R C
O O
W D
be defect tolerant (since 1979!) E x
R

Only certain fraction of the total
Non-repairable core
area is repairable - Decoders, drivers
Repairable cell arrays

5 - 10 repairs are common - Extra word, bit lines


Unrepaired yield of 10-20% can be increased to 80-90%

Memory chips can be larger in area than processors

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Defect Clustering on Wafers

➢ The Poisson model has been found to consistently

underestimate yield
– This suggests, defects on semiconductor
wafers are not uniformly distributed x
but are clustered x x
x
– For a given total number of defects x x x
on the wafer, defect clustering x

results in more die with multiple x x

defects, and therefore more defect
x
free die (higher yield)

The impact on yield is significant but modest
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Defect Clustering on Wafers

➢ Defect clustering has been observed in virtually

every fabrication line in 40 years of semiconductor
manufacturing experience

The radial effect in defect
clustering is quite pronounced

The causes of defect clustering
are numerous and varied, and
can be related to many different fabrication steps

The extent of defect clustering can vary based on the
product and process technology
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Defect Based Yield Models

➢ Several Yield Models have been developed to

account for this defect clustering and relate
defect density data to chip yield
➢ Stapper’s Negative Binomial model is the most
widely accepted
➢ This model has been widely used for yield
prediction and optimization, and redundancy trade-
off calculations for memories

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Test Coverage for 100 DPM

➢ Assume 2 million ICs manufactured with 50% yield


1 million GOOD >> shipped

1 million BAD >> Test escapes cause defective parts to
be shipped

For 100 BAD parts in 1M shipped parts (DPM=100)
– Test must detect 999,900 out of the 1,000,000 BAD

For 100 DPM, needed Test Coverage = 99.99%

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DPM Depends on Yield

➢ For a test coverage of 99.99% (Escapes: 100

defective per million good parts)

1 Million Parts @ 10% Yield
– 0.1 million GOOD >> shipped
– 0.9 million BAD >> 90 test escapes
– DPM = 90/0.1 = 900

1 Million Parts @ 90% Yield
– 0.9 million GOOD >> shipped
– 0.1 million BAD >> 10 test escapes
– DPM = 10/0.9 = 11

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Testing a Large Complex Die

➢ Testing large, complex low yielding die is the

biggest challenge

Higher DPM even for equally effective (similar
“coverage”) tests because of lower yields

Difficult to achieve high coverage testing for large
complex die

DPM increases non linearly with die complexity

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Types of Testing

➢ Classified into four types depending upon purpose


Characterization
– Also known as design debug or verification testing
– Performed on a new design before it is sent to production

Production
– Also known as manufacturing testing
– Performed on every manufactured chip

Burn-in

Incoming Inspection

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Characterization Testing

➢ Performed on first silicon samples

➢ Verify correctness of design

Functional tests are run
➢ Ensures device will meet all specifications

Comprehensive AC and DC characterization
➢ Ferociously expensive
– SEM testers
– E-beam tests
– Repeated functional tests

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Characterization Testing

➢ Determines exact limits of device operating values

➢ Worst case test

Select test that results in chip pass/fail decision
– Select statistically signifact sample of passed devices
– Repeat test for two or more environmental variable
– Two dimensional Shmoo plot is used
for worst case

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Manufacturing Testing

➢ Determines whether manufactured chip meets

specs

Must cover high % of modeled faults

Must minimize test time (to control cost)

Generally no fault diagnosis
– Identification of systematic (repeat) failures
– Important for yield improvement (yield ramp)

Tests every device on chip

Test at-speed of application or speed guaranteed by the
supplier

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Burn-in Stress Test


Catches:
– Infant mortality failures – these are flawed chips that will fail
in the first few days of operation – causes bad devices to
actually fail - screened out by a short-term burn-in (10-30
hours) in a normal or slightly accelerated working environment
– Freak failures - devices having the same failure mechanisms as
the reliable devices, require long burn-in time (100-1,000 hours)
in an accelerated environment

Process:
– Subject chips to high temperature & over-voltage supply, while
running tests

Where needed:
– Large, low yielding chips; all high end µPs are burned-in
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Incoming Inspection Testing

➢ Performed by system manufactureron on the

purchased devices before integration into system

Can be similar to production testing or more
comprehensive

Can be done on random samples with sample size
considered based on device quality or system requirment

Reduces system diagnosis cost

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Roles of Testing

➢ Detection: Determination whether or not the

device under test (DUT) has some fault
➢ Diagnosis: Identification of a specific fault that is
present on DUT
➢ Device characterization: Determination and
correction of error in design/test procedure
➢ Failure mode analysis (FMA): Determination of
manufacturing process errors that may have
caused defects on the DUT

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Cost of Testing Semiconductor Chips

➢ Three main variable components


Test Application Time
– When amortizing the cost of a tester over all chips, higher test
time results in to higher actual cost
– Rule of thumb: 1 second per chip!

Test Data Volume
– Low and medium cost testers have limited storage

Tester Pins
– Cost of a tester is directly proportional to the number of pins it
supports

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ADVANTEST Model T6682 ATE

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Types of ATE


IC Device ATE
– Memory, Logic, Mixed-signal, Analog
– Environmental Test - Burn-In

Board-Level ATE
– Bare-Board Testers (Assembly Fault Testers )
– Manufacturing Defects Analyzers
– In-circuit Testers
– Functional Board Testers
– Combinational Board Testers

Systems Testers

Field Service Testers
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Cost of Manufacturing Testing in 2000AD


0.5-1.0GHz, analog instruments,1,024 digital pins: ATE
purchase price
= $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M = $1.439M / year

Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600) = 4.5 cents / second

Example: test time = 6 seconds; yield = 65%
– Test cost / per chip = 4.5 x 6 = 27 cents
– Test component in good chip cost = 27 / 0.65 = 41.5 cents
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Tremendous Cost Pressure


The price to performance ratio of semiconductors
continues to decline: Moore’s Law

Test equipment cost increases
– Tester cost increase 10X in 30 years
– Prober cost increase 20X in 30 years

Test costs don’t scale with geometry
– must test all the individual parts
– must test them more thoroughly

Circuit complexity is increasingly continuously!!!
– Cerebras Systems Smashes the 2.5 Trillion Transistor Mark
with New Second Generation Wafer Scale Engine (WSE-2)
7nm-based Cerebras WSE-2 Powers Industry’s New Fastest AI Computer, the Cerebras CS-2
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Testing Cost : The Rule of Tens
Cost per fault (Dollars)
1000
500

100
50

10
5

1
0.5

0.1
IC Test Board Test System Test Warranty Repair

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 In-field Failures are Common and Costly

➢ Xbox 360 (Nov 2005)

- 16.4% failure rate

➢ Additional warranty and refund

- cost Microsoft $1.15B ($86
per $300-item)

➢ More than financial cost

- reputation and market loss

[Link]
02/xbox-360-failure-rates-worse-than-
most-consumer-electornics/

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The Testing Problem

➢ Which faults to target?


Fault modeling
➢ How is test derived?

Manually

Automatic Test Pattern Generation (ATPG)
➢ How is test quality measured?

Fault coverage vs. product quality

Fault simulation

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The Testing Problem

➢ How are tests applied?

– Test Engineering, Test programming
– Automatic Test Equipment (ATE)
– Wafer probe
➢ How to make sure high quality test can be derived
and applied?
– Design for testability (DfT)
– Built-in self-test (BIST)
➢ How to identify the source of errors?
– Fault Diagnosis

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