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LM5100A, LM5100B, LM5100C

LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015

LM5100A/B/C, LM5101A/B/C 3-A, 2-A, and 1-A High-Voltage, High-Side

and Low-Side Gate Drivers
1 Features An integrated high-voltage diode is provided to
charge the high-side gate drive bootstrap capacitor. A
1• Drives Both a High-Side and Low-Side N-Channel robust level shifter operates at high speed while
MOSFETs consuming low power and providing clean level
• Independent High- and Low-Driver Logic Inputs transitions from the control logic to the high-side gate
• Bootstrap Supply Voltage up to 118 V DC driver. Undervoltage lockout is provided on both the
low-side and the high-side power rails. These devices
• Fast Propagation Times (25-ns Typical)
are available in the standard SOIC-8 pin, SO
• Drives 1000-pF Load With 8-ns Rise and Fall PowerPAD-8 pin, and the WSON-10 pin packages.
Times The LM5100C and LM5101C are also available in
• Excellent Propagation Delay Matching (3-ns MSOP-PowerPAD-8 package. The LM5101A is also
Typical) available in WSON-8 pin package.
• Supply Rail Undervoltage Lockout Device Information(1)
• Low Power Consumption PEAK OUTPUT
PART NUMBER INPUT THRESHOLD
• Pin Compatible With HIP2100/HIP2101 CURRENT
LM5100A CMOS 3A
2 Applications LM5101A TTL 3A
• Current-Fed Push-Pull Converters LM5100B CMOS 2A

• Half and Full Bridge Power Converters LM5101B TTL 2A

LM5100C CMOS 1A
• Synchronous Buck Converters
LM5101C TTL 1A
• Two Switch Forward Power Converters
• Forward with Active Clamp Converters (1) For all available packages, see the orderable addendum at
the end of the data sheet.

3 Description
The LM5100A/B/C and LM5101A/B/C high-voltage
gate drivers are designed to drive both the high-side
and the low-side N-Channel MOSFETs in a
synchronous buck or a half-bridge configuration. The
floating high-side driver is capable of operating with
supply voltages up to 100 V. The A versions provide
a full 3-A of gate drive, while the B and C versions
provide 2 A and 1 A, respectively. The outputs are
independently controlled with CMOS input thresholds
(LM5100A/B/C) or TTL input thresholds
(LM5101A/B/C).
Simplified Block Diagram
HB

UVLO HO
LEVEL DRIVER
SHIFT
HS
HI

VDD

UVLO

LO
LI DRIVER

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015 [Link]

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 14
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 15
3 Description ............................................................. 1 9 Application and Implementation ........................ 16
4 Revision History..................................................... 2 9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 16
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 20
7 Specifications......................................................... 5 11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
7.1 Absolute Maximum Ratings ..................................... 5
11.2 Layout Example .................................................... 21
7.2 ESD Ratings.............................................................. 5
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 22
7.4 Thermal Information .................................................. 6 12.1 Documentation Support ....................................... 22
7.5 Electrical Characteristics ......................................... 6 12.2 Related Links ........................................................ 22
7.6 Switching Characteristics......................................... 8 12.3 Community Resources.......................................... 22
7.7 Typical Characteristics ............................................ 10 12.4 Trademarks ........................................................... 22
12.5 Electrostatic Discharge Caution ............................ 22
8 Detailed Description ............................................ 14
12.6 Glossary ................................................................ 22
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14 13 Mechanical, Packaging, and Orderable
Information ........................................................... 22

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision P (March 2013) to Revision Q Page

• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section. .................................... 1

Changes from Revision O (March 2013) to Revision P Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 19

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 LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
[Link] SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015

5 Device Comparison Table

PART NUMBER PACKAGE BODY SIZE (NOM)

WSON (10) 4.00 mm × 4.00 mm
LM5100A, LM5100C SO PowerPAD™ (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
WSON (10) 4.00 mm × 4.00 mm
LM5100B, LM5101B
SOIC (8) 3.91 mm × 4.90 mm
WSON (8) 4.00 mm × 4.00 mm
WSON (10) 4 .00mm × 4.00 mm
LM5101A
SO PowerPAD (8) 3.90 mm × 4.89 mm
SOIC (8) 3.91 mm × 4.90 mm
MSOP PowerPAD (8) 3.00 mm × 3.00 mm
LM5101C WSON (10) 4.00 mm × 4.00 mm
SOIC (8) 3.91 mm × 4.90 mm

6 Pin Configuration and Functions

D Package
8-Pin SOIC DPR Package
Top View 10-Pin WSON With Exposed Thermal Pad
Top View

VDD 1 8 LO VDD 1 10 LO

HB 2 7 VSS HB 2 9 VSS
SOIC-8
HO 3 6 LI HO 3 WSON-10 8 LI

HS 4 7 HI
HS 4 5 HI
NC 5 6 NC

NGT Package
8-Pin WSON With Exposed Thermal Pad DDA Package
Top View 8-Pin SO PowerPAD
Top View
VDD 1 8 LO

VDD 1 8 LO
HB 2 7 VSS
WSON-8
HO 3 6 LI HB 2 7 VSS
SO
PowerPad-8
HS 4 5 HI HO 3 6 LI

HS 4 5 HI

Exposed Pad
Connect to VSS

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LM5100A, LM5100B, LM5100C
LM5101A, LM5101B, LM5101C
SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015 [Link]

DGN Package
8-Pin MSOP-PowerPAD
Top View

VDD 1 8 LO

HB 2 7 VSS
MSOP-
PowerPad-8
HO 3 6 LI

HS 4 5 HI

Pin Functions
PIN
I/O DESCRIPTION
NAME 8 PINS 10 PINS (1)
High-side gate driver bootstrap supply. Connect the positive terminal of the bootstrap
HB 2 2 I capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be
placed as close to the IC as possible.
High-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
HI 5 7 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
High-side gate driver output. Connect to the gate of high-side MOSFET with a short,
HO 3 3 O
low inductance path.
High-side MOSFET source connection. Connect to the bootstrap capacitor negative
HS 4 4 —
terminal and the source of the high-side MOSFET.
Low-side driver control input. The LM5100A/B/C inputs have CMOS type thresholds.
LI 6 8 I The LM5101A/B/C inputs have TTL type thresholds. Unused inputs should be tied to
ground and not left open.
Low-side gate driver output. Connect to the gate of the low-side MOSFET with a
LO 8 10 O
short, low inductance path.
Positive gate drive supply . Locally decouple to VSS using low ESR/ESL capacitor
VDD 1 1 I
located as close to the IC as possible.
VSS 7 9 — Ground return. All signals are referenced to this ground.
TI recommends that the exposed pad on the bottom of the package is soldered to
EP (2) — ground plane on the PC board, and that ground plane should extend out from
beneath the IC to help dissipate heat.

(1) For WSON-10 package, pins 5 and 6 have no connection.

(2) Exposed pad is not available on the 8-pin SOIC package.

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 LM5100A, LM5100B, LM5100C
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[Link] SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015

7 Specifications
7.1 Absolute Maximum Ratings
(1) (2)
See
MIN MAX UNIT
VDD to VSS −0.3 18 V
HB to HS −0.3 18 V
LI or HI input −0.3 VDD + 0.3 V
LO output −0.3 VDD + 0.3 V
HO output VHS − 0.3 VHB + 0.3 V
(3)
HS to VSS −5 100 V
HB to VSS 118 V
Junction temperature 150 °C
Storage temperature −55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military or Aerospace specified devices are required, contact the Texas Instruments Sales Office or Distributors for availability and
specifications.
(3) In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not
exceed –1 V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage
transiently. If negative transients occur, the HS voltage must never be more negative than VDD – 15 V. For example if VDD = 10 V, the
negative transients at HS must not exceed –5 V.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
Electrostatic
V(ESD) Option A 50 V
discharge Machine Model (MM) (2)
Option B and C 100

(1) The Human Body Model (HBM) is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2 kV for all pins except Pin 2,
Pin 3 and Pin 4 which are rated at 1000 V for HBM.
(2) Machine Model (MM) ratings are: 100 V(MM) for Options B and C; 50 V(MM) for Option A.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD 9 14 V
HS –1 100 V
HB VHS + 8 VHS + 14 V
HS slew rate < 50 V/ns
Junction temperature −40 125 °C

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LM5100A, LM5100B, LM5100C
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7.4 Thermal Information

LM5100A,
LM5100x,
LM5100C, LM5101C LM5101A
LM5101x
LM5101A
THERMAL METRIC (1) UNIT
MSOP-
SO PowerPAD WSON (2) WSON (2) SOIC
PowerPAD (2)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance (3) 40 80 37.8 40 170 °C/W
RθJC(top) Junction-to-case (top) thermal resistance — — 36.7 — — °C/W
RθJB Junction-to-board thermal resistance — — 14.9 — — °C/W
ψJT Junction-to-top characterization parameter — — 0.3 — — °C/W
ψJB Junction-to-board characterization parameter — — 15.2 — — °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — — 4.4 — — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) 4-layer board with Cu finished thickness 1.5, 1, 1, 1.5 oz. Maximum die size used. 5× body length of Cu trace on PCB top.
50-mm × 50-mm ground and power planes embedded in PCB. See Application Note AN-1187 (SNOA401).
(3) The RθJA is not a given constant for the package and depends on the printed circuit board design and the operating environment.

7.5 Electrical Characteristics

(1)
unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO .
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
VDD quiescent current, TJ = 25°C 0.1
LI = HI = 0 V mA
LM5100A/B/C TJ = –40°C to 125°C 0.2
IDD
VDD quiescent current, TJ = 25°C 0.25
LI = HI = 0 V mA
LM5101A/B/C TJ = –40°C to 125°C 0.4
TJ = 25°C 2
IDDO VDD operating current f = 500 kHz mA
TJ = –40°C to 125°C 3
TJ = 25°C 0.06
IHB Total HB quiescent current LI = HI = 0 V mA
TJ = –40°C to 125°C 0.2
TJ = 25°C 1.6
IHBO Total HB operating current f = 500 kHz mA
TJ = –40°C to 125°C 3
TJ = 25°C 0.1
IHBS HB to VSS current, quiescent HS = HB = 100 V µA
TJ = –40°C to 125°C 10
IHBSO HB to VSS current, operating f = 500 kHz 0.4 mA
INPUT PINS
Input voltage threshold TJ = 25°C 5.4
VIL Rising Edge V
LM5100A/B/C TJ = –40°C to 125°C 4.5 6.3
Input voltage threshold TJ = 25°C 1.8
VIL Rising Edge V
LM5101A/B/C TJ = –40°C to 125°C 1.3 2.3
Input voltage hysteresis
VIHYS 500 mV
LM5100A/B/C
Input voltage hysteresis
VIHYS 50 mV
LM5101A/B/C
TJ = 25°C 200
RI Input pulldown resistance kΩ
TJ = –40°C to 125°C 100 400

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

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Electrical Characteristics (continued)

unless otherwise specified, limits are for TJ = 25°C, VDD = VHB = 12 V, VSS = VHS = 0 V, no load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
UNDER VOLTAGE PROTECTION
TJ = 25°C 6.9
VDDR VDD rising threshold V
TJ = –40°C to 125°C 6 7.4
VDDH VDD threshold hysteresis 0.5 V
TJ = 25°C 6.6
VHBR HB rising threshold V
TJ = –40°C to 125°C 5.7 7.1
VHBH HB threshold hysteresis 0.4 V
BOOT STRAP DIODE
TJ = 25°C 0.52
VDL Low-current forward voltage IVDD-HB = 100 µA V
TJ = –40°C to 125°C 0.85
TJ = 25°C 0.8
VDH High-current forward voltage IVDD-HB = 100 mA V
TJ = –40°C to 125°C 1
Dynamic resistance TJ = 25°C 1.0
RD IVDD-HB = 100 mA Ω
LM5100A/B/C, LM5101A/B/C TJ = –40°C to 125°C 1.65
LO AND HO GATE DRIVER
Low-level output voltage TJ = 25°C 0.12
V
LM5100A/LM5101A TJ = –40°C to 125°C 0.25
Low-level output voltage TJ = 25°C 0.16
VOL IHO = ILO = 100 mA V
LM5100B/LM5101B TJ = –40°C to 125°C 0.4
Low-level output voltage TJ = 25°C 0.28
V
LM5100C/LM5101C TJ = –40°C to 125°C 0.65
High-level output voltage TJ = 25°C 0.24
V
LM5100A/LM5101A TJ = –40°C to 125°C 0.45
IHO = ILO = 100 mA TJ = 25°C 0.28
High-level output voltage
VOH VOH = VDD– LO or V
LM5100B/LM5101B TJ = –40°C to 125°C 0.60
VOH = HB - HO
High-level output voltage TJ = 25°C 0.6
V
LM5100C/LM5101C TJ = –40°C to 125°C 1.10
Peak pullup current
3 A
LM5100A/LM5101A
Peak pullup current
IOHL HO, LO = 0 V TJ = 25°C 2 A
LM5100B/LM5101B
Peak pullup current
1 A
LM5100C/LM5101C
Peak pulldown current
3 A
LM5100A/LM5101A
Peak pulldown current
IOLL HO, LO = 12 V TJ = 25°C 2 A
LM5100B/LM5101B
Peak pulldown current
1 A
LM5100C/LM5101C

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7.6 Switching Characteristics

Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of –40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise specified, VDD =
VHB = 12 V, VSS = VHS = 0 V, No Load on LO or HO (1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LO turnoff propagation delay LM5100A/B/C 20 45 ns
tLPHL LI Falling to LO Falling
LO turnoff propagation delay LM5101A/B/C 22 56 ns
LO turnon propagation delay LM5100A/B/C 20 45 ns
tLPLH LI Rising to LO Rising
LO turnon propagation delay LM5101A/B/C 26 56 ns
HO turnoff propagation delay
20 45 ns
LM5100A/B/C
tHPHL HI Falling to HO Falling
HO turnoff propagation delay
22 56 ns
LM5101A/B/C
LO turnon propagation delay LM5100A/B/C 20 45 ns
tHPLH HI Rising to HO Rising
LO turnon propagation delay LM5101A/B/C 26 56 ns
Delay matching: LO on and HO off
1 10 ns
LM5100A/B/C
tMON
Delay matching: LO on and HO off
4 10 ns
LM5101A/B/C
Delay matching: LO off and HO on
1 10 ns
LM5100A/B/C
tMOFF
Delay matching: LO on and HO off
4 10 ns
LM5101A/B/C
tRC, tFC Either output rise and fall time CL = 1000 pF 8 ns
Output rise time (3 V to 9 V)
430 ns
LM5100A/LM5101A
Output rise time (3 V to 9 V)
tR CL = 0.1 µF 570 ns
LM5100B/LM5101B
Output rise time (3 V to 9 V)
990 ns
LM5100C/LM5101C
Output fall time (3 V to 9 V)
260 ns
LM5100A/LM5101A
Output fall time (3 V to 9 V)
tF CL = 0.1 µF 430 ns
LM5100B/LM5101B
Output fall time (3 V to 9 V)
715 ns
LM5100C/LM5101C
Minimum input pulse width that changes
tPW 50 ns
the output
IF = 100 mA,
tBS Bootstrap diode reverse recovery time 37 ns
IR = 100 mA

(1) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

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[Link] SNOSAW2Q – SEPTEMBER 2006 – REVISED NOVEMBER 2015

LI
LI
HI
HI tHPLH
tLPLH
tHPHL
tLPHL
LO

LO
HO
HO

tMON tMOFF

Figure 1. Timing Diagram

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7.7 Typical Characteristics

5.0 5.0
4.5 4.5
4.0 4.0
3.5 LM5100A/LM5101A 3.5 LM5100A/LM5101A
CURRENT (A)

CURRENT (A)
3.0 3.0
2.5 2.5
2.0 2.0 LM5100B/LM5101B
LM5100B/LM5101B
1.5 1.5
1.0 1.0
LM5100C/LM5101C LM5100C/LM5101C
0.5 0.5

0.0 0.0
7 8 9 10 11 12 13 14 15 7 8 9 10 11 12 13 14 15
VDD (V) VDD (V)
Figure 2. Peak Sourcing Current vs VDD Figure 3. Peak Sinking Current vs VDD
3.5 3.5
VDD = 12 V VDD = 12 V
3.0 3.0
LM5100A/LM5101A LM5100A/LM5101A
2.5 2.5
CURRENT (A)
CURRENT (A)

2.0 2.0

LM5100B/LM5101B LM5100B/LM5101B
1.5 1.5

1.0 1.0
LM5100C/LM5101C
0.5 0.5 LM5100C/LM5101C

0.0 0.0
0 2 4 6 8 10 12 0 2 4 6 8 10 12
OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V)
Figure 4. Sink Current vs Output Voltage Figure 5. Source Current vs Output Voltage
100000 100000
VDD = 12 V
CL = 4400 pF VDD = 12 V
CL = 4400 pF
10000
10000
CURRENT (μA)

CURRENT (μA)

CL = 1000 pF
1000
CL = 1000 pF
1000
100 CL = 0 pF
CL = 0 pF

10 100
0.1 1 10 100 1000
0.1 1 10 100 1000
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 7. LM5101A/B/C IDD vs Frequency
Figure 6. LM5100A/B/C IDD vs Frequency

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Typical Characteristics (continued)

2.3 100000
HB = 12 V,
2.1 IDDO (LM5101A/B/C) HS = 0 V
CL = 4400 pF
1.9 10000
IDDO (LM5100A/B/C)

CURRENT (PA)
CURRENT (mA)

1.7 CL = 1000 pF

1.5 IHBO 1000

1.3

100 CL = 0 pF
1.1

0.9

0.7 10
-50 -25 0 25 50 75 100 125 150 0.1 1 10 100 1000
TEMPERATURE ( oC) FREQUENCY (kHz)
Figure 8. Operating Current vs Temperature Figure 9. IHB vs Frequency
400 350

350
IDD (LM5101A/B/C) 300
300 IDD (LM5101A/B/C)
250
CURRENT (μA)

CURRENT (μA)
250
200
200
IDD (LM5100A/B/C) 150
150
IDD (LM5100A/B/C)
100
100
IHB 50
50
IHB
0 0
8 9 10 11 12 13 14 15 16 -50 -25 0 25 50 75 100 125 150
VDD, VHB (V) TEMPERATURE (°C)
Figure 10. Quiescent Current vs Supply Voltage Figure 11. Quiescent Current vs Temperature
7.30 0.60

7.20
0.55
7.10 VDDH
HYSTERESIS (V)

7.00
THRESHOLD (V)

VDDR 0.50
6.90
6.80 0.45

6.70 VHBH
0.40
6.60 VHBR
6.50 0.35
6.40
6.30 0.30
-50 0 25
-50 -25 0 25 50 75 100 125 150

TEMPERATURE (°C) TEMPERATURE ( oC)

Figure 12. Undervoltage Rising Thresholds vs Temperature Figure 13. Undervoltage Threshold Hysteresis vs
Temperature

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Typical Characteristics (continued)

1.00E-01 50
49
T = 150°C

THRESHOLD VOLTAGE (%VDD)

1.00E-02 48 Rising
47
1.00E-03 46
ID (A)

T = 25°C
45
1.00E-04 44 Falling
43
T = -40°C
1.00E-05 42
41
1.00E-06 40
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 -50 -25 0 25 50 75 100 125 150

VD (V) TEMPERATURE (°C)

Figure 14. Bootstrap Diode Forward Voltage Figure 15. LM5100A/B/C Input Threshold vs Temperature
1.92 50
1.91
49

THRESHOLD VOLTAGE (%VDD)

1.90
THRESHOLD VOLTAGE (V)

Rising 48
1.89 Rising
1.88 47

1.87 46
1.86 45
1.85 Falling
44
1.84
43
1.83 Falling
42
1.82
1.81 41
1.80 40
-50 -25 0 25 50 75 100 125 150 8 9 10 11 12 13 14 15 16
TEMPERATURE (°C) VDD (V)
Figure 16. LM5101A/B/C Input Threshold vs Temperature Figure 17. LM5100A/B/C Input Threshold vs VDD
1.92 35
1.91
1.90
THRESHOLD VOLTAGE (V)

Rising
1.89 30
1.88
DELAY (ns)

1.87
1.86 25

1.85 T_PLH
Falling
1.84
20 T_PHL
1.83
1.82
1.81
1.80 15
8 9 10 11 12 13 14 15 16 -50 -25 0 25 50 75 100 125 150
VDD (V) TEMPERATURE (°C)
Figure 18. LM5101A/B/C Input Threshold vs VDD Figure 19. LM5100A/B/C Propagation Delay vs Temperature

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Typical Characteristics (continued)

40 1.0
VDD = 12 V
0.9
35 0.8
LM5100C/LM5101C
0.7
DELAY (ns)

30 0.6

VOH (V)
T_PLH
0.5
LM5100B/LM5101B
25 0.4
T_PHL 0.3

20 0.2
LM5100A/LM5101A
0.1

15 0.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 21. LO and HO Gate Drive - High Level Output
Figure 20. LM5101A/B/C Propagation Delay vs Temperature
Voltage vs Temperature
0.50 0.8
VDD = 12 V IOUT = -100 mA
0.45
0.7
0.40
0.35 0.6 LM5100C/LM5101C
LM5100C/LM5101C
0.30
VOL (V)

0.5
VOH (V)

0.25
LM5100B/LM5101B
0.20 0.4

0.15
0.3 LM5100B/LM5101B
0.10 LM5100A/LM5101A
0.05 0.2
LM5100A/LM5101A
0.00 0.1
-50 -25 0 25 50 75 100 125 150 7 8 9 10 11 12 13 14 15
TEMPERATURE (°C) VDD (V)
Figure 22. LO and HO Gate Drive - Low Level Output Figure 23. LO and HO Gate Drive - Output High Voltage vs
Voltage vs Temperature VDD
0.35
IOUT = 100 mA

0.30 LM5100C/LM5101C

0.25
VOL (V)

0.20
LM5100B/LM5101B

0.15
LM5100A/LM5101A

0.10
7 8 9 10 11 12 13 14 15
VDD (V)
Figure 24. LO and HO Gate Drive - Output Low Voltage vs VDD

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8 Detailed Description

8.1 Overview
The LM5100A/B/C and LM5101A/B/C are designed to drive both the high-side and the low-side N-channel FETs
in a synchronous buck or a half-bridge configuration. The outputs are independently controlled with CMOS input
thresholds(LM5101A/B/C) or TTL input thresholds(LM5101A/B/C). The floating high-side driver is capable of
working with supply voltages up to 100 V. An integrated high voltage diode is provided to charge high side gate
drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing
clean level transitions from the control logic to the high side gate driver. Under-voltage lockout is provided on
both the low side and the high side power rails.

8.2 Functional Block Diagram

HB

UVLO HO
LEVEL DRIVER
SHIFT
HS
HI

VDD

UVLO

LO
LI DRIVER

GND

8.3 Feature Description

8.3.1 Start-up and UVLO
Both high and low-side drivers include under voltage lockout (UVLO) protection circuitry which monitors the
supply voltage (VDD) and bootstrap capacitor voltage (VHB–HS) independently. The UVLO circuit inhibits each
driver until sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO
hysteresis prevents chattering during supply voltage transitions. When the supply voltage is applied to the VDD
pin of the LM5100A/B/C and LM5101A/B/C, the outputs of the low-side and high-side are held low until VDD
exceeds the UVLO threshold, typically about 6.6 V. Any UVLO condition on the bootstrap capacitor will disable
only the high-side output (HO).

8.3.2 Level Shift

The level shift circuit is the interface from the high-side input to the high-side driver stage which is referenced to
the switch node (HS). The level shift allows control of the HO output referenced to the HS pin and provides
excellent delay matching with the low-side driver.

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Feature Description (continued)

8.3.3 Bootstrap Diode
The bootstrap diode necessary to generate the high-side bias is included in the LM5100/1 family. The diode
anode is connected to VDD and cathode connected to VHB. With the VHB capacitor connected to HB and the HS
pins, the VHB capacitor charge is refreshed every switching cycle when HS transitions to ground. The boot diode
provides fast recovery times, low diode resistance, and voltage rating margin to allow for efficient and reliable
operation.

8.3.4 Output Stages

The output stages are the interface to the power MOSFETs in the power train. High slew rate, low resistance,
and high peak current capability of both output drivers allow for efficient switching of the power MOSFETs. The
low-side output stage is referenced from VDD to VSS and the high-side is referenced from VHB to VHS.

8.4 Device Functional Modes

The device operates in normal mode and UVLO mode. See Start-up and UVLO for more information on UVLO
operation mode. In normal mode, the output stage is dependent on the states of the HI and LI pins.

Table 1. Input/Output Logic Table

HI LI HO (1) LO (2)
L L L L
L H L H
H L H L
H H H H
x (3) x L L

(1) HO is measured with respect to the HS.

(2) LO is measured with the respect to the VSS.
(3) x is floating condition

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is
employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate
drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching
devices. With the advent of digital power, this situation will be often encountered because the PWM signal from
the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting
circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the
power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar
transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power
because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive
functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by
locating the high-current driver physically close to the power switch, driving gate-drive transformers and
controlling floating power-device gates, reducing power dissipation and thermal stress in controllers by moving
gate charge power losses from the controller into the driver.
The LM5100A/B/C and LM5101A/B/C are the high voltage gate drivers that are designed to drive both the high-
side and low-side N-Channel MOSFETs in a half-bridge/full bridge configuration or in a synchronous buck circuit.
The floating high side driver is capable of operating with supply voltages up to 100 V. This allows for N-Channel
MOSFET control in half-bridge, full-bridge, push-pull, two switch forward and active clamp topologies. The
outputs are independently controlled. Each channel is controlled by its respective input pins (HI and LI), allowing
full and independent flexibility to control on and off state of the output.

9.2 Typical Application

Optional external
fast recovery diode VIN

VCC
RBOOT DBOOT

HB RGATE
VDD VDD HO
CBOOT
0.1 µF
OUT1 HI
PWM HS
T1
LM5101A
Controller
OUT2 LI
LO
RGATE

1.0 µF
VSS

Figure 25. LM5101A Driving MOSFETs in Half-Bridge Configuration

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Typical Application (continued)

9.2.1 Design Requirements
See Table 2 for the parameter and values.

Table 2. Operating Parameters

PARAMETER VALUE
Gate Driver LM5101A
MOSFET CSD18531Q5A
VDD 10 V
Qgmax 43 nC
Fsw 100 kHz
Dmax 95%
IHBS 10 µA
VDH 1.0 V
VHBR 7.1 V
VHBH 0.4 V

9.2.2 Detailed Design Procedure

[Link] Select Bootstrap and VDD capacitor

The bootstrap capacitor must maintain the HB pin voltage above the UVLO voltage for the HB circuit in any
circumstances during normal operation. Calculate the maximum allowable drop across the bootstrap capacitor
with Equation 1.
ΔVHB = VDD – VDH – VHBL= 10 V – 1.0 V – 6.7 V = 2.3 V
where
• VDD = Supply voltage of the gate drive IC
• VDH = Bootstrap diode forward voltage drop
• VHBL = VHBR – VHBH = 6.7 V, HB falling threshold (1)
The quiescent current of the bootstrap circuit is 10 µA, which is negligible compared to the Qgs of the MOSFET
(see Equation 2 and Equation 3).
D 0.95
QTOTAL = Qgmax + IHBS MAX = 43 nC + 10 µA = 43.01nC
FSW 100 kHz (2)
QTOTAL 43.01nC
CBOOT = = =18.7 nF
DVHB 2.3 V (3)
In practice the value for the CBOOT capacitor should be greater than that calculated to allow for situations where
the power stage may skip pulse due to load transients. It is recommended to place the bootstrap capacitor as
close to the HB and HS pins as possible.
CBOOT = 100 nF (4)
As a general rule the local VDD bypass capacitor should be 10 times greater than the value of CBOOT.
CVDD = 10 × CBOOT = 1 µF (5)
The bootstrap and bias capacitors should be ceramic types with X7R dielectric. The voltage rating should be
twice that of the maximum VDD to allow for loss of capacitance once the devices have a DC bias voltage across
them and to ensure long-term reliability of the devices.

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[Link] Select External Bootstrap Diode and Resistor

The bootstrap capacitor is charged by the VDD through the internal bootstrap diode every cycle when low side
MOSFET turns on. The charging of the capacitor involves high peak currents, and therefore transient power
dissipation in the internal bootstrap diode may be significant and dependent on its forward voltage drop. Both the
diode conduction losses and reverse recovery losses contribute to the total losses in the gate driver and need to
be considered in the gate driver IC power dissipation.
For high frequency and high capacitive loads, it may be necessary to consider using an external bootstrap diode
placed in parallel with internal bootstrap diode to reduce power dissipation of the driver. For the selection of
external bootstrap diodes for LM510x device, please refer to the application note SNVA083.
Bootstrap resistor RBOOT is selected to reduce the inrush current in DBOOT and limit the ramp up slew rate of
voltage of HB-HS. It is recommended that RBOOT is between 2 Ω and 10 Ω. For this design, a current limiting
resistor of 2.2 Ω is selected to limit inrush current of bootstrap diode.
V - VDBOOT 10 V - 0.6 V
IDBOOT(pk ) = DD = = 4.27 A
RBOOT 2.2 W (6)

[Link] Select Gate driver Resistor

Resistor RGATE is sized to reduce ringing caused by parasitic inductances and capacitances and also to limit the
current coming out of the gate driver. For this design 4.7-Ω resistors were selected for this design. Maximum HO
and LO drive current are calculated by Equation 7 through Equation 10.
V - VDH - VOH 10 V - 1.0 V - 0.45 V
IHOH = DD = = 1.819 A
RGATE 4.7 W (7)
VDD - VOH 10 V - 0.45 V
ILOH = = = 2.032 A
RGATE 4.7 W (8)
VDD - VDH - VOL 10 V - 1.0 V - 0.25 V
IHOL = = = 1.862 A
RGATE 4.7 W (9)
V - VOH 10 V - 0.25 V
ILOL = DD = = 2.074 A
RGATE 4.7 W
where
• IHOH = Maximum HO source current
• ILOH = Maximum LO source current
• IHOL = Maximum HO sink current
• ILOH = Maximum HO sink current
• VOH = High-Level output voltage drop across HB to HO or VDD to LO
• VOL = Low-Level output voltage drop across HO to HS or LO to GND (10)

[Link] Estimate the Driver Power Losses

The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate
driver losses are related to the switching frequency (fsw), output load capacitance on LO and HO (CL), and supply
voltage (VDD). The gate charge losses can be calculated by Equation 11.
2
PDGATES = 2 ´ VDD ´ CL ´ fsw (11)
There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and
HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load
capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the
power losses driving the output loads and agrees well with Equation 11. Figure 26 can be used to approximate
the power losses due to the gate drivers.

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1.000

CL = 4400 pF

0.100

POWER (W)
CL = 1000 pF

0.010

CL = 0 pF

0.001
0.1 1.0 10.0 100.0 1000.0

SWITCHING FREQUENCY (kHz)

Figure 26. Gate Driver Power Dissipation (LO + HO)

VDD = 12 V, Neglecting Diode Losses

The internal bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the
bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these
events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads
require more energy to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to
the half bridge result in higher reverse recovery losses. The following plot was generated based on calculation
and lab measurements of the diode recovery time and current under several operating conditions. This can be
useful for approximating the internal diode power dissipation. If the diode losses can be significant, an external
diode placed in parallel with the internal bootstrap diode can be helpful to reduce power dissipation within the IC.
0.100

CL = 4400 pF
POWER (W)

0.010 CL = 0 pF

0.001
1 10 100 1000
SWITCHING FREQUENCY (kHz)

Figure 27. Diode Power Dissipation VIN = 50 V

The total IC power dissipation can be estimated from the plots shown in Figure 26 and Figure 27 by summing the
gate drive losses with the internal bootstrap diode losses for the intended application. For a given ambient
temperature, the maximum allowable power loss of the IC can be defined as equation Equation 12.
T - TA
Ploss = J
RqJA
where
• Ploss = The total power dissipation of the driver
• TJ = Junction temperature
• TA = Ambient temperature
• RθJA = Junction-to-ambient thermal resistance (12)

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The thermal metrics for the driver package is summarized in the Thermal Information table. For detailed
information regarding the thermal information table, refer to the Application Note from Texas Instruments entitled
Semiconductor and IC Package Thermal Metrics SPRA953.

9.2.3 Application Curves

Figure 28. HI/LI to HO/LO Turnon Propagation Delay Figure 29. HI/LI to HO/LO Turnoff Propagation Delay

10 Power Supply Recommendations

The bias supply voltage range for which the device is rated to operate is from 9 V to 14 V. The lower end of this
range is governed by the internal under voltage-lockout (UVLO) protection feature on the VDD pin supply circuit
blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the VDDR supply start
threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is
driven by the 18-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating).
Keeping a 4-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin
is 14 V.
The UVLO protection feature also involves a hysteresis function. This means that when the VDD pin bias voltage
has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device
continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDDH.
Therefore, ensuring that, while operating at or near the 9-V range, the voltage ripple on the auxiliary power
supply output is smaller than the hysteresis specification of the device is important to avoid triggering device
shutdown.
During system shutdown, the device operation continues until the VDD pin voltage has dropped below the
threshold (VDDR – VDDH), which must be accounted for while evaluating system shutdown timing design
requirements. Likewise, at system start up, the device does not begin operation until the VDD pin voltage has
exceeded above the VDDR threshold. The quiescent current consumed by the internal circuit blocks of the device
is supplied through the VDD pin. Keep in mind that the charge for source current pulses delivered by the LO pin
is also supplied through the same VDD pin. As a result, every time a current is sourced out of the LO pin a
corresponding current pulse is delivered into the device through the VDD pin. Thus ensuring that a local bypass
capacitor is provided between the VDD and GND pins and located as close as possible to the device for the
purpose of decoupling is important. A low ESR, ceramic surface mount capacitor is necessary. TI recommends
using two capacitors between VDD and GND: a 100-nF ceramic surface-mount capacitor that can be nudged
very close to the pins of the device and another surface-mount capacitor in the range 0.22 µF to 10 µF added in
parallel. In a similar manner, the current pulses delivered by the HO pin are sourced from the HB pin. Therefore,
a 0.022-µF to 1-µF local decoupling capacitor is recommended between the HB and HS pins.

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11 Layout

11.1 Layout Guidelines

The optimum performance of high and low-side gate drivers cannot be achieved without taking due
considerations during circuit board layout. Following points are emphasized.
1. Low-ESR/ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the
HB and HS pins to support the high peak currents being drawn from VDD during turnon of the external
MOSFET.
2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be
connected between MOSFET drain and ground (VSS).
3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the
source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized.
4. Grounding Considerations:
– The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as
possible to the gate driver.
– The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground
referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on
a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor.
The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length
and area on the circuit board is important to ensure reliable operation.
A recommended layout pattern for the driver is shown in Figure 30. If possible a single layer placement is
preferred.

11.2 Layout Example

Recommended Layout for Driver IC and
Passives

VDD LO

HB VSS
SO
PowerPAD-8
HO LI

HS HI
HO

HO
HS

LO

Single Layer
G

Multi Layer
N
D

Option Option

To Hi-Side FET To Low-Side FET

Figure 30. PCB Layout Recommendation

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
• AN-1187 Leadless Leadframe Package (LLP) (SNOA401)
• AN-1317 Selection of External Bootstrap Diode for LM510X Devices (SNVA083)
• Semiconductor and IC Package Thermal Metrics (SPRA953)

12.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 3. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
LM5100A Click here Click here Click here Click here Click here
LM5100B Click here Click here Click here Click here Click here
LM5100C Click here Click here Click here Click here Click here
LM5101A Click here Click here Click here Click here Click here
LM5101B Click here Click here Click here Click here Click here
LM5101C Click here Click here Click here Click here Click here

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM5100AM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AM/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AMR/NOPB Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR - L5100
(DDA) | 8 AMR
LM5100AMR/NOPB.A Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR -40 to 125 L5100
(DDA) | 8 AMR
LM5100AMR/NOPB.B Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR -40 to 125 L5100
(DDA) | 8 AMR
LM5100AMRX/NOPB Active Production SO PowerPAD 2500 | LARGE T&R Yes Call TI | Sn Level-3-260C-168 HR - L5100
(DDA) | 8 AMR
LM5100AMRX/NOPB.A Active Production SO PowerPAD 2500 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 125 L5100
(DDA) | 8 AMR
LM5100AMRX/NOPB.B Active Production SO PowerPAD 2500 | LARGE T&R Yes Call TI Level-3-260C-168 HR -40 to 125 L5100
(DDA) | 8 AMR
LM5100AMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100AMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
AM
LM5100ASD/NOPB Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100ASD/NOPB.A Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100ASD/NOPB.B Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100ASD
LM5100BMA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMA/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM5100BMAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BMAX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
BMA
LM5100BSD/NOPB Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100BSD/NOPB.A Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100BSD/NOPB.B Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5100BSD
LM5100CMAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
CMA
LM5100CMAX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5100
CMA
LM5101AM/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AM/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AM/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AMR/NOPB Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR - L5101
(DDA) | 8 AMR
LM5101AMR/NOPB.A Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR -40 to 125 L5101
(DDA) | 8 AMR
LM5101AMR/NOPB.B Active Production SO PowerPAD 95 | TUBE Yes SN Level-3-260C-168 HR -40 to 125 L5101
(DDA) | 8 AMR
LM5101AMRX/NOPB Active Production SO PowerPAD 2500 | LARGE T&R Yes SN Level-3-260C-168 HR - L5101
(DDA) | 8 AMR
LM5101AMRX/NOPB.A Active Production SO PowerPAD 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L5101
(DDA) | 8 AMR
LM5101AMRX/NOPB.B Active Production SO PowerPAD 2500 | LARGE T&R Yes SN Level-3-260C-168 HR -40 to 125 L5101
(DDA) | 8 AMR
LM5101AMX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101AMX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM5101AMX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 L5101
AM
LM5101ASD-1/NOPB Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM - 5101A-1
LM5101ASD-1/NOPB.A Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101A-1
LM5101ASD-1/NOPB.B Active Production WSON (NGT) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101A-1
LM5101ASD/NOPB Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASD/NOPB.A Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASD/NOPB.B Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASDX-1/NOPB Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM - 5101A-1
LM5101ASDX-1/NOPB.A Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101A-1
LM5101ASDX-1/NOPB.B Active Production WSON (NGT) | 8 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101A-1
LM5101ASDX/NOPB Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASDX/NOPB.A Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101ASDX/NOPB.B Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101ASD
LM5101BMA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMA/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BMAX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
BMA
LM5101BSD/NOPB Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSD/NOPB.A Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSD/NOPB.B Active Production WSON (DPR) | 10 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSDX/NOPB Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSDX/NOPB.A Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101BSD
LM5101BSDX/NOPB.B Active Production WSON (DPR) | 10 4500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101BSD

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

LM5101CMA/NOPB Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMA/NOPB.A Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMA/NOPB.B Active Production SOIC (D) | 8 95 | TUBE Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMAX/NOPB Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMAX/NOPB.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMAX/NOPB.B Active Production SOIC (D) | 8 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 L5101
CMA
LM5101CMY/NOPB Active Production HVSSOP (DGN) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM - SXDB
LM5101CMY/NOPB.A Active Production HVSSOP (DGN) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CMY/NOPB.B Active Production HVSSOP (DGN) | 8 1000 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CMYE/NOPB Active Production HVSSOP (DGN) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM - SXDB
LM5101CMYE/NOPB.A Active Production HVSSOP (DGN) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CMYE/NOPB.B Active Production HVSSOP (DGN) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CMYX/NOPB Active Production HVSSOP (DGN) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM - SXDB
LM5101CMYX/NOPB.A Active Production HVSSOP (DGN) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CMYX/NOPB.B Active Production HVSSOP (DGN) | 8 3500 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 SXDB
LM5101CSD/NOPB Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes NIPDAU | SN Level-1-260C-UNLIM -40 to 125 5101CSD
LM5101CSD/NOPB.A Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101CSD
LM5101CSD/NOPB.B Active Production WSON (DPR) | 10 1000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 5101CSD

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

Addendum-Page 4
 PACKAGE OPTION ADDENDUM

[Link] 10-Nov-2025

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 5
 PACKAGE MATERIALS INFORMATION

[Link] 31-Jul-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5100AMRX/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PowerPAD
LM5100AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100ASD/NOPB WSON DPR 10 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5100BSD/NOPB WSON DPR 10 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5100CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101AMRX/NOPB SO DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
PowerPAD
LM5101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101ASD-1/NOPB WSON NGT 8 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1
LM5101ASD-1/NOPB WSON NGT 8 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASD/NOPB WSON DPR 10 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX-1/NOPB WSON NGT 8 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101BSD/NOPB WSON DPR 10 1000 180.0 12.4 4.3 4.3 1.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 31-Jul-2025

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LM5101BSD/NOPB WSON DPR 10 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101BSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1
LM5101CMAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM5101CMY/NOPB HVSSOP DGN 8 1000 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYE/NOPB HVSSOP DGN 8 250 177.8 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CMYX/NOPB HVSSOP DGN 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LM5101CSD/NOPB WSON DPR 10 1000 177.8 12.4 4.3 4.3 1.3 8.0 12.0 Q1

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 31-Jul-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5100AMRX/NOPB SO PowerPAD DDA 8 2500 356.0 356.0 36.0
LM5100AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100ASD/NOPB WSON DPR 10 1000 208.0 191.0 35.0
LM5100BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5100BSD/NOPB WSON DPR 10 1000 208.0 191.0 35.0
LM5100CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101AMRX/NOPB SO PowerPAD DDA 8 2500 356.0 356.0 36.0
LM5101AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101ASD-1/NOPB WSON NGT 8 1000 200.0 183.0 25.0
LM5101ASD-1/NOPB WSON NGT 8 1000 208.0 191.0 35.0
LM5101ASD/NOPB WSON DPR 10 1000 208.0 191.0 35.0
LM5101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0
LM5101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM5101BSD/NOPB WSON DPR 10 1000 200.0 183.0 25.0
LM5101BSD/NOPB WSON DPR 10 1000 208.0 191.0 35.0
LM5101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0
LM5101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0

Pack Materials-Page 3
 PACKAGE MATERIALS INFORMATION

[Link] 31-Jul-2025

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM5101CMY/NOPB HVSSOP DGN 8 1000 208.0 191.0 35.0
LM5101CMYE/NOPB HVSSOP DGN 8 250 208.0 191.0 35.0
LM5101CMYX/NOPB HVSSOP DGN 8 3500 367.0 367.0 35.0
LM5101CSD/NOPB WSON DPR 10 1000 208.0 191.0 35.0

Pack Materials-Page 4
 PACKAGE MATERIALS INFORMATION

[Link] 31-Jul-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LM5100AM/NOPB D SOIC 8 95 495 8 4064 3.05
LM5100AM/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5100AM/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM5100AMR/NOPB DDA HSOIC 8 95 495 8 4064 3.05
LM5100AMR/NOPB.A DDA HSOIC 8 95 495 8 4064 3.05
LM5100AMR/NOPB.B DDA HSOIC 8 95 495 8 4064 3.05
LM5100BMA/NOPB D SOIC 8 95 495 8 4064 3.05
LM5100BMA/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5100BMA/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM5101AM/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM5101AMR/NOPB DDA HSOIC 8 95 495 8 4064 3.05
LM5101AMR/NOPB.A DDA HSOIC 8 95 495 8 4064 3.05
LM5101AMR/NOPB.B DDA HSOIC 8 95 495 8 4064 3.05
LM5101BMA/NOPB D SOIC 8 95 495 8 4064 3.05
LM5101BMA/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5101BMA/NOPB.B D SOIC 8 95 495 8 4064 3.05
LM5101CMA/NOPB D SOIC 8 95 495 8 4064 3.05
LM5101CMA/NOPB.A D SOIC 8 95 495 8 4064 3.05
LM5101CMA/NOPB.B D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 5
 PACKAGE OUTLINE
TM
DGN0008A SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4
5

0.25
GAGE PLANE
2.0
1.7 9 1.1 MAX

8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

1.88
TYPICAL
1.58

4218836/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

[Link]
 EXAMPLE BOARD LAYOUT
TM
DGN0008A PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.88)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(3)
9 SYMM NOTE 9

(2)

6X (0.65) (1.22)
5
4

( 0.2) TYP
VIA (0.55) SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4218836/A 11/2019
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

[Link]
 EXAMPLE STENCIL DESIGN
TM
DGN0008A PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

(1.88)
BASED ON
0.125 THICK
STENCIL
SYMM

8X (1.4) (R0.05) TYP

8
8X (0.45) 1

(2)
SYMM BASED ON
0.125 THICK
STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.10 X 2.24
0.125 1.88 X 2.00 (SHOWN)
0.15 1.72 X 1.83
0.175 1.59 X 1.69

4218836/A 11/2019
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DDA0008B SCALE 2.400
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

C
6.2
TYP SEATING PLANE
5.8
A
PIN 1 ID
AREA 0.1 C
6X 1.27
8
1

5.0 2X
4.8 3.81
NOTE 3

4X (0 -10 )
4
5
0.51
8X
4.0 0.31
B 1.7 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.10

SEE DETAIL A

4 5
EXPOSED
THERMAL PAD

3.4 0.25
9 GAGE PLANE
2.8

0.15
0 -8 1.27 0.00
1 8
0.40
DETAIL A
2.71 TYPICAL
2.11

4214849/B 09/2025
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012.

[Link]
 EXAMPLE BOARD LAYOUT
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.95)
NOTE 9
(2.71) SOLDER MASK
DEFINED PAD
SOLDER MASK
OPENING
8X (1.55) SEE DETAILS

1
8

8X (0.6)

(3.4)
SYMM 9 SOLDER MASK
(1.3)
TYP OPENING

(4.9)
NOTE 9
6X (1.27)

4 5
(R0.05) TYP
SYMM METAL COVERED
( 0.2) TYP BY SOLDER MASK
VIA
(1.3) TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:10X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK METAL SOLDER MASK METAL UNDER

OPENING OPENING SOLDER MASK

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

PADS 1-8

4214849/B 09/2025

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 ([Link]/lit/slma002) and SLMA004 ([Link]/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

[Link]
 EXAMPLE STENCIL DESIGN
DDA0008B PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE

(2.71)
BASED ON
0.125 THICK
STENCIL
8X (1.55) (R0.05) TYP
1
8

8X (0.6)

(3.4)
SYMM 9 BASED ON
0.125 THICK
STENCIL

6X (1.27)

5
4

METAL COVERED
SYMM SEE TABLE FOR
BY SOLDER MASK
DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.4)
THICKNESSES

SOLDER PASTE EXAMPLE

EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 3.03 X 3.80
0.125 2.71 X 3.40 (SHOWN)
0.150 2.47 X 3.10
0.175 2.29 X 2.87

4214849/B 09/2025

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
NGT0008A SCALE 3.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

4.1 B
A
3.9

PIN 1 INDEX AREA

4.1
3.9

C
0.8 MAX
SEATING PLANE

0.05 0.08 C
0.00

EXPOSED
2.6 0.05 (0.2) TYP
THERMAL PAD

4 5

2X SYMM
9
2.4 3 0.05

8
1
6X 0.8
0.35
8X
SYMM 0.25
PIN 1 ID
0.5 0.1 C A B
8X
0.3 0.05 C

4214935/A 08/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

[Link]
 EXAMPLE BOARD LAYOUT
NGT0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(2.6)
8X (0.6) SYMM

1
8X (0.3) 8

SYMM 9
(3)

(1.25)
6X (0.8)
4 5

(R0.05) TYP
( 0.2) VIA
TYP (1.05)
(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

EXPOSED EXPOSED
METAL METAL

SOLDER MASK METAL METAL UNDER SOLDER MASK

OPENING SOLDER MASK OPENING
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214935/A 08/2020

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 ([Link]/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

[Link]
 EXAMPLE STENCIL DESIGN
NGT0008A WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD

(0.675)

SYMM
METAL
8X (0.6) TYP

1
8X (0.3) 8

(0.755)
SYMM 9

6X (0.8) (1.31)

5
4

(R0.05) TYP
(1.15)

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9:
77% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4214935/A 08/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

[Link]
 GENERIC PACKAGE VIEW
DPR 10 WSON - 0.8 mm max height
4 x 4, 0.8 mm pitch PLASTIC SMALL OUTLINE - NO LEAD

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4232220/A

[Link]
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

[Link]
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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Last updated 10/2025