Tungsten Local Interconnection
• CMP PSG
• Wafer clean (a)
• Local interconnection mask (a)
• Etch PSG
• Strip photoresist
• Wafer clean (b) PSG
STI n+ n+ USG p+ p+
• Argon sputtering clean (b) P-Well N-Well
P-Epi
P-Wafer
• Sputtering Ti
• Sputtering TiN Ti/TiN Barrier and Adhesion Layer
• CVD TiN PSG Tungsten
STI n+ n+ USG p+ p+
• TiN treatment (c) P-Well N-Well
P-Epi
• CVD Tungsten (c) P-Wafer
• CMP Tungsten Ti/TiN Barrier and Adhesion Layer
• CMP titanium and titanium nitride (d) PSG Tungsten
n+
n+ USG p+ p+
• Wafer clean (d) STI P-Well N-Well
P-Epi
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] P-Wafer 121
Mask 10: Local Interconnection
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 122
Strip Photoresist/Clean
PSG
STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 123
PVD Ti/TiN and CVD TiN/W
Ti/TiN Barrier and Adhesion Layer
PSG Tungsten
STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 124
CMP W/TiN/Ti, Clean
Ti/TiN Barrier and Adhesion Layer
PSG Tungsten
STI n+ n+ USG p+ p+
P-Well N-Well
P-Epi
P-Wafer
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 125
Early Global Interconnection
• Oxide CVD
• Photolithography, oxide etch, and PR strip
• Metal PVD
• Photolithography, metal etch, and PR strip
– Oxide etch forms contact or via holes
– metal etch forms interconnection lines
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 126
Early Aluminum PSG
Interconnection (a) p+
n+ n+ SiO2
p+
p+
N-well
p+
P-type substrate
• CVD PSG (a)
PSG
• PSG reflow (b) SiO2
(b) p+ n+ n+
p+
p+ p+
• Wafer clean P-type substrate
N-well
• Contact hole mask PSG
SiO2
• Etch PSG (c) p +
n+ n+
p+
p+ p+
N-well
• Strip photoresist (c) P-type substrate
• Wafer clean Al ·Si
PSG
SiO2
• Deposit Al alloy (d) (d) p+
n+ n+
p+
p+ p+
N-well
• Metal interconnection mask P-type substrate
• Etch metal Al ·Si
PSG
• Strip photoresist (e) (e) p+
n+ n+ SiO2
p+
p+ p+
N-well
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 127
• Metal anneal P-type substrate
Multi-level Interconnection
• Earlier interconnection has rough surface
• problems in photolithography and metal PVD
• Tungsten to fill narrow contact and via holes
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 128
Multi-level Interconnection
• The basics interconnection process steps:
– Dielectric CVD and planarization
– Photolithography, oxide etch, and PR strip
– W CVD, bulk W removal
– Metal stack PVD,
– Photolithography, oxide etch, and PR strip
• PSG or BPSG for PMD and USG for IMD
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 129
Multi-level Interconnection
• Dielectric CMP for planarization
• W CMP to removal bulk tungsten
• Metal stack: Ti welding layer, Al·Cu alloy,
and TiN ARC
• Metal etch defines metal interconnection lines
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 130