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Hot Electron Effect in Transistor Design

The document discusses the process of transistor making, specifically focusing on the self-aligned gate and the hot electron effect, which can impact transistor performance and reliability. It describes the formation of lightly doped drain (LDD) to mitigate the hot electron effect through low energy ion implantation and the use of sidewall spacers. Additionally, it outlines various steps in the fabrication process, including poly etch, nitride deposition, and source drain implantation.

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yongfeng jia
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4 views10 pages

Hot Electron Effect in Transistor Design

The document discusses the process of transistor making, specifically focusing on the self-aligned gate and the hot electron effect, which can impact transistor performance and reliability. It describes the formation of lightly doped drain (LDD) to mitigate the hot electron effect through low energy ion implantation and the use of sidewall spacers. Additionally, it outlines various steps in the fabrication process, including poly etch, nitride deposition, and source drain implantation.

Uploaded by

yongfeng jia
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Transistor Making:

Self-aligned Gate
Phosphorus Ions

Polysilicon
Gate
n+ n+
Gate oxide
p-Si

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 81


Hot Electron Effect
• Gate width is < 2 microns,
• Vertical electric field accelerates electrons
tunneling through the thin gate oxide layer
• Hot electron effect
– gate leakage affect transistor performance
– trapping of electrons in the gate oxide cause
reliability problems for the IC chips
• LDD is used to prevent hot electron effect
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 82
Hot Electron Effect
VG>VT>0 VD > 0

Poly Si
Gate oxide
n+ e− n+
p-Si Electron
Source Drain
injection

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 83


LDD Formation
• Low energy, low current ion implantation
– very low dopant concentration and shallow
junction just extended underneath the gate
• Sidewall spacers can be formed by
depositing and etching back dielectric layers
• High current, low energy ion implantation
forms the heavily doped source/drain
– Source/drain are kept apart from the gate
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 84
LDD Formation
• Reduce the vertical electric field of the
source/drain bias
• Reduce the available electrons for tunneling
• Suppress the hot electron effect

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 85


Poly Etch, PR Strip and Poly Anneal

Gate oxide Polysilicon


Gate

p-Si

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 86


LDD implantation

Gate oxide Polysilicon


Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 87


Nitride Deposition

Nitride
Gate oxide Polysilicon Layer
Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 88


Nitride Etch Back

Sidewall
Gate oxide Polysilicon Spacer
Gate
n- n-

p-Si LDD, n–

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 89


Source Drain Implantation

Sidewall
Gate oxide Polysilicon Spacer
Gate
n+ n+

p-Si LDD, n–

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 90

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