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Advanced MOSFET Fabrication Techniques

The document discusses various processes and materials used in the fabrication of Metal and High-κ Gate MOSFETs, including the use of tungsten and tantalum pentaoxide. It outlines different interconnection techniques, such as local interconnections and tungsten silicide processes, highlighting their advantages and methods. Additionally, it covers self-aligned silicide processes and the benefits of using cobalt for lower resistance and higher speed in interconnections.

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yongfeng jia
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5 views10 pages

Advanced MOSFET Fabrication Techniques

The document discusses various processes and materials used in the fabrication of Metal and High-κ Gate MOSFETs, including the use of tungsten and tantalum pentaoxide. It outlines different interconnection techniques, such as local interconnections and tungsten silicide processes, highlighting their advantages and methods. Additionally, it covers self-aligned silicide processes and the benefits of using cobalt for lower resistance and higher speed in interconnections.

Uploaded by

yongfeng jia
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CVD Tungsten

Tungsten
PSG W PSG

STI STI

P-well

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 111


CMP Tantalum Pentaoxide

Silicon Nitride Tungsten Gate

PSG W PSG

STI n+ n+ STI

P-well Ta2O5 Gate Dielectric

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 112


Metal and High-κ Gate MOSFET
Dummy Gate Process
• For < 0.1 µm IC device
• PSG CMP, polysilicon and oxide stripping,
and high-κ dielectric deposition.
• Ta2O5, κ ~ 25, TiO2 κ up to 80, and HfO2
• CVD plus RTA process
• It may never be used due to complexity
• Advantage: can used Ta2O5 hard hard to etch.
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 113
Metal and High-κ Gate MOSFET
Traditional Process
• Traditional MOSFET making process in R&D
– Dielectric deposition and annealing
– Metal deposition
– Photolithography
– Metal etch
– Ion implantation
– Rapid thermal annealing.
• Too early to predict which method will win
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 114
Interconnection
• Making transistor: front-end
• Interconnection: back-end
– Multi metal layers with dielectric in between
– Local interconnection: silicide
– PMD: doped oxide, PSG or BPSG
– W and Al alloy metallization
– IMD: USG and FSG
– Transition to copper and low-κ interconnection
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 115
Local Interconnection
• Connection between neighboring transistors
• Usually polysilicon or polycide stack
• WSi2, TiSi2, and CoSi2 are commonly used
– WSix: CVD process with WF6 and SiH4
• TiSi2: PVD Ti on Si then thermal anneal

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 116


Tungsten Silicide Process
• Wafer clean Tungsten silicide
(a) Amorphous silicon
• Grow gate oxide STI STI

P-well
• Deposited amorphous silicon

• Deposited tungsten silicide (a) Photoresist


Tungsten silicide
• Gate and local interconnection mask (b) Amorphous silicon
STI STI

• Etch tungsten silicide (fluorine chemistry) (b) P-well Gate oxide

• Etch amorphous silicon (chlorine chemistry)


Tungsten Silicide
• Strip photoresist Polysilicon
(c) STI STI
• Polysilicon and silicide annealing (c) P-well Gate oxide

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 117


Self-aligned Silicide (Salicide)
• TiSi2 and CoSi2
• Lower resistivity than WSi2
• TiSi2 when gate size > 0.2 µm
• CoSi2 when gate size < 0.2 µm
• Metal (Ti or Co) PVD
• Thermal anneal to form silicide
• Strip unreacted metal
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 118
Cobalt Self-aligned Silicide Process
Cobalt Deposition Sidewall Spacer

STI Silicon

Cobalt
RTP Silicide Alloying

Silicon
Strip Unreact Cobalt
Cobalt Silicide
Polysilicon

Silicon
Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 119
Gate Oxide
Tungsten Local Interconnection
• Lower resistance, higher speed, less power
• Damascene: similar to W plug formation
– Etched trenches are in silicate glass layer
– Deposit Ti and TiN barrier/adhesion layers
– CVD W fill trenches
– CMP to remove bulk W from wafer surface
– W left in trenches to form local interconnection

Hong Xiao, Ph. D. [Link]/HongXiao/[Link] 120

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