Digital Circuit Design
More Fun with NMOS
• Get Rid of the Resistors
The technology did not have a good way to
make resistors
Wanted to speed up the Rise time
• People first tried Using a NMOS
transistor
Operated in Saturation all the time
Not used in production (We can do the
EE 224 notesmath, so we study it)
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VDS=VGS If VT is positive,
VDD
always in saturation
L
OUT VOH = VDD-VT
A I
Remember that VT
has the VSB when
at VOH
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k
2
2 V V
2(VOH VT )VOL VOL DD OL
RL
1 2V VOL is small, VOL2 goes
VOL 2 VDD VT VOL DD 0
2
kR
L kRL
VDD
VOL
1 kRL (VDD VT )
dVOUT dI dVOUT Since RL is gone
D 1 we use this
dVIN dVIN dI D
for many NMOS
k LVDS
1 derivations
k L (VGS VT VDS )
VIN VT
VOUT
2 The current is set by IDI
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Two currents are equal for L=load, and I=inverter Transistor.
L is in saturation (Always)
I is in Linear region at VOL (VOL should be < VT for good logic)
kL
2
VGSL VTL 2 k I 2(VIH VTI )VOL VOL 2
2
V DD VOUT VTL k 2(V
* 2
R IH VTI )VOL VOL
2
*
VTL VTL @ VOL
This is a 4th order equation, and is normally solved by trial and error.
Better Yet, Use Spice!
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Inverter is saturated since VIL is near VTI (Check Later)
dVout dI DI dVDSL
1
dVin dVGSI dI DL
k I (VGSI VTI )
From Earlier Results. Both saturated
k L (VGSL VTL )
2k I I DI
Restate as Currents
2k L I DL
kR Currents are equal
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Using the NMOS results, and solving for the case IDL=IDI
VIN VTI Leave out
VOUT
2
kI
2
2
k
2(VIN VTI )VOUT VOUT L VDD VOUT VTL
2
2
Sub for VOUT
2VDD VTL
VIH VTI Brought to you by the magic of
3K R 1 Algebra
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• The Load Transistor has a negative
Threshold
Gate Tied to Source
VGS=0V
• That’s OK since the Threshold is Negative
• Often drawn with a fat bar to represent
the implant!
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VDD
VGSL=0V VTL~-3V VDD ~ 5V
D VDS <VGSL-VTL => Linear for VOH
VDS>VGSL-VTL => Saturated for VOL
out
A
E
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Designed a “Buried Contact”
Easy since the gate is tied to the Source
Contact
POLY
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VDD
Depletion Load
GND
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• Transistor Conducts All the way to VDD
VOH = VDD
Enters the linear mode VDS < VGS-VT
• VGS=0V
• VT is typically -2 to -3 V
• When VDS < -VT, enters linear mode
– Still Conducts in Linear mode
Need to consider Body effect on VTD
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• Both Transistor conduct during VOL
Load Transistor is in Saturation
• VDS > -VTL (Assuming VTL is -3V)
• Verify later
Inverter Transistor is in Linear mode
• VDS < VGS-VTI
• Verify Later
• Assume VIH is VDD for Ease of Calculation
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kI
2
VDD VTI VOL VOL 2 k L [VTD (VOL )]2
2
This equation is solved iterativly since VTD(VOL) results in a high
order equation.
Typically a VOL of .3 to 0.5V is chosen, and then iterated until
VTD(VOL) is correct.
In the real world, Spice is used to fine tune the results
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VIL is found as before (Many assumptions here)
dVOUT dI dVDSL Often solved by
DI 1
dVIN dVGSI dI DL assuming VTL(VOUT)
is constant, and then
k I VGSI VTI iterating
1
k L VGSL VTL (VOUT ) VDSL
VDSL VDD VOUT
VOUT K R (VGSI VTI ) VGSL VTL (VOUT ) VDD
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• The Load is saturated, and the Inverter
transistor is in the linear region.
• VOUT=(VIN-VTI)/2
• Assume the Drain Current doesn’t
change much going from VOL to the
knee at VIH
• Substitute VOUT from above into Current
equation
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I DL
kL
2
2(VIH VTI )VDS VDS
2
(V VTI )
VOUT VDS IH
2
kL
2
2( 2VDS )VDS VDS
2
2
3K LVDS
I DL
2
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• Plug in the current from the VOL
calculations, and solve for VIH
• This is an approximation
• Use Spice to get closer
• Design, then Tune
• Assumes output transistor controls
current
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• To calculate delay times, we need to
understand the capacitance of the MOS
transistor
• Comes from several Places
Gate
Source and Drain Diodes
• Often called Bottom and side wall capacitance
• Connection Capacitances
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• Gate and Junction capacitance
dominated
We just ignored the interconnect
capacitance
• Oxides were thick
• Transistors were huge
• Single well processes
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• Interconnect capacitance is a major part
of the total capacitance
Leads to one of the “Deep Sub Micron”
problems people have
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q NA
C j0 SI
2 0
NAND
0 VT ln 2
PB
ni
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Area of the Source and Drain
Used for the bottom Junction
Perimeter of the Source and Drain
Used for the Side Wall Junction
The Capacitance is Voltage Variable!!!
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CGD CDB
Two are Voltage
Variable
CGS CSB
CGB
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Q Q (V2 ) Q(V1 )
Ceq K eq C j 0
V V2 V1
1/ 2
2 0
V2 V1
1/ 2 1/ 2
K eq 0 0
V2 V1
This is almost always done in Spice. We supply the parameters, and
Spice computes the capacitance.
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• The calculations are intense
• The solutions do not fall out of algebra
• This can be done only for simple circuits
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• Only need to focus on the capacitances
where there is a changing voltage
• Remove any “DEAD” capacitances from
calculations
• Feed Through capacitance may have
an impact on the result
• Slew rate will impact the switching time
How much voltage is getting to the gate
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