1

CHAPTER 5
SYNCHRONOUS
SEQUENTIAL LOGIC
This chapter outlines the formal procedures for the analysis
and design of clocked (synchronous) sequential circuits.
The gate structure of several types of flip-flops, both level
and edge-triggered, is presented. Examples are used to
derive state table and state diagram for analysis of
sequential circuits. A number of design examples are
presented. Finite state machines using Melay and Moore
models are studied.
 2

5.2 Sequential Circuits

• A Sequential Circuit is one whose output depends upon
present inputs and current outputs (past inputs).

• Outputs are frequently also referred as states of the circuit

that is currently known condition.

• Two Types of Sequential Circuits:

• Asynchronous: Output changes as soon as Input changes.
• Synchronous: Output changes at specific instants of time controlled
by a signal called clock. (A similar pin to enable in combinational
circuits)
 3

5.2 Sequential Circuits

• All sequential circuits have memory elements that
somehow store information of past scenario.
 4

5.2 Sequential Circuits

• In asynchronous sequential circuits, these memory
elements are called Latches.

• In synchronous circuits, we call them flip-flops.

• Flip-Flops are advanced form of latches and only store

information when triggered by clock whereas latches store
or change information at the change of input (or certain
combination of inputs.)
 5

5.2 Sequential Circuits

• State, output or storage of a latch are one and the same
thing.

• One latch or flip-flop can store only one bit. i.e. one bit’s
status 1/0.

• Let’s make a one-bit latch, that can store one-bit

information.
 6

5.2 Contd. (Sequential Circuit Types)

• There are two types of sequential circuits Synchronous
and Asynchronous.

• A synchronous sequential circuit is a system whose

behavior can be defined from the knowledge of its signals
at discrete (specific) instants of time.

• Storage elements in synchronous circuits are affected at

discrete instants of time only.
 7

5.2 Contd. (Sequential Circuit Types)

• An asynchronous sequential circuit depends on the
input signals at any instant of time and the order in
which the inputs change.

• Storage elements in asynchronous circuits are usually

time-delay devices.

• The storage capability of time-delay devices is due to

the time it takes for the signal to propagate through the
device.

• It is also regarded as combinational circuit with

feedback.
 8

5.2 Contd. (Synchronous Sequential Circuits)

• Synchronous circuits employs signals that affect storage
elements only at discrete instants of time.

• Synchronization is achieved by a timing device called

clock generator.

• A clock generator generates a periodic train of clock

pulses.

• The clock pulses are distributed throughout the system in

such a way that storage elements are affected only with
the arrival of each pulse.
 9

5.2 Contd. (Synchronous Sequential Circuits)

• Synchronous sequential circuits that use clock pulses in
the inputs of storage elements are called clocked
sequential circuits.

• These are most commonly used having no instability

problems. The memory elements used in these circuits
are flip-flops.
 10

Read through today’s

lecture once
 11

5.3 Storage Elements: Latches

• A flip flop circuit can maintain a binary state indefinitely
(as long as power is maintained) until directed by an input
signal to switch states.

• Flip flops are categorized by the number of inputs they

possess and the manner in which the inputs affect the
binary state.

• Latches are the most basic flip flop and they operate with
signal levels.
 12

5.3 Storage Elements: Latches

• Latches are useful for storing binary information and for
the design of asynchronous sequential circuits.

• Latches are the building blocks for all flip flops.

• Latches are level-triggered, are bound to change the

output as soon as the input changes (after a little
propagation delay), whereas flip flops are edge-triggered
and change the output at the clock transition.
 13

5.3 Contd. (SR Latch)

• The SR latch is a circuit with two cross-coupled NOR
gates or two cross-coupled NAND gates.

• There are two outputs Q and Q’. Q’ always being the

complemented version of Q.

• There are two inputs:

• S is for set. (Q=1, Q’=0)
• R is for reset. (Q=0, Q’=1)

• Since, two inputs (S/R) can have 4 combinations, there

can be 4 types of outputs. (Next slide)
 14

5.3 Contd. (SR Latch: NOR Gates)

NOR
14 Gate
Table

Manual I/O Explanation

 15

5.3 Contd. (SR Latch: NAND Gates)

NAND
15 Gate
Table

Manual I/O Explanation

More Appropriately 𝑆ҧ𝑅ത Latch

 16

5.3 Contd. (SR Latch: Control input)

NAND Table
𝑆ҧ 𝑅ത Q Q’
0 0 forbidden
0 1 1 0
1 0 0 1
1 1 No change
 17

5.3 Contd. (D Latch: Transparent Latch)

• If R and S can never be equal to 1 at the same time,
undefined or intermediate state can not occur.
S

En

No change ≈ Storage
 18

5.3 Contd. (Graphic Symbols)

S R Q Q’ 𝑆ҧ 𝑅ത Q Q’ En D Q Q’
0 0 No change 0 0 Forbidden 0 X No change
0 1 0 1 0 1 1 0 1 0 0 1
1 0 1 0 1 0 0 1 1 1 1 0
1 1 Forbidden 1 1 No change
 19

Revise
Cross-Coupled
NAND/NOR Latch,
SR-Latch & D-Latch
 20

5.4 Storage Elements: Flip-Flops

Clock Responses/Trigger in Latch/Flip Flop

 21

5.4 Contd. (Edge-Triggered D-Flip Flop)

Negative
Positive Edge Triggered
Response on positive transition
Clk

Q
 22

5.4 Contd. (Edge-Triggered D-Flip Flop)

Clk

Q
 23

NAND Table 1
5.4 Contd. 1(Edge-Triggered
0 D-Flip Flop)

0
1
0
0
1 1
0

𝑆ҧ 𝑅ത Q Q’

1 0 0 forbidden

0 1 0 1 1 0
1 0 0 1
1 1 No change
 24

NAND Table 1
0
1

0
1
01
0 1
1 01
01

𝑆ҧ 𝑅ത Q Q’
0 0 forbidden
01
0 1 0 1 1 0
1 0 0 1
1 1 No change
 25

NAND Table 0
1
1

1
1
0
0
1 1
0
0

𝑆ҧ 𝑅ത Q Q’

1 0 0 forbidden

1 0 0 1 1 0
1 0 0 1
1 1 No change
 26

NAND Table 0
1
01

1
01
01
0 1
1 1
01
0

𝑆ҧ 𝑅ത Q Q’

1 0 0 forbidden

1 0 0 1 1 0
1 0 0 1
1 1 No change
 27

5.4 Contd. (Graphic Symbols for Flip Flop)

Dynamic
Input
 28

5.4 Contd. (Other Flip Flops: JK-FF)

• Synchronous with clock. Current output state also depend

upon clock transition.
• D=JQ’+K’Q
• When J=1,K=0, D=Q’+Q=1 (o/p of D flip flop =1)
• When J=0, K=1, D=0+0=0
• When J=0, K=0, D=0.Q’+1.Q=Q (No change)
• When J=1,K=1, D=1.Q’+0.Q=Q’ (Complemented)
 29

5.4 Contd. (Other Flip Flops: T-FF)

• Synchronous with clock. Current output state also

depend upon clock transition.
• From JK flip-flop, J=K=T
• When T=J=K=0, D=Q (No change)
• When T=J=K=1, D=Q’ (Complemented)
 30

5.4 Contd. (Other Flip Flops: T-FF)

• Synchronous with clock. Current output state also

depend upon clock transition.
• From D flip-flop, D=T⨁Q=TQ’+T’Q
• Now, when T=0, D=0.Q’+1.Q=Q
• When T=1, D=1.Q’+0.Q=Q’
 31

5.4 Contd. (Characteristic Tables)

• Characteristic Tables define the next state (i.e. after clock
transition) as a function of inputs and the present state in
tabular form.
• Q(t) refers to the present state and Q(t+1) refers to the
next state one clock period later.
• Clock edge input is not included in the characteristic
tables.
 32

5.4 Contd. (Characteristic Equations)

• Characteristic equations express the next state
algebraically in the form of an equation.
• For D flip-flop: Q(t+1)=D
• For JK flip-flop: Q(t+1)=JQ’+K’Q (Q refers to Q(t))
• For T flip-flop: Q(t+1)= T ⨁ Q = TQ’+T’Q
 33

5.4 Contd. (Direct Inputs)

• Clock independent inputs can still be introduced in the
synchronous circuits. e.g. A reset input that turns the
output 0, without depending upon clock.

• It is also useful to use this input to reset the circuit, as

after powering on, the circuit might be in an intermediate
or undefined state.

• Such a circuit with reset as an asynchronous (or direct)

input is shown in the next slide.
 34

5.4 Contd. (Direct Inputs)

1 1
0
0 1

1
0

1
0
0
 35

5.4 Contd. (Direct Inputs)

Reset=1 alone cannot

1 decide behavior of
1 circuit.
 36

Perform Analysis of all

the circuits thoroughly.
Better to solve once on
notebook.
 37

5.5 Analysis of Clocked Sequential Circuits

• A logic diagram is recognized as a clocked sequential
circuit if it includes flip-flops with clock inputs.

• The flip-flops may be of any type, and the logic diagram

may or may not include combinational gates.

• Analysis of Sequential circuits include obtaining a table or

a diagram for the time sequence of inputs, outputs, and
internal states

• It is recommended to write equations for the sequential

circuits before obtaining table.
 38

5.5 Contd. (State Equations)

• A state/transition equation specifies the next state as a
function of the present state and input.

• For upper flip-flop, A(t+1)=A(t)x(t)+B(t)x(t), where (t)

denotes the present state and (t+1) denotes the next state
after the clock transition.

• For lower flip-flop, B(t+1)=A’(t)x(t)

• Since y is a combinational output, it is expressed as

current state(present time). Thus y(t)= [A(t)+B(t)]x’(t).
Copy Diagram on Board
 39

5.5 Contd. (State Equations)

Ax
DA
Ax+Bx
Bx

A’x DB

A+B

(A+B) x’
x’
 40

5.5 Contd. (State Equations)

• Since all variables in Boolean expression are the function
of present state, we can omit the designation (t) and
hence

• A(t+1)=A(t)x(t)+B(t)x(t) → A(t+1)=Ax+Bx
• B(t+1)=A’(t)x(t) → B(t+1)=A’x
• y(t)=[A(t)+B(t)]x’(t) → y= (A+B)x’

• Note that the ‘combinational’ output is defined only for the

present state i.e. y(t)
 41

5.5 Contd. (State Table)

• The time sequence of the inputs, outputs and flip-flop
states can be enumerated in a state/transition table.

• It is normally obtained using the state equations, unlike in

the combinational circuit where we directly make the truth
table from the analysis of the circuit.

• The derivation of state table requires the listing of all the

possible combination of the present state and input.
 42

5.5 Contd. (State Table)

• In the current scenario, there are two present states and
one input, the binary combinations will be from 000 to 111.

• One form of state table has four columns, one for present
state and one for input, which are both considered as
inputs. (State Table : Form-I)

• The other two columns are for next state and output,
which are both considered as outputs.

• For m D flip flops with n inputs, the no. of columns for

input would be m+n and the combination will go from 0 to
2m+n-1. In previous case 2 D flip-flops and 1 input.
 43

5.5 Contd. (State Table : Form-I)

0, where
1, x isx0
1,where
where and
xisis A and
01and
andAAorBB
is both
is 1zero
zero
• A(t+1)=Ax+Bx
• B(t+1)=A’x Inputs Outputs
Present
• y=(A+B)x’ Input Next State Output
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
 44

5.5 Contd. (State Table)

• Another form of state table is where there are three
columns, one for present state, one for next state and one
for output. (State Table : Form-II)

• The input conditions are enumerated under the next-state

and output sections.

• The choice of the state table form depends upon the

application.
 45

5.5 Contd. (State Table : Form-II)

• A(t+1)=Ax+Bx
• B(t+1)=A’x
Present Next State Output
• y=(A+B)x’
State x=0 x=0 x=1 x=1 x=0 x=1
A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
 46

5.5 Contd. (State Diagram)

• Information from state table can be represented
graphically in the form of a state diagram.

• There is no difference between a state table and state

diagram except in the manner of representation. In fact
state diagram follows directly from the state table.

• The state diagram gives a pictorial view of state

transitions and is more suitable for human interpretation.
 47

5.5 Contd. (State Diagram)

• In the state diagram, a state is represented by a circle,
and the (clock-triggered) transitions between states are
indicated by directed lines (one-headed arrow) connecting
the circles.

• The binary number inside the circle identifies the state of

the flip-flops.

• Directed lines are labeled with two binary numbers

Input/Output
separated by a slash.

Present Next
State State
 48

5.5 Contd. (State Diagram)

• The input value during the present state is labeled first (on
right), and the number after the slash gives the output
during the present state with the given input.
• The present state is the one connected to arrow tail.
 49

5.5 Contd. (State Diagram)

Inputs Outputs
Present
Input Next State Output
State
A B x A B y
Manually draw state
0 0 0 0 0 0
diagram on Board
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0
1 1 0 0 0 1
1 1 1 1 0 0
Circuit Diagram → Equations → State Table → State Diagram
 50

5.5: Very important topic

Still to go…
 51

5.5 Contd. (Flip Flop Input Equations)

• The logic diagram of a sequential circuit consists of
combinational circuits and flip-flops.

• A part of the combinational circuit sometimes generate

external outputs which can be described algebraically by
a set of Boolean functions called output equations.

• Other part of the combination circuit will generate the

inputs to flip-flops whose algebraic expression will be
known as flip-flop input equations. (or excitation
equations)
 52

5.5 Contd. (Flip Flop Input Equations)

• Since the next state of the flip-flop(and the circuit)
depends upon the input of the flip flop, flip-flop input
equations play a significant role in easing the analysis of
the sequential circuit.

• Instead of directly defining the next state in terms of

previous state and input, the flip-flop input equations are
defined and the states are determined using the flip-flop
input equations.
 53

5.5 Contd. (Flip Flop Input Equations)

• To write the flip-flop input equation, the input of the flip-
flop is followed by a subscript of the name of the state.

• For example, if a D-flip-flop whose output state is Q, is a

function of x ORED with y, the flip-flop input equation will
be written as DQ=x+y.

• Normally, there are more than one flip-flop in the

sequential circuit and the states are defined starting
alphabetically e.g. A, B and so on. Thus, the symbol on
left hand side of the input equation become DA, DB e.t.c.
 54

5.5 Contd. (Flip Flop Input Equations)

• In the previous circuit, flip-flop input equations can be
written as DA=Ax+Bx and DB=A’x and y=(A+B)x’

• For the D-flip flop, state equation will be identical to the

input equation since Q(t+1)=DQ.
 55

5.5 Contd. (Analysis with D Flip-Flops)

• Flip-Flop Input Equation:
• DA=(A⊕x⊕y)
• A(t+1)=(A⊕x⊕y)

• Since, there are no combinational outputs, the state itself

is regarded as output of the circuit.
State Diagram: First Draw Manually
 56

5.5 Contd. (Analysis with JK Flip-Flops)

• The next state values can also be obtained by evaluating
the state equations from the characteristic equations.

• This is done by using the following procedure:

1. Determine the flip-flop input equations in terms of the present
state and input variables.
2. Substitute the input equations into the flip-flop characteristic
equation to obtain the state equations.
3. Use the corresponding state equations to determine the next-
state values in the state table.
 57

5.5 Contd. (Analysis with JK Flip-Flops)

1. Determine the flip-flop input equations in terms of the
present state and input variables.

• JA=B
JA
• KA=B.x’
KA
• JB=x’
• KB=A⊕x
JB

KB
 58

5.5 Contd. (Analysis with JK Flip-Flops)

2. Substitute the input equations into the flip-flop characteristic
equation to obtain the state equations.
• JA=B ; KA=B.x’ ; JB=x’ ; KB=A⊕x

• Q(t+1)= JQ’+K’Q

• A(t+1)=JAA’+KA’A
• A(t+1)= BA’+(B.x’)’A
• A(t+1)= A’B+A(B’+x)
• A(t+1)=A’B+AB’+Ax

• B(t+1)=JBB’+KB’B
• B(t+1)= x’B’+(A⊕x)’B
• B(t+1)= B’x’ + (Ax+A’x’)B
• B(t+1)=B’x’+ABx+A’Bx’
 59

5.5 Contd. (Analysis with JK Flip-Flops)

3. Use the corresponding state equations to determine
the next-state values in the state table.
A(t+1)=A’B+AB’+Ax B(t+1)=B’x’+ABx+A’Bx’
 60

5.5 Contd. (Analysis with JK Flip-Flops)

• The state diagram only depends upon the knowledge of
circuit inputs and outputs, not flip-flop inputs.
A(t+1)=A’B+AB’+Ax B(t+1)=B’x’+ABx+A’Bx’

State Diagram: First Draw Manually

 61

5.5 Contd. (Analysis with T Flip-Flops)

• The analysis of a sequential circuit with T flip-flops follows
the same procedure outlined for JK flip-flops.

• The next state values of a sequential circuit that uses JK-

or T-type flip-flop can be derived as follows:
1. Determine the flip-flop input equations in terms of the present
state and input variables.
2. List the binary values of each input equation.
3. Use the corresponding flip-flop characteristic table to determine
the next-state values in the state table.
2. Substitute the input equations into the flip-flop characteristic
equation to obtain the state equations.
3. Use the corresponding state equations to determine the next-
state values in the state table.
 62

5.5 Contd. (Analysis with T Flip-Flops)

• TA=B.x TA

• TB=x
• y=A.B , Note that y is
only dependent upon
the states and that too
on present states only. TB
 63

5.5 Contd. (Analysis with T Flip-Flops)

• TA=B.x
• A(t+1)=TAA’+TA’A = B.x.A’ + (B.x)’A = A’Bx+AB’+Ax’
• TB=x
• B(t+1)=TBB’+TB’B = xB’ + x’B = B’x + Bx’
• y=AB
 64

5.5 Contd. (Analysis with T Flip-Flops)

State Diagram: First Draw Manually

 65

5.5 Contd. (Mealy and Moore FSM)

• The are two different models of the sequential circuit that
are only distinguished by the way the output is generated.

• Where the output depends upon the present states and

the input (directly), the (state diagram of the) sequential
circuit is represented by Mealy State Machine.

• Since, in this type of Machine, the input affects the output

(directly), this is the one where arrow heads are labeled
with input-output combination separated by a slash.
 66

5.5 Contd. (Mealy and Moore FSM)

• In Moore State machine, output either only depends upon
the present state of the machine and the input does not
(directly) affect the output or the output(s) of the machine
are state(s) themselves.

• The term state machine is referred to the state diagram of

the sequential circuit.

• The two models of the sequential circuit are commonly

referred to as a finite state machine, abbreviated FSM.
 67

5.5 Contd. (Mealy and Moore FSM)

• In a Moore model, the outputs of the sequential circuit are
synchronized with the clock, because they depend only
on flip-flop outputs that are synchronized with the clock.

• Whereas, the output of the Mealy machine is the value

that is present immediately before the active edge of the
clock.
 68

5.5 Contd. (Mealy or Moore?)

Mealy Moore

Moore
Moore
 69

End of Topic 5.5

5.6 Not Included
Quiz for Analysis of JK
and T flip flop, both
methods
 70

5.7 State Reduction and Assignment

• The analysis of sequential circuits starts from a circuit
diagram and culminates in a state table or diagram.

• Whereas the design (synthesis) of a sequential circuit

starts from a set of specifications and culminates in a
logic diagram.

• Two sequential circuits may exhibit the same input-output

behavior, but have a different number of internal states in
their state diagram.
 71

5.7 State Reduction and Assignment

• The above is true when state diagrams of two different
circuits may be compared. But while designing, from the
problem statement, one cannot tell that the problem may
have an equivalent solution with the reduced number of
states.

• But, while designing, if state reduction algorithms are

applied, the equivalent circuit (in terms of input-output
behavior) with reduced number of states may be
produced. This section is all about that.

• Reducing states leads to reduction of gates and flip flops

which reduces the cost of the circuit.
 72

5.7 Contd. (State Reduction)

• The reduction in the number of flip-flops in a sequential circuit
is referred to as the state-reduction problem.

• State-reduction algorithms are concerned with procedures for

reducing the number of states in a state table, while keeping
the external input–output requirements unchanged.

• Since m flip-flops produce 2m states, a reduction in the number

of states may (or may not) result in a reduction in the number
of flip-flops.

• An unpredictable effect in reducing the number of flip-flops is

that sometimes the equivalent circuit (with fewer flip-flops) may
require more combinational gates to realize its next state and
output logic.
 73

5.7 Contd. (State Reduction)

• State reduction is mostly applied where we are interested
only in input-output sequence rather than the number of
state themselves.

• In contrast, if the states themselves are considered

outputs, we cannot reduce the states and hence the flip-
flops e.g. Counters

• Let us take as an example a state diagram of a circuit(in

next slide) and see if we can reduce it. Since we are only
interested in the input-output sequence and not the
states, we can represent different states by alphabets.
 74

5.7 Contd. (State Reduction)

• Example input sequence applied
01010110100 (one of many
sequences) , starting with
state - a

/
 75

5.7 Contd. (State Reduction)

• Now, let’s assume that we have found a sequential circuit
whose state diagram has fewer than seven states, and
applying the identical input sequences to the two circuits
generates identical output sequences for all the input
sequences then the two circuits are said to be equivalent
(only for input-output).

• The problem of state reduction is to find ways of reducing

number of states without altering input-output
relationships.
 76

5.7 Contd. (State Reduction)

• The following algorithm for the state reduction of a
completely specified state table is given here without
proof: “Two states are said to be equivalent if, for each
member of the set of inputs, they give exactly the same
output and send the circuit either to the same state or to
an equivalent state.”

• We proceed by making state table from state diagram and

eliminating one of the two states that gives exactly the
same output for all the possible combination of inputs and
go to the same next state.
 77

5.7 Contd. (State Reduction)

• Note that, making state table using the alphabets for the
states (of the circuit) rather than the binary combination
will be easier and the resulting state
table can more appropriately be
referred to as transition table.

Looking
e=g, eliminate
for equivalent
g and replace
states is
g as
by e
easy
in table
as finding identical rows
 78

5.7 Contd. (State Reduction)

• Repeat the same procedure with the newly obtained state
table until you don’t find equivalent states.

d
d

Looking
d=f, eliminate
for equivalent
f and replace
statesf is
byas
d in
easy
table
as finding identical rows
 79

5.7 Contd. (State Reduction)

• Repeat the same procedure with the newly obtained state
table until you don’t find equivalent states.

If there are no further equivalent states, then this is it…

 80

5.7 Contd. (State Reduction)

• Now, if the same sequence is applied, you will notice that
the states replaced will also have effect on the sequence
of the switching of the state but no effect at input-output
sequence

e=g & d=f

 81

5.7 Contd. (State Assignment)

• When Binary or Gray code assignment is used m states
are encoded using n-bits, where 2n≥m. Each bit
represents a flip-flop, so to represent m states, n flip flop
can be used, whose unique combinations can be
assigned to the individual states.

• If m≤2n, which is usually the case, the unused binary

combinations can be used as don’t cares and help in
simplifying the circuit while designing.

• In one-hot assignment, one flip-flop is required to

represent one state.
 82

5.7 Contd. (State Assignment)

• After the state reduction and assignment, one may
convert the transition table to state tableUnused
and is able to
design the logical (sequential) circuit from there, as will be
combinations,
done in the next section. next state
and outputs
don’t care
 83

5.8 : “Everest” of the

course
 84

5.8 Design Procedure

• The procedure for designing synchronous sequential circuits
can be summarized by a list of recommended steps:
1. From the word description and specifications of the desired
operation, derive a state diagram for the circuit.
2. Reduce the number of states if necessary. (Reduce states if
possible till there are no equivalent states) [state-table first]
3. Assign binary values to the states.
4. Obtain the binary-coded state table.
5. Choose the type of flip-flops to be used.
6. Derive the simplified flip-flop input equations and output
equations.
7. Draw the logic diagram.
 85

5.8 Contd. (Design Problem)

• Design a circuit that detects a sequence of three or more
consecutive 1’s in a string of bits coming through an input
line (i.e., the input is a serial bit stream )

• Three consecutive 1’s, starting from initial state, each ‘1’

input transits to the next state, each ‘0’ input resets the
system to the initial state, so initial state + 3 next states= 4
states.

• Output will be ‘1’ only when the last state is achieved.

(State dependent output = Moore Model.)
 86

5.8 Contd. (Step-I: State Diagram)

First Draw Manually
 87

5.8 Contd. (Step-II: State Reduction)

• Make state table and look for reduction.

Present Next State Output

State
x=0 x=1 (P.S.)
S0 S0 S1 0
S1 S0 S2 0
S2 S0 S3 0
S3 S0 S3 1

No row is identical for inputs, no reduction

 88

5.8 Contd. (Pre-Step-III: State Table-Form I)

• Form-I state table helps to find equation easier than
Form-II but Form-II helps in state reduction.
Present Input Next Output
State State
Present Next State Output x y
State
S0 0 S0 0
x=0 x=1 (P.S.) S0 1 S1 0
S0 S0 S1 0 S1 0 S0 0
S1 S0 S2 0 S1 1 S2 0
S2 S0 S3 0 S2 0 S0 0
S2 1 S3 0
S3 S0 S3 1
S3 0 S0 1
S3 1 S3 1
 89

5.8 Contd. (Step-III/IV: State Assignment

+ Binary State Table)
P.S Input N.S Output
. .
x y
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S0 0
S2 1 S3 0
S3 0 S0 1
S3 1 S3 1

So=00, S1=01, S2=10, S3=11 Four States, Two bits, two flip-flops
 90

5.8 Contd. (Step-III/IV: State Assignment +

Binary State Table)
• So=00, S1=01, S2=10, S3=11, Two Flip-Flops A & B

Present Input Next Output

State State
x y
S0 0 S0 0
S0 1 S1 0
S1 0 S0 0
S1 1 S2 0
S2 0 S0 0
S2 1 S3 0
S3 0 S0 1
S3 1 S3 1
 91

5.8 Contd. (Step-V: Flip-Flop Type)

• We may choose D, JK or T Flip-Flop to design our circuit.
It is recommended to choose all the flip-flops to be of one
type for the circuit. For example, we have to use two Flip-
Flops A & B, so either choose both of them to be D or JK
or T type Flip-Flop.

• The method to find Flip-Flop Input Equations (Step-VI)

and thus the Logic Diagram (Step-VII) differs if we choose
a different type of flip-flop.

• We will use the same state-table to cover the methods for

finding the flip-flop input equations for all three flip-flops.
Output equations have only one method.
 92

5.8 Contd. (Step-VI: Synthesis with D-FF)

• Since we have four states, we choose two D Flip Flops,
label their outputs/states as A & B. And thus, we are
required to find the flip-flop input equations for DA and DB.

• Since, the State Equation and Flip-Flop input for a D Flip-

Flops are identical, we can find the FF-input equation
directly from state table using K-Maps.

• For JK & T Flip-Flops, we will require the excitation tables

though.
 93

5.8 Contd. (Step-VI: Synthesis with D-FF)

 94

5.8 Contd. (Step-VII: Logic Diagram)

 95

Excitation Tables

Shortcut for JK Flip-Flop

 96

Synthesis using JK Flip-Flop

• Consider the given state table. To fill in the binary input
combinations for JK Flip-Flop, consult the excitation table.
 97

Synthesis Using JK Flip Flop

 98

Synthesis Using JK Flip-Flop

𝐽𝐴 = 𝐵𝑥′

𝐾𝐴 = 𝐵𝑥

𝐽𝐵 = 𝑥

𝐾𝐵 = (𝐴 + 𝑥)′
 99

Synthesis Using T Flip-Flop

• Example: Design a three bit binary counter using T Flip-Flop.
• A counter is a circuit that starts from a binary combination that
represents decimal 0 and increments the binary combination
on each clock cycle till it reaches 2n-1 and then back to 0.
• Since the clock is not considered an input for flip-flops in
sequential circuit, it looks like that the circuit is functioning
without any input.
• A three bit counter will have seven states, each going into the
next state without any input and the counter doesn’t need any
extra output except the next state itself that represent the
incrementing binary combination. (i.e. until an output is
specified in the problem.)
 100

Synthesis Using T Flip-Flop (State

Diagram)
• The counter’s state will be
the output of the counter.
• And since every next state is
the binary increment of the
previous state, no two states
are going to the same next
state.
• So, there is no chance of
state reduction and we can
even start our state diagram
by assigning the
combinations to the state
first.
• Seven states: Three flip-
flops, Three outptus.
 101

Synthesis Using T Flip-Flop (State Table)

?
 102

Synthesis Using T Flip-Flop (Flip-Flop

inputs)
 103

Synthesis Using T Flip-Flop (Flip-Flop

input equations)
 104

Synthesis Using T Flip-Flop (Logic

Diagram)

𝑇𝐴2 = 𝐴0 𝐴1 𝑇𝐴1 = 𝐴0 𝑇𝐴0 = 1

 105

Official End of Chapter 5