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Full Adder Circuit Design Lab Report

The document outlines a laboratory experiment conducted by B.Sc. Mechatronic Engineering students to design, construct, and test a 1-bit Full Adder using basic logic gates. The experiment includes objectives, apparatus required, theory behind binary addition, and a detailed procedure for implementation, along with an observation table for testing results. The conclusion confirms the successful construction and verification of the full adder circuit, highlighting its significance in arithmetic circuits.

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13 views4 pages

Full Adder Circuit Design Lab Report

The document outlines a laboratory experiment conducted by B.Sc. Mechatronic Engineering students to design, construct, and test a 1-bit Full Adder using basic logic gates. The experiment includes objectives, apparatus required, theory behind binary addition, and a detailed procedure for implementation, along with an observation table for testing results. The conclusion confirms the successful construction and verification of the full adder circuit, highlighting its significance in arithmetic circuits.

Uploaded by

omodiaesther059
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

UNIT: Digital Electronics Laboratory

COURSE: [Link]. Mechatronic Engineering


DATE PERFORMED : 3rd December 2025
DATE SUBMITTED : 10th December 2025

LAB 1 : FULL ADDERS


GROUP MEMBERS
Bicoumarck Maingo​ E022-01-1092/2023
Esther Omodia ​ E022-01-1095/2023
Josephine Karioki ​ E022-01-1096/2023
Antony Mulwa ​ E022-01-1076/2023
Nathaniel Makutsa ​ E022-01-1123/2023
Aim

To design, construct, and test a 1-bit Full Adder using basic logic gates (XOR, AND, OR)
and verify its truth table.

Objectives

●​ To understand binary addition with carry-in and carry-out.


●​ To construct a full adder using discrete digital ICs.
●​ To verify the functional correctness of the circuit through truth-table testing.
●​ To understand how multiple full adders form multi-bit binary adders.

Apparatus Required

●​ Breadboard
●​ 5V DC Power Supply
●​ LEDs (2 pcs)
●​ Resistors (220Ω or 470Ω)
●​ Connecting wires

Digital ICs Used:

●​ 7486 – Quad 2-input XOR gate


●​ 7408 – Quad 2-input AND gate
●​ 7432 – Quad 2-input OR gate​

Theory

Binary Addition

A full adder performs the addition of three input bits:

●​ A – First operand bit


●​ B – Second operand bit
●​ Cin – Carry-in from the previous stage

It produces two outputs:

●​ Sum (S) – Least significant result bit


●​ Carry-out (Cout) – Carry generated to the next stage​

Full Adder Logic


The Boolean expressions are:

S=A⊕B⊕CinS = A \oplus B \oplus CinS=A⊕B⊕Cin Cout=AB+(A⊕B)CinCout = AB + (A


\oplus B)CinCout=AB+(A⊕B)Cin

Gate-Level Implementation Includes:

●​ Two XOR gates


●​ Two AND gates
●​ One OR gate

This forms the standard 1-bit full-adder structure.

Procedure

1.​ Insert the ICs 7486, 7408, and 7432 into the breadboard.
2.​ Connect Vcc = 5V and GND to each IC.
3.​ Make the gate connections according to the full-adder logic diagram.
4.​ Connect input switches or use jumper wires to set inputs A, B, and Cin.
5.​ Use LEDs at outputs Sum and Carry-out with 220Ω resistors.
6.​ Test all eight combinations of inputs.
7.​ Record whether LEDs are ON (logic 1) or OFF (logic 0).​

Observation Table (Truth Table)

A B Cin Sum Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

These results should match the LED outputs.


Discussion

Limitations of a Full Adder

●​ A single full adder only adds one bit; multiple full adders must be cascaded for
multi-bit addition.​

●​ Propagation delay increases as more stages are added (ripple-carry effect).​

●​ Requires more hardware (gates) compared to a half adder.​

Realizing a Full Adder Using Two Half Adders

A full adder can be constructed from:

Two half adders

One OR gate

Process:

1.​ First half adder adds A and B.


2.​ Second half adder adds the intermediate sum to Cin.
3.​ Carry outputs from both stages are OR'ed to produce Cout.

This modular approach reduces design complexity and is widely used in hardware design.

Conclusion

A 1-bit full adder was successfully constructed using XOR, AND, and OR gates.​
The circuit was tested for all input combinations, and the outputs matched the expected truth
table.​
This demonstrates the correct working of the full adder and its importance in building
arithmetic circuits such as multi-bit adders and ALUs.

References

●​ Digital Logic and Computer Design – M. Mano


●​ Datasheets for IC 7486, 7408, 7432

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