MODULE 3

LOW-LEVEL DESIGN ENTRY

• The purpose of design entry is to describe a microelectronic system to a set
of electronic-design automation ( EDA ) tools.
• Design entry for these systems now usually consists of drawing a picture,
a schematic .
• The schematic shows how all the components are connected together,
the connectivity of an ASIC. (schematic entry , or schematic capture)
• A circuit schematic describes an ASIC in the same way an architect’s plan
describes a building.
• The circuit schematic is a picture, an easy format for us to understand and use,
but computers need to work with an ASCII or binary version of the schematic
that we call a netlist .
• Not all the design information may be conveyed in a circuit schematic or netlist,
because not all of the functions of an ASIC are described by the connectivity
information.
• Alternative design-entry methods can use graphical methods, such as a
schematic, or text files, such as a programming language. Using a hardware
description language ( HDL ) for design entry allows us to generate netlists
directly using logic synthesis .
Schematic Entry
• Schematic entry is the most common method of design entry for ASICs and is
likely to be useful in one form or another for some time.
• HDLs are replacing conventional gate-level schematic entry, but new graphical
tools based on schematic entry are now being used to create large amounts of
HDL code.

Terms used in circuit schematics

• Circuit schematics are drawn on schematic sheets .
• Standard schematic sheet sizes are ANSI A–E (more common in the United
States) and ISO A4–A0 (more common in Europe).
• Usually a frame or border is drawn around the schematic containing boxes
that list the name and number of the schematic page, the designer, the
date of the drawing, and a list of any modifications or changes.
• Schematic-entry tools for ASIC design are similar to those for
printed-circuit board (PCB) design.
• The basic object on a PCB schematic is a component or device —a TTL
IC or resistor.
• We can normally draw every component on a few schematic sheets for
a PCB, but drawing every component on an ASIC schematic is
impractical.

IEEE-recommended dimensions and their construction for logic-gate symbols.

(a) NAND gate (b) exclusive-OR gate (an OR gate is a subset).
Hierarchical Design

• Hierarchy reduces the

size and complexity of a
schematic.
The Cell Library
• Designers don’t draw each gate from scratch.
• Instead, they choose components (cells/modules) from a library provided by
the ASIC/FPGA vendor.
• Examples of library elements:
▪ Primitive gates (AND, OR, NAND, NOR, etc.)
▪ Flip-flops, latches, buffers
▪ Larger functional blocks (multipliers, adders, ALUs, memory blocks)
Schematic Library Problems
• No Naming Conventions
• Different vendors use different names for the same cell.
• Example:
• A 2-input NAND gate in Xilinx FPGA library may be named NAND2.
• In LSI Logic gate-array library, it might be ND2 or something else.
• This inconsistency makes porting designs (moving from one
technology/vendor to another) difficult.
• No Standards for Cell Behavior
• The same cell type may behave differently across vendors.
• Example: A D flip-flop in one library may have:
• Asynchronous reset (active-low)
• While another library’s D flip-flop may have:
• Synchronous reset (active-high).
• This difference means the same schematic may not work correctly if
moved to another ASIC/FPGA platform without modifications
• Because of inconsistent naming and different behavior,
schematic-based designs are hard to port.
• This is one big reason why HDLs (Verilog/VHDL) became more popular
→ they are standardized and portable
• There are two types of macros for MGAs and programmable ASICs.
• The most common type of macro is a hard macro that includes
placement information.
• A hard macro can change in position and orientation, but the relative
location of the transistors, other layout, and wiring inside the macro is
fixed.
• A soft macro contains only connection information (between
transistors for a gate array or between logic cells for a programmable
ASIC).
• Thus the placement and wiring for a soft macro can vary. This means
that the timing parameters for a soft macro can only be determined
after you complete the place-and-route step.
• A standard cell contains layout information on all mask levels.
• An MGA hard macro contains layout information on just the metal,
contact, and via layers.
Names
Cells, Instances, and Symbols in ASIC Schematics
• Cell Name
• Every cell (primitive or complex) has a unique name in the library.
• Example: NAND2 (2-input NAND gate), DFF (D flip-flop), HADD (half-adder).
• Instance Name
• Each use of a cell in a schematic is called an instance.
• Every instance gets its own unique name, even if it comes from the same cell.
• Example: If we use the NAND2 cell three times, the instances might be named
u1, u2, u3.
• Cell Instance = Between Copy and Reference
• A cell instance is not a full copy of the library cell (because it doesn’t duplicate
the definition).
• It is also not just a reference (because it has unique connections/parameters).
• Analogy: Like the picture of a hamburger in a fast-food restaurant → it’s not a
real hamburger, but not just text either.
Symbols (Icons)
• Each cell instance is represented by a symbol/icon on the schematic.
• Two main styles:
• Familiar gate shapes (NAND, NOR, XOR drawn like shovels/spades).
• Rectangular IEEE standard symbols (official standard but less
visually intuitive).
Problem in Schematics
• No standard way to differentiate:
• Primitive cell (like NAND gate)
• Subschematic cell (like a half-adder made of NANDs/OR/INV).
• On a schematic, both look the same (both are just icons).
• Result: You often can’t tell at a glance whether an icon is a basic gate
or a block made of many gates
Schematic Icons and Symbols
• Most schematic-entry programs allow the designer to draw special or
custom icons.
• In addition, the schematic-entry tool will also usually create an icon
automatically for a subschematic that is used in a higher-level
schematic.
Nets
Local nets vs. External nets
• Local nets: Exist inside a cell (internal connections).
Example: n1 in Figure 9.4(b), which connects and1 output to or1 input.
• External nets: Connect a cell to higher-level circuitry (the parent
schematic).
Example: inputs (D), enable (EN), and outputs (Q) in the DLAT cell.
• Problem of net naming
• When the FourBit cell (Figure 9.5(d)) is created using four DLAT instances:
• Each DLAT has its own local net called n1.
• Even though they share the same name (n1), they are different physical nets and
not electrically connected.
• To avoid confusion, unique names must be assigned.
Convention for hierarchical net naming
• The parent cell instance name is used as a prefix to the local net.
• A special delimiter (e.g., : or /) separates the two.
Example (Figure 9.5(b)):
• Four DLAT instances: L1, L2, L3, L4.
• Each has its own n1.
• These become:
• FourBit.L1:n1
• FourBit.L2:n1
• FourBit.L3:n1
• FourBit.L4:n1
• This ensures unique identification of each net.
Automatic naming
• Modern schematic-entry tools automatically generate these hierarchical names.
• Designers don’t usually need to manually rename.
External nets in DLAT
• DLAT has three external nets: D, EN, Q.
• When DLAT is instantiated inside another schematic, these nets get
connected to the parent circuit nets.
• Example: A signal Trigger:flag in Figure 9.4(c) is also referred to as
[Link]:Q.
HDLs (VHDL/Verilog)
• Unlike schematic tools, HDLs have strict, well-defined naming rules for
hierarchical nets.
• This makes simulation and debugging easier because signal references
are always unique and traceable.
Schematic Entry for ASICs and PCBs
• A symbol on a schematic may represent a component, which may
contain component parts.
• A component is slightly different from an ASIC library cell.
• A simple example of a component would be a TTL gate, an SN74LS00N, that
contains four 2-input NAND gates. We call an SN74LS00N a component and
each of the individual NAND gates inside is a component part.
• Another common example of a component would be a resistor pack—a
single package that contains several identical resistors.
• In PCB design language a component label or name is a reference
designator .
• A reference designator is a unique name attribute, such as R99 , attached to
each component. A reference designator, such as R99 , has two pieces: an
alpha prefix R and a numerical suffix 99 . To understand the difference
between reference designators and instance names, we need to look at the
special requirements of PCB design.
• PCBs usually contain packaged ASICs and other ICs that have pins that are
soldered to a board.
• For rectangular, dual-in-line (DIP) packages the pins are numbered
counterclockwise from the upper-left corner looking down on the package.
• IC symbols have a pin number for each part in the package.
• The number of wire crossings on a PCB is minimized by careful assignment of
components to packages and choice of parts within a package.
• There is no process in ASIC design directly equivalent to the process of part
assignment described above and thus no need to use reference designators.
• The reference-designator naming convention quickly becomes unwieldy if
there are a large number of components in a design.
• In large hierarchical ASIC designs it is difficult to provide a unique reference
designator to each element.
• For this reason ASIC designs use instance names to identify the individual
components. Meaningful name can be assigned to low-level components.
Connections
• Cell instances have terminals that are the inputs and outputs of the cell.
Terminals are also known as pins , connectors , or signals .
• Electrical connections between cell instances use wire segments or nets .
• In ASIC design: Terminal refers to logical connections . Pin is used for the
physical metal lead in a package.
• Using buses reduces complexity and mistakes in schematics.
Figure (a):
• It appears to represent a 4-input AND gate
configuration, where:
• Two sets of inputs:
• D[1], D[2] (probably for data lines)
• E[1], E[2] (enable lines)
• Three AND gates, producing outputs
labeled C, B, and A.
• The AND gates seem to be performing bit-wise
AND operations on these two input buses.
Figure (b):
• This looks like an expanded version using a
"bus ripper" for a cleaner representation.
• The bus ripper splits the bus into individual bits
(D0 to D7) and connects them to AND gates
producing the outputs C, B, and A.
• This is typically used for logic simplification in
schematics, especially when working with wide
buses
Vectored Instances and Buses
• The buses are labeled with the appropriate bits.
Edit-in-Place
• Using edit-in-place we can edit the cell Floor .
• Suppose we change some of the cell instances of cell name No Window
Office to instances of cell name Window Office .
• When we finish editing and save the cell Floor , we have effectively changed
all of the floors that contain instances of this cell.
• Instead of editing a cell in place, you may really want to edit just one
instance of a cell and leave any other instances unchanged.
• In this case you must create a new cell with a new symbol and new, unique
cell name.
• It might also be wise to change the instance name of the new cell to avoid
any confusion.
Attributes
Name (Identifier / Label):
• Attached to a component, cell instance, net, terminal, or
connector.
• Example: U1, clk, D[0].
Attribute (Property):
• Describes some aspect of the component or connection.
• Has a name and may have a value.
• Example:
•width = 16
•delay = 2ns
•cell_type = NAND2.
Common Naming Problems:
• Case sensitivity (e.g., clk vs CLK).
• Name collisions (duplicate names).
• Special characters:
•Embedded blanks, underscores, foreign alphabets.
• First character restrictions (cannot start with a digit in many
tools).
• Name length restrictions (e.g., 28 characters max for NFS).
Impact:
• Inconsistent naming leads to tool interoperability problems.
• Errors when exchanging schematics/netlists between different
EDA tools.
Netlist Screener
• A surprising number of problems can be found by checking a schematic for
obviously fatal errors.
• A program that analyzes a schematic netlist for simple errors is sometimes
called a schematic screener or netlist screener .
• Errors that can be found by a netlist screener include:
1. unconnected cell inputs,
2. unconnected cell outputs,
3. nets not driven by any cells,
4. too many nets driven by one cell,
5. nets driven by more than one cell.
• The screener can work continuously as the designer is creating the schematic
or can be run as a separate program independently from schematic entry.
• Usually the designer provides attributes that give the screener the information
necessary to perform the checks.
• A screener usually generates a list of errors together with the locations of
the problem on the schematic where appropriate.
• Some editors associate an identifier, or handle , to every piece of a
schematic, including comments and every net.
• Normally there is some convention to the assigned names such as a grid
on a schematic.
• This works like the locator codes on a map, so that a net with A1 as part of
the name is in the upper-left-hand corner,
• for example. This allows you to quickly and uniquely find any problems
found by a screener.
• The term handle is a computer programming term that is used in referring
to a location in memory.
• Each piece of information on a schematic is stored in lists in memory. This
technique breaks down completely when we move to HDLs.
ASIC CONSTRUCTION
• The physical design of ASICs is normally divided into system
partitioning, floorplanning, placement, and routing.
• A microelectronic system is the town and the ASICs are the buildings.
System partitioning corresponds to town planning, ASIC floorplanning
is the architect’s job, placement is done by the builder, and the
routing is done by the electrician.
• We shall design most, but not all, ASICs using these design steps.
Physical Design
CAD Tools
• In order to develop a CAD tool it is necessary to convert each of the physical
design steps to a problem with well-defined goals and objectives.
• The goals for each physical design step are the things we must achieve.
• The objectives for each step are things we would like to meet on the way to
achieving the goals.
• Some examples of goals and objectives for each of the ASIC physical design
steps are as follows:
1. System partitioning:
Goal: Partition a system into a number of ASICs.
Objectives: Minimize the number of external connections between the ASICs. Keep
each ASIC smaller than a maximum size.
2. Floor planning:
Goal: Calculate the sizes of all the blocks and assign them locations.
Objective: Keep the highly connected blocks physically close to each other.
3. Placement:
Goal: Assign the interconnect areas and the location of all the logic cells within
the flexible blocks.
Objectives: Minimize the ASIC area and the interconnect density.
4. Global routing:
Goal: Determine the location of all the interconnect.
Objective: Minimize the total interconnect area used.
5. Detailed routing:
Goal: Completely route all the interconnect on the chip.
Objective: Minimize the total interconnect length used.
This image illustrates the relationship between a network and a graph in the
context of electronic circuits or logic modules.
(a) shows a network with modules or blocks (A, B, C, D, E, F) connected by
nets, signals, or wires, and terminals or pins on these modules.
(b) translates the network into a graph where each module/block becomes a
vertex (or node), and each wire or net becomes an edge connecting the
vertices.
(c) shows a net cut in the network, splitting the network into two parts,
highlighting how multiple modules can be connected by a single wire.
(d) shows the corresponding edge cut in the graph, splitting the graph into
subgraphs by cutting edges, and indicates that a single wire can be modeled
by multiple edges in the network graph
A Simple Partitioning Example
Goal of the Example:
Partition a network of 12 logic
cells (A–L) connected by 12
nets (1–12) into 3 ASICs,
satisfying:
Objectives:
1. Use no more than 3 ASICs.
2. Each ASIC can have no
more than 4 logic cells.
3. Minimize the number of
external connections per
ASIC.
4. Minimize the total number
of external connections
(i.e., net cuts).
 Example:
Suppose your current partition contains logic cells A,B, and C and you
want to evaluate cell D:
•If D shares 3 nets with cells in the partition A,B,C, then g(D)=3.
•If another cell E shares only 1 net with cells in the partition, then
g(E)=1.
•So you'd pick D over E because D has a higher gain.
g(m)=Number of connections (nets) between logic cell m and the
current partition
 Constructive Partitioning
Constructive partitioning algorithms typically use seed growth or cluster growth
methods. The main idea is to start with a small portion (seed) of the network and grow
it by adding logic cells, based on some gain or benefit function, until certain constraints
are met.
Simple Seed-Growth Algorithm Steps:
[Link] a new partition by choosing a seed logic cell.
[Link] all logic cells not yet in a partition, selecting each in turn.
[Link] a gain function g(m), which measures the benefit of adding logic cell m to the
current partition. A common measure of gain is how many connections exist between
logic cell m and the current partition.
[Link] the logic cell with the highest gain g(m) to the partition.
[Link] from step 2 until the partition size limit is reached, then start a new partition.
Additional Notes:
•The choice of the seed logic cell is important; the cell with the most nets (connections)
is often a good starting point.
Iterative Partitioning Improvement, focusing on two main approaches: interchange
(swapping) and group migration.
Summary:
1. Interchange (Swapping) Method
Goal: Improve a partition by swapping logic cells between partitions.
Process:
Swap two cells and check if the partition improves (fewer external connections).
If improved, accept the swap; if not, reject it and try a different swap.
Limitation:
Only considers one swap at a time (simple interchange).
Can get stuck in a local minimum where no single swap improves the partition even though
better partitions exist.
Example given: To move from one partitioning solution to an optimal one may require
swapping multiple pairs of cells simultaneously, which is computationally expensive.
2. Group Migration
Swaps groups of logic cells between partitions instead of just individual cells.
More effective than simple interchange but also more complex.
Most group migration algorithms are based on the Kernighan-Lin (KL) algorithm.
Step 0: Initial Setup Step 1: Compute D values
We have 6 nodes: For each node:
Nodes: {1, 2, 3, 4, 5, 6} •D=external cost−internal cost
We divide them into two Partition A
partitions: Node External Internal D
•Partition A: {1, 2, 3} 1 to 4, 5 → 2 to 2 → 1 2 − 1 = +1
•Partition B: {4, 5, 6} 2 to 5, 6 → 2 to 1 → 1 2 − 1 = +1
🔗 Connections (Edges): 3 to 4, 6 → 2 none 2 − 0 = +2
Edge Weight Partition B
1—4 1 Node External Internal D
1—5 1 4 to 1, 3 → 2 to 5 → 1 2 − 1 = +1
2—5 1 5 to 1, 2 → 2 to 4 → 1 2 − 1 = +1
2—6 1 6 to 2, 3 → 2 none 2 − 0 = +2
3—4 1
3—6 1
1—2 1
4—5 1
Step 2: Try all pairwise swaps and
compute gain 3. Swap (1, 6):

Gain formula: ∙ D1=1, D6=2, c1,6=0

gi=Dai+Dbi−2caibi ∙ Gain: 1+2−2×0=3

Try every pair (A node, B node): 4. Swap (2, 4):Gain: 1+1−0=2

1. Swap (1, 4): 5. Swap (2, 5):Gain: 1+1−2×1=0

∙ D1=1, D4=1, c1,4=1 6. Swap (2, 6):Gain: 1+2−2×1=1

∙ Gain: 1+1−2×1=0 7. Swap (3, 4):Gain: 2+1−2×1=1

2. Swap (1, 5): 8. Swap (3, 5):Gain: 2+1−0=3

∙ D1=1, D5=1, c1,5=1 9. Swap (3, 6):Gain: 2+2−2×1=2

∙ Gain: 1+1−2×1=0
Step 3: Select best pair to swap first
The highest gain = 3, for:
(1, 6)
(3, 5)
Let’s pick (1, 6) first.
Now mark 1 and 6 as swapped.
Step 4: Repeat with remaining nodes
Remaining:
A: {2, 3}
B: {4, 5}
Repeat D calculation and gain computation excluding swapped nodes.
Keep doing this until all nodes are marked (pretend-swapped). Record each swap and
gain.
Step 5: Track total gain Gn
Suppose after 3 rounds of pretend swaps, we have gains:
Swap 1 (1, 6): +3
Swap 2 (2, 4): +2
Swap 3 (3, 5): +3
Cumulative gains:
G1=3
G2=3+2=5
G3=5+3=8
So, we swap all 3 pairs.
Final Result
Before:
A: {1, 2, 3}
B: {4, 5, 6}
After:
A: {4, 5, 6}
B: {1, 2, 3}
Cut size is reduced by total gain = 8, meaning 8 fewer external edges
Ratio-Cut Algorithm Explanation
∙ The goal is to partition a network into two parts A and B such that the cut weight W (sum
of weights of edges between A and B) is minimized.
∙ Unlike the Kernighan-Lin algorithm, the ratio-cut algorithm removes the restriction that
partitions have to be the same size.
∙ The ratio of a cut is defined as:
R = W
∣A∣×∣B∣
Where:
∙ W = total weight of edges crossing between partitions A and B.
∙ ∣A∣, ∣B∣ = the sizes (number of nodes) in partitions A and B.
The objective is to minimize R, meaning the cut weight relative to the product of the
partition sizes is minimized. This tends to produce balanced partitions that also minimize
connections between them
Simple Example
Suppose you have a network graph with 6 nodes and the following edges (all with equal
weight 1):Edges: (1-2), (1-3), (2-4), (3-5), (4-6), (5-6)You want to partition nodes into sets A
and B:
Partition 1:
Partition 2:
• A={1,2,3}
• B={4,5,6} A={1,2,3,4}
Cut edges (edges between A and B): B={5,6}
• (2-4) Cut edges:
• (3-5) (3-5)
So, cut weight W=2 (4-6)
Sizes: Cut weight W=2
∣A∣=3 Sizes:
∣B∣=3 ∣A∣=4
Ratio cut: ∣B∣=2
R= W Ratio cut:
∣A∣×∣B∣
R= 2
= 2
3×3 4×2
≈0.222 =0.25
 The example network is split into two partitions A
Look-ahead Algorithm and B, with nodes labeled 1 to 10.
First Sequence (Partitions a, b, c):
(a) Initial partitioning, moving node 2 from A to B
gains +1.
(b) After moving node 2, move node 3 from A to B,
again gain +1.
(c) New partition with nodes 2 and 3 moved to B.
Result: Total gain = 2 (sum of gains +1 and +1).

Second Sequence (Partitions d, e, f):

(d) Same initial partitioning as (a).
(e) Move node 5 from A to B, gain +1.
Then move node 4 from A to B, gain +2 (higher
gain because of earlier move).
(f) Resulting partition after moving nodes 5 and 4.
Result: Total gain = 3 (sum of gains +1 and +2).

Hence Look-ahead considers second-level and higher gains to choose moves that lead
to better partition