EE203 Semiconductor Devices

MOS Cap → MOSFET

Effect of Third Terminal

 Important equations so far:

𝑛𝑜 = 𝑛𝑖 𝑒 −𝑞𝜙𝐹 /𝑘𝑇 𝑝𝑜 = 𝑛𝑖 𝑒 𝑞𝜙𝐹 /𝑘𝑇 𝑛𝑠 = 𝑛𝑜 𝑒 𝑞𝜓𝑠/𝑘𝑇 = 𝑛𝑖 𝑒 𝑞(𝜓𝑠 −𝜙𝐹 )/𝑘𝑇 ≈ 𝑁𝐴 𝑒 𝑞(𝜓𝑠 −2𝜙𝐹 )/𝑘𝑇

𝐸𝑖,𝑏𝑢𝑙𝑘 − 𝐸𝑖,𝑠𝑢𝑟𝑓𝑎𝑐𝑒 Δ𝑉𝐺𝐵 = Δ𝜓𝑠 + Δ𝜓𝑜𝑥

𝜓𝑠 ≡
𝑞
∆𝑄𝐺′ ∆𝑄𝐶
′
𝐶𝐺′ = 𝐶𝑐′ ≜ −
1/2 ∆𝑉𝐺𝐵 ∆𝜓𝑠
2𝜖𝑠 𝜓𝑠
𝑉𝐺𝐵 = 𝑉𝐹𝐵 + 𝑉𝑜𝑥 + 𝑉𝑠𝑒𝑚 𝑊𝑑 =
𝑞𝑁𝐴
1 1 1
𝑄𝐶′ = +
𝐶𝐺′ 𝐶𝑜𝑥
′
𝐶𝑐′
𝑉𝐺𝐵 = 𝜙𝑚𝑠 − ′ + 𝜓𝑠 𝑉𝐺 = 𝑉𝐹𝐵 + 𝜓𝑠 + 𝛾 𝜓𝑠
𝐶𝑜𝑥
𝜖𝑠 𝜖𝑠
(assuming no oxide charges) 𝐶𝑑′ = ′
𝐶𝑑|𝐹𝐵 =
𝑊𝑑 𝐿𝐷
𝑄𝐶′ = 𝑄𝐵′ + 𝑄𝐼′ 𝑄𝐵′ ≈ − 2𝜖𝑠 𝑞𝑁𝐴 𝜓𝑠 𝑄𝐼′ ≈ −𝐶𝑜𝑥
′ (𝑉
𝐺𝐵 − 𝑉𝑇 )
𝐶𝑑′ 𝐶𝑐′
∆𝑉𝐺𝐵
2𝜖𝑠 𝑞𝑁𝐴 ′
𝐶𝑜𝑥 𝐶𝐼′
𝑉𝑇 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 𝛾≜ ′
𝐶𝑜𝑥
 𝐶𝐺′

′
𝐶𝑜𝑥

𝑉𝐺𝐵
𝑉𝐹𝐵 𝑉𝑇
 Class Exercise
Draw the low- and high-frequency 𝐶 − 𝑉 characteristics at room temperature, clearly showing all the relevant
details, for a two-terminal MOS structure having 30 nm thick oxide and a Si substrate with acceptor doping of
1015 cm−3 . Assume the following: 𝑉𝐹𝐵 = −0. 2 V, 𝐶𝐼′ is neglected in weak inversion region, minimum capacitance
point is at 𝑉𝑇 and that the change in 𝜓𝑠 is negligible for voltages higher than 𝑉𝑇 .

′
𝜖𝑜𝑥 3.9 × 8.854 × 10−14 −7 F. cm−2
𝐶𝑜𝑥 = = = 1.15 × 10
𝑡𝑜𝑥 30 × 10−7
𝐶𝐺′
1/2 1/2 ′
2𝜖𝑠 𝜓𝑠 2𝜖𝑠 2𝜙𝐹 𝐶𝑜𝑥
𝑊𝑑 = At threshold, 𝜓𝑠 = 2𝜙𝐹 𝑊𝑑,𝑚𝑎𝑥 =
𝑞𝑁𝐴 𝑞𝑁𝐴

𝑁𝐴 1015
𝜙𝐹 = 𝑘𝑇ln = 0.026 × ln = 0.29 V 𝑉𝐹𝐵 𝑉𝑇 𝑉𝐺𝐵
𝑛𝑖 1.5 × 1010

2 × 11.7 × 8.854 × 10−14 × 0.58 −5 cm

∴ 𝑊𝑑,𝑚𝑎𝑥 = = 8.67 × 10
1.6 × 10−19 × 1015
 ′
𝐶𝑜𝑥 = 1.15 × 10−7 F. cm−2 𝜙𝐹 = 0.29 V 𝑉𝐹𝐵 = −0.2 V 𝑊𝑑,𝑚𝑎𝑥 = 8.67 × 10−5 cm

′ 𝜖𝑆 11.7 × 8.854 × 10−14

𝐶𝑑,𝑚𝑖𝑛 = = −5 = 1.19 × 10−8 F. cm−2
𝑊𝑑,𝑚𝑎𝑥 8.67 × 10
−1
′ ′ ′ 1 1
𝐶𝐺,𝑚𝑖𝑛 = 𝐶𝑜𝑥 series 𝐶𝑑,𝑚𝑖𝑛 = + = 1.08 × 10−8 F. cm−2
1.15 × 10−7 1.19 × 10−8

𝐶𝐺′
′ 𝜖𝑠 𝜖𝑆 𝑘𝑇 11.7 × 8.854 × 10−14 × 0.026
𝐶𝑑|𝐹𝐵 = 𝐿𝐷 = = −19 15 = 1.3 × 10−5 cm ′
𝐶𝑜𝑥
𝐿𝐷 𝑞𝑁𝐴 1.6 × 10 × 10

′ 11.7 × 8.854 × 10−14

𝐶𝑑|𝐹𝐵 = −5
= 8 × 10−8 F. cm−2
1.3 × 10
−1
𝑉𝐹𝐵 𝑉𝑇 𝑉𝐺𝐵
1 1
′
𝐶𝐺,𝐹𝐵 = ′
𝐶𝑜𝑥 series ′
𝐶𝑑,𝐹𝐵 = + = 4.72 × 10−8 F. cm−2
1.15 × 10−7 8 × 10−8

2𝜖𝑠 𝑞𝑁𝐴
𝑉𝑇 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 𝛾≜ ′ 𝑉𝑇 = −0.2 + 0.58 + 𝛾 0.58 = 0.5 V
𝐶𝑜𝑥
 𝐶𝐺′ (F. cm−2 )

1.15 × 10−7
′
𝐶𝑜𝑥
Low Frequency
4.72 × 10−8
1.08 × 10−8
High Frequency

𝑉𝐺𝐵 (V)
−0.2 0.5
𝑉𝑇 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 Ex.,: 𝑉𝐹𝐵 = 0.18 V, 2𝜙𝐹 = 0.7 V, 𝛾 = 0.15 V1/2 ⇒ 𝑉𝑇 = 1.0 V

1.0 1.0
0
− − − − − − − − 𝑛𝑠 = 𝑁𝐴 𝑛+ −−−−−−−−

P-type P-type

𝑛𝑠 = 𝑁𝐴 ?

0
−−−−−−−− 𝑛+ −−−−−−−−

P-type P-type
−1.0 −1.0
 𝑉𝐺𝐵 𝑛𝑠 = 𝑛𝑖 𝑒 (𝐸𝐹𝑛𝑠 −𝐸𝑖𝑠)/𝑘𝑇

𝑛𝑠 = 𝑛𝑖 𝑒 (𝐸𝐹𝑛𝑠 +𝐸𝐹𝑛𝐵−𝐸𝐹𝑛𝐵+𝐸𝑖𝐵−𝐸𝑖𝐵−𝐸𝑖𝑠)/𝑘𝑇
−−−−−− −−
𝑛𝑠 = 𝑛𝑖 𝑒 (𝐸𝐹𝑛𝐵 −𝐸𝑖𝐵)/𝑘𝑇 𝑒 (𝐸𝑖𝐵−𝐸𝑖𝑠 )/𝑘𝑇 𝑒 (𝐸𝐹𝑛𝑠 −𝐸𝐹𝑛𝐵)/𝑘𝑇
P-type 𝑛𝑖2 𝑞𝜓 /𝑘𝑇 (𝐸 −𝐸 )/𝑘𝑇
𝑛𝑠 = 𝑒 𝑠𝐵 𝑒 𝐹𝑛𝑠 𝐹𝑛𝐵 = 𝑁𝐴 at threshold
𝑁𝐴

𝑘𝑇 𝑁𝐴
⇒ 𝜓𝑠𝐵|𝑇 = 2 ln − (𝐸𝐹𝑛𝑠 − 𝐸𝐹𝑛𝐵 )/𝑞
𝑉𝐺𝐵 𝑞 𝑛𝑖
𝑉𝐶𝐵

+
𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + (𝐸𝐹𝑛𝐵 − 𝐸𝐹𝑛𝑠 )/𝑞 𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + (𝐸𝐹𝑛𝐵 − 𝐸𝐹𝑛𝐶 )/𝑞
𝑛
𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐶𝐵
P-type
𝑉𝐺𝐵 = 𝑉𝐹𝐵 + 𝜓𝑠𝐵 + 𝛾 𝜓𝑠𝐵 𝑉𝑇 = 𝑉𝐹𝐵 + (2𝜙𝐹 + 𝑉𝐶𝐵 ) + 𝛾 (2𝜙𝐹 + 𝑉𝐶𝐵 )

What determines the quasi-Fermi level at the surface in strong inversion?

 1.0 0.8 1.0 1.0
0
𝑛+ − − − − − − 𝑛−+− − −−−−−−−−−−
−−−
−−−
−−−− − − −

P-type P-type P-type

0
𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + (𝐸𝐹𝑛𝐵 − 𝐸𝐹𝑛𝐶 )/𝑞
𝑛+
−−−−−−−−
𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐶𝐵

−1.0 𝑉𝐺𝐵|𝑇 = 𝑉𝑇 = 𝑉𝐹𝐵 + (2𝜙𝐹 + 𝑉𝐶𝐵 ) + 𝛾 (2𝜙𝐹 + 𝑉𝐶𝐵 )

 What is the effect of the wire connection on the internal potential?

𝑉𝐺𝐵 𝑉𝐺𝐵

𝑛+ 𝑛+

P-type P-type
 𝑛+ 𝑛+
+ 𝑉𝑏𝑖 𝑑 + 𝑉𝑏𝑖
𝑉𝐹𝐵 𝑉𝐹𝐵
− −
P P

Almost the entire depletion region width (𝑑) of the N+P junction will be inside P-region.

Apply a gate voltage such that the surface is at flat band.

Assume that the gate is long and wide – much longer than 𝑑.
 P
𝐸𝑖

𝐸𝑉
𝑛+

𝑉𝑏𝑖

−
+

𝑉𝐹𝐵
 0
𝑛+
+ 𝑉𝑏𝑖
𝑉𝐹𝐵
− 𝑦
P

𝐸𝑉

𝐸𝑖
𝐸𝐶
𝑞𝑉𝑏𝑖 No 𝑒 − s at the surface
Built-in potential barrier for 𝑒 − s from 𝑛+ region
𝐸𝑉

At the surface
Along 𝑥 - direction
 𝐸𝐶
−−−−−−−− − 𝑞𝑉𝑏𝑖 𝑞𝜓𝑠
𝑛+
+ 𝑉𝑏𝑖
𝑉𝐺𝐵1 𝐸𝑉
−
P

Apply gate voltage such that the surface is inverted i.e.,

surface will be more positive than bulk. Let the surface
potential be 𝑞𝜓𝑠 . The 𝑒 − s energy at the surface will be
lower than that in the bulk by an amount of 𝜓𝑠 .

Effectively, the barrier for 𝑒 − s to go into the channel is lowered in strong inversion.
⇒ they can easily go into the channel if the barrier is low enough. ∝ 𝑒 𝜓𝑠 /𝑘𝑇
Surface 𝑒 − s can now come from 𝑛+ region as well – much easier than for them to
come from the bulk. Thus, the imref of 𝑒 − s is determined by the 𝑛+ region.
 − − − − −
𝑛+ Reverse bias the 𝑛+ 𝑝 junction by applying 𝑉𝐶𝐵
+ + 𝑉𝐶𝐵 𝑑1
𝑉𝐺𝐵1 ✓ Depletion region will be wider (𝑑1 > 𝑑)
− −
P ✓ Energy band of 𝑛+ region shifts down by 𝑞𝑉𝐶𝐵

✓ Lesser no. of 𝑒 − s can cross the barrier

𝐸𝐶 ⇒ Channel will have fewer 𝑒 − s than before
𝑞𝜓𝑠1

𝑞𝑉𝐶𝐵 𝑞(𝜓𝑠1 + 𝑉𝐶𝐵 ) • Restore the channel 𝑒 − s to previous value ?

⇒ Increase 𝜓𝑠 by an amount equal to 𝑉𝐶𝐵 i.e., at the

surface, an extra band bending of 𝑞𝑉𝐶𝐵 .

−− −− −− −− − This can be done by increasing 𝑉𝐺𝐵 .

𝑛+
𝑉𝐺𝐵2 + + 𝑉 Key point to remember: Surface potential w.r.t. body, and
𝐶𝐵
− − hence the gate-body voltage, is competing against 𝑉𝐶𝐵 in
> 𝑉𝐺𝐵1
P maintaining the inversion charge at any particular level.
 G 𝑉𝐺𝐶 + G
− C
C
−− −− −− −− − −− −− −− −− −
𝑛+ 𝑛+

𝑉𝐺𝐵 + + 𝑉 𝑉𝐶𝐵 +
𝐶𝐵
− − −
P P

B B

Voltages with reference to body terminal Voltages with reference to C terminal

𝑄𝐼′ =−𝐶𝑜𝑥
′
𝑉𝐺𝐵 − 𝑉𝑇𝐵 𝑉𝐺𝐶 = 𝑉𝐺𝐵 − 𝑉𝐶𝐵 or 𝑉𝐺𝐵 = 𝑉𝐺𝐶 + 𝑉𝐶𝐵

𝑉𝑇𝐵 = 𝑉𝑇ℎ𝐶 + 𝑉𝐶𝐵

𝑉𝑇𝐵 = 𝑉𝐹𝐵 + (2𝜙𝐹 +𝑉𝐶𝐵 ) + 𝛾 2𝜙𝐹 + 𝑉𝐶𝐵
𝑄𝐼′ =−𝐶𝑜𝑥
′ 𝑉 + 𝑉 − (𝑉 + 𝑉 )
𝐺𝐶 𝐶𝐵 𝑇𝐶 𝐶𝐵
𝑉𝑇0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹
𝑄𝐼′ =−𝐶𝑜𝑥
′ 𝑉 −𝑉
𝐺𝐶 𝑇𝐶

𝑉𝑇𝐵 − 𝑉𝐶𝐵 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) + 𝛾 2𝜙𝐹 − 𝛾 2𝜙𝐹 𝑉𝑇𝐶 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) − 2𝜙𝐹
Body Effect 𝑉𝐶𝐵 ↑ ⇒ 𝑄𝐼′ ↓ for a fixed 𝑉𝐺𝐶

𝑉𝐺𝐶 + G
− C
• Assume the device to be in S.I. i.e., large 𝑉𝐺𝐶 −− −− −− −− −
𝑛+ − − − − − − − − −
• Fixed 𝑉𝐺𝐶 ⇒ Gate charge (+ve) remains constant
𝑉𝐶𝐵 +
• S.I. layer is like the bottom plate of capacitor −
• Surface is like an extended 𝑛+ 𝑝 junction: field-induced P
• 𝑉𝐶𝐵 ↑ ⇒ Effective reverse bias 𝑛+ 𝑝 junction ↑ B
• ⇒ Depletion region widens
• ⇒ More acceptor ions get uncovered ⇒ 𝑄𝐵′ ↑
𝐸𝐶
• For charge balance: Fewer inversion charges
• Restoring to original inversion level ⇒ 𝑄𝐼′ ↑ ⇒ 𝑉𝐺𝐶 ↑
𝑉𝑇𝐶 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) − 2𝜙𝐹
• 𝑁𝐴 ↑, larger the change in 𝑄𝐵′ ⇒ larger 𝑉𝐺𝐶 change required
• Thus, body effect is more pronounced for heavy doping 2𝑞𝜖𝑠 𝑁𝐴
𝛾≡ ′
• Also for thicker oxide (since larger gate voltage is needed) 𝐶𝑜𝑥
 Pinch-off
𝑄𝐼′

In strong inversion region

𝑄𝐼′ ≈ −𝐶𝑜𝑥
′ 𝑉
𝐺𝐵 − 𝑉𝑇𝐵

𝑉𝑇𝐵 = 𝑉𝐹𝐵 + (2𝜙𝐹 +𝑉𝐶𝐵 ) + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 )

𝑄𝐼′ = −𝐶𝑜𝑥
′ 𝑉𝐺𝐵 − (𝑉𝐹𝐵 + (2𝜙𝐹 +𝑉𝐶𝐵 ) + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) )
𝑉𝐶𝐵
𝑉𝑃
Increase 𝑉𝐶𝐵 ⇒ 𝑉𝑇𝐵 increases

2
At some value of 𝑉𝐶𝐵
, 𝑉𝑇𝐵 = 𝑉𝐺𝐵 ⇒ 𝑄𝐼′ ≈ 0
𝛾 𝛾2
𝑉𝑃 = − + + 𝑉𝐺𝐵 − 𝑉𝐹𝐵 − 2𝜙𝐹
This is known as pinch off voltage 𝑉𝑃 2 4
 𝑄𝐼′
However, the inversion charge is not zero at this point.

At low values of inversion charge, the device is NOT in

strong inversion.

Hence, the strong inversion equation is not valid.

Exact expression for inversion charge should be used.

A small amount of charge will be present at the surface.

It will be in weak inversion region.

𝑉𝐶𝐵
𝑉𝑃
S.I.
EE203 Semiconductor Devices

MOSFET - 2

Level – 0 Model
 G G G
1.0 C C1 C2

−−−−−− −− 𝑛+ 𝑛+ 𝑛+

P-type P-type P-type

B B B

𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐶1𝐵 𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐶2𝐵

𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + (𝐸𝐹𝑛𝐵 − 𝐸𝐹𝑛𝐶 )/𝑞 𝑄𝐼′ =−𝐶𝑜𝑥

′ 𝑉
𝐺𝐵 − 𝑉𝑇𝐵 𝑄𝐼′ =−𝐶𝑜𝑥
′ 𝑉 −𝑉
𝐺𝐶 𝑇𝐶

𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐶𝐵 𝑉𝑇0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹

𝑉𝐺𝐵|𝑇 = 𝑉𝑇𝐵 = 𝑉𝐹𝐵 + (2𝜙𝐹 + 𝑉𝐶𝐵 ) + 𝛾 (2𝜙𝐹 + 𝑉𝐶𝐵 )

𝑉𝑇𝐶 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) − 2𝜙𝐹
𝑉𝑇𝐶 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 ) − 2𝜙𝐹 𝑉𝑇0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹
G
𝑄𝐼′ =−𝐶𝑜𝑥
′
𝑉𝐺𝐶 − 𝑉𝑇𝐶
S D
′ ′ ′ ′ 𝑉
𝑄𝐼|𝑆 =−𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑆 𝑄𝐼|𝐷 =−𝐶𝑜𝑥 𝐺𝐷 − 𝑉𝑇𝐷 𝑛+ 𝑛+
′ ′
𝑄𝐼|𝐷 =−𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝐷𝑆 − 𝑉𝑇𝐷
P-type

𝑉𝑇𝑆 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 ) − 2𝜙𝐹 B

𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝑆𝐵 𝜓𝑠𝐵|𝑇 = 2𝜙𝐹 + 𝑉𝐷𝐵

𝑉𝑇𝐷 = 𝑉𝑇0 + 𝛾 (2𝜙𝐹 +𝑉𝐷𝐵 ) − 2𝜙𝐹

𝑉𝑇𝐷 = 𝑉𝑇𝑆 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 ) − 2𝜙𝐹 + 𝛾 (2𝜙𝐹 +𝑉𝐷𝐵 ) − 2𝜙𝐹 = 𝑉𝑇𝑆 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 ) − (2𝜙𝐹 +𝑉𝐷𝐵 )

𝑉𝑇𝐷 = 𝑉𝑇𝑆 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 ) − (2𝜙𝐹 +𝑉𝑆𝐵 + 𝑉𝐷𝑆 )

′ ′
𝑄𝐼|𝐷 =−𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝐷𝑆 − 𝑉𝑇𝑆 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 + 𝑉𝐷𝑆 ) − (2𝜙𝐹 +𝑉𝑆𝐵 )
′ ′ 𝑉 −𝑉 ′ ′ 𝑉 −𝑉 −𝑉
𝑄𝐼|𝑆 =−𝐶𝑜𝑥 𝐺𝑆 𝑇𝑆 𝑄𝐼|𝑐ℎ(𝑥) ≅ −𝐶𝑜𝑥 𝐺𝑆 𝑇 𝑐ℎ(𝑥)

′ ′
𝑄𝐼|𝑐ℎ(𝑥) =−𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑐ℎ(𝑥)𝑆 − 𝑉𝑇𝑆 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 + 𝑉𝑐ℎ(𝑥)𝑆 ) − (2𝜙𝐹 +𝑉𝑆𝐵 ) An overestimate
MOSFET G
S D
𝐿𝐷𝑟𝑎𝑤𝑛

𝑛+ 𝑊 𝑛+ 𝑛+
𝑛+ 𝐿𝐸𝑓𝑓
𝐿

P-Type

• Basic idea: Connect the majority carriers of S and D by a channel of carriers of same type
(opposite to those of the substrate)
• If a 𝑉𝐺𝐵 larger than the threshold voltage is applied, inversion layer will form in the channel
• If a potential difference is applied between S and D, there will be a current flow
• Key: Gate terminal voltage can control the conductivity of the channel
• Enhancement-mode (or Normally-OFF) devices and Depletion-mode (or Normally-ON) devices
 G
B S D Band Diagrams - At the surface, Along the Channel

𝑛+ 𝑛+
• Effectively, 𝑛+ 𝑝 junctions are forward biased
• 𝑒 − s get injected from 𝑛+ regions
P
• Because of the vertical field, 𝑒 − s remain at the
surface
𝑞𝑉𝑏𝑖 𝑉𝐺 = 0 • ∵ the 𝑒 − s are supplied by 𝑛+ regions, and are
𝑉𝐷 = 0 available in plenty, they can respond to high
𝑉𝑆 = 𝑉𝐵 = 0 frequencies
• ∴ unlike MOS cap, MOSFET can operate at
𝑞 𝑉𝑏𝑖 − 𝜓𝑠
𝑉𝐺 > 𝑉𝐹𝐵 high frequencies

𝑉𝐷 = 0 • Application of 𝑉𝐷 ⇒ Reverse bias of drain

junction
𝑉𝑆 = 𝑉𝐵 = 0
𝑞 𝑉𝑏𝑖 − 𝜓𝑠 • 𝑊𝑑𝑒𝑝 near drain widens (drain-induced
𝑉𝐺 > 𝑉𝐹𝐵 depletion)
𝑞𝑉𝐷
𝑉𝐷 > 0 • Injected 𝑒 − s can travel towards drain side by
𝑉𝑆 = 𝑉𝐵 = 0 (diffusion + drift) process – Current flow
 𝑉𝐺 = 0
Energy level diagrams along the channel
(Only 𝐸𝐶 shown here)
𝑉𝐺 > 0

𝑉𝐷 > 0

0 𝑥

Corresponding channel potential diagrams

Current-Voltage Characteristics

𝑉𝐺
• Assume: Long and wide channel B S D
• Assume S and B are tied to ground
𝑛+ 𝑛+
• Vertical electric field between G and B 𝑑𝐵𝑆 𝑑𝐵𝐷
• Lateral electric field between D and S
P
⇒ 2-D electric field in the device

Recall the potential balance equation of MOS capacitor

2𝑞𝜖𝑠 𝑁𝐴
𝑉𝐺𝐵 = 𝑉𝐹𝐵 + 𝜓𝑠 + 𝛾 𝜓𝑠 𝛾= ′
𝐶𝑜𝑥

For 𝜓𝑠 = 2𝜙𝐹 , 𝑉𝐺𝐵 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹

• Apply drain voltage 𝑉𝐷 (= 𝑉𝐷𝑆 )

• Define channel potential w.r.t. substrate 𝑉𝐶𝐵 (𝑥)

𝑉𝐺
• At 𝑥 = 0, 𝑉𝐶𝐵 0 = 𝑉𝑆𝐵 = 0 𝑉𝐷
B S
• At 𝑥 = 𝐿 , 𝑉𝐶𝐵 𝐿 = 𝑉𝐷𝐵 = 𝑉𝐷
𝑛+ 𝑛+
• Correspondingly, the gate-to-channel voltage 𝑑𝐵𝑆
𝑑𝐵𝐷
will also vary along the channel
𝑝
• At 𝑥 = 0, 𝑉𝐺𝐶 0 = 𝑉𝐺𝐵 − 𝑉𝐶𝐵 (0) = 𝑉𝐺𝑆

• At 𝑥 = 𝐿, 𝑉𝐺𝐶 𝐿 = 𝑉𝐺𝐵 − 𝑉𝐶𝐵 (𝐿) = 𝑉𝐺𝐷

• Note that 𝑉𝐺𝐷 < 𝑉𝐺𝑆

• Thus, threshold voltage to create S.I. will also

vary along the channel
 • As we move along the channel from S to D,
𝑉𝐺𝐶 keeps on reducing and, thus, the level of
inversion keeps on dropping. 𝑉𝐺
B S 𝑉𝐷
• Depletion layer under the drain has a larger width
than that under source 𝑛+
𝑛+
𝑑𝐵𝑆
• Note that the surface potential has to be higher 𝑑𝐵𝐷
than 2𝜙𝐹 + 𝑉𝐶𝐵 (𝑥) to ensure S.I. at any 𝑥
𝑝
• Corresponding to threshold condition,

𝑉𝐺𝐶 𝑥 + 𝑉𝐶𝐵 𝑥 = 𝑉𝐹𝐵 + (2𝜙𝐹 +𝑉𝐶𝐵 (𝑥)) + 𝛾 2𝜙𝐹 + 𝑉𝐶𝐵 (𝑥)

𝑉𝐺𝐶 𝑥 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 + 𝑉𝐶𝐵 (𝑥)

• As we move along the channel from S to D, 𝑉𝐶𝐵 𝑉𝐺
keeps on increasing and, thus, to keep the same 𝐵 𝑆 𝑉𝐷
level of inversion, 𝑉𝐺𝐶 should increase with 𝑥.
𝑛+ 𝑛+
• So, how do we define the threshold voltage? 𝑑𝐵𝑆 𝑑𝐵𝐷
• Universally accepted: At source end
P
Threshold voltage of a MOSFET: Gate-to-Source voltage
required to create strong inversion at the source end
′
𝑄𝐵,𝑚𝑎𝑥 Alternative form
𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 + ′
𝐶𝑜𝑥
𝑉𝐺𝐶 𝑥 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 + 𝑉𝐶𝐵 (𝑥) ′
𝑄𝐵,𝑚𝑎𝑥 ≃ − 2𝑞𝜖𝑠 𝑁𝐴 (2𝜙𝐹 + 𝑉𝑆𝐵 )

𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 In general, flat band voltage is negative.

∴ threshold voltage of P-channel devices is almost

Similarly, for PMOS
universally negative

𝑉𝑇𝑃 = 𝑉𝐹𝐵 − 2𝜙𝐹 − 𝛾 2𝜙𝐹 − 𝑉𝑆𝐵 For N-channel devices, it could be either positive
or negative
Rewriting
𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵

𝑉𝑇𝑁 = 𝑉𝑇𝑁0 + 𝛾( 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 )

𝑉𝑇𝑁0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹

𝑉𝑇𝑃 = 𝑉𝐹𝐵 − 2𝜙𝐹 − 𝛾 2𝜙𝐹 − 𝑉𝑆𝐵

zero back-bias threshold voltage
𝑉𝑇𝑃 = 𝑉𝑇𝑃0 − 𝛾( 2𝜙𝐹 − 𝑉𝑆𝐵 − 2𝜙𝐹 )
G G
𝑉𝑇𝑃0 = 𝑉𝐹𝐵 − 2𝜙𝐹 − 𝛾 2𝜙𝐹

S D S D
+𝑣𝑒 𝑉𝑇𝑁0 : Enhancement Mode or Normally-OFF devices
B B
−𝑣𝑒 𝑉𝑇𝑁0 : Depletion Mode or Normally-ON devices
Threshold voltage changes with technology 𝑉𝑇𝑁 Increasing 𝛾

Other parameters being constant, if the oxide thickness

is increased, how will threshold voltage change ?

2𝑞𝜖𝑠 𝑁𝐴 ′
𝛾= ′
𝑡𝑜𝑥 ↑ ⇒ 𝐶𝑜𝑥 ↓ ⇒ 𝛾 ↑ ⇒ 𝑉𝑇𝑁0 ↑
𝐶𝑜𝑥

Similarly, we can see the change with doping. 𝑉𝑆𝐵

For NMOS, 𝑉𝑇𝑁 = 𝑉𝑇𝑁0 + 𝛾( 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 )

Is it preferable to keep 𝑉𝑆𝐵 positive or negative ? Why ?
𝑉𝑇𝑁0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹
 Source-referenced Voltages
• Assume that the channel is sufficiently long and
wide 𝑉𝐺𝑆 𝑉𝐷𝑆 > 0
𝐼𝐺 = 0
→ Edge effects can be neglected 𝑉𝑆𝑆 = 0 𝑉𝐷𝑆
+++++++++++++++++++ + 𝐼𝐷𝑆
• Assume that the substrate is uniformly doped −
−−
𝑛+ − −−
− −−−−−−
−−−−−−−−−− −− −− − −−− 𝑛+
• Both B-S and B-D junctions are reverse biased − − − − − − − −
− − − − −
− −
• Assume that the rate of change of vertical field is
𝑥=0 𝑥=𝐿
much larger than the rate of change of lateral field 𝑁𝐴
i.e., 𝜕ℰ𝑦 Τ𝜕𝑦 ≫ 𝜕ℰ𝑥 Τ𝜕𝑥.
𝐼𝐵 = 0 𝑉𝐵𝑆
→ Any distortion of vertical field lines by horizontal
field can be neglected
𝑑 2 𝑉𝑥 𝑑 2 𝑉𝑦 𝜌 𝑑 2 𝑉𝑦 𝜌
→ 𝑉𝐶𝑆 (𝑥) can be assumed to vary linearly with 𝑥 + = − ≈ −
𝑑𝑥 2 𝑑𝑦 2 𝜖 𝑑𝑦 2 𝜖

Gradual Channel Approximation Approximate by 1D Poisson’s equation

Assume that only drift component of current is relevant.

Assume that there is no voltage drop in source and drain.

Assume that the inversion layer can be described by an average thickness.

𝑑𝑉𝐶𝑆 (𝑥)
Ohm’s law along 𝑥 : 𝐽𝑥 = 𝜎𝑛 ℰ𝑥 𝜎𝑛 = 𝑛𝑞𝜇𝑛 ℰ𝑥 =
𝑑𝑥

𝐼𝐷 = 𝐽𝑥 𝐴 (assume 𝐴 to be constant) 𝐴 = 𝑊𝑡𝐼𝑎𝑣𝑔 𝑡𝐼𝑎𝑣𝑔 ≜ Average thickness of inversion layer

𝜇𝑛 ≜ Surface electron mobility
|𝑄𝐼′ | = 𝑞𝑛𝑡𝐼𝑎𝑣𝑔 𝑄𝐼′ = ′ (𝑉
−𝐶𝑜𝑥 𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉𝐶𝑆 (𝑥))

Combining all of these, Assume it to be constant

′
𝑑𝑉𝐶𝑆 (𝑥)
𝐼𝐷 (𝑥) = 𝜇𝑛 𝑊𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉𝐶𝑆 (𝑥)
𝑑𝑥
𝐿 𝑉𝐷𝑆
′ න 𝜇 𝑉 −𝑉 ′
𝑊 1 2
න 𝐼𝐷 𝑑𝑥 = 𝑊𝐶𝑜𝑥 𝑛 𝐺𝑆 𝑇𝑁 − 𝑉𝐶𝑆 𝑥 𝑑𝑉𝐶𝑆 (𝑥) 𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ]
𝐿 2
0 0
 ′
𝑊 1 2 𝐼𝐷
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ]
𝐿 2
1 2
𝐼𝐷 = 𝑘𝑁 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉 ]
2 𝐷𝑆

′ ′
𝑘𝑁 = 𝜇𝑛 𝐶𝑜𝑥 Process transconductance parameter

′
𝑊
𝑘𝑁 = 𝑘𝑁 Device transconductance parameter 𝑉𝐷𝑆
𝐿

𝑊
Aspect ratio
𝐿
 𝐼𝐷𝑆 = 0 at 𝑉𝐷𝑆 = 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁
1 2
𝐼𝐷 = 𝑘𝑁 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ]
2 2
Small values of 𝑉𝐷𝑆 ⇒ 𝑉𝐷𝑆 is very small ⇒ Linear

Increase 𝑉𝐷𝑆 ⇒ Quadratic term comes into picture,

restraining the linear rate of increase linear saturation

Reaches a maximum value 𝐼𝐷𝑆,𝑚𝑎𝑥 at 𝑉𝐷𝑆 = 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝐼𝐷𝑆,𝑆𝑎𝑡

?
Becomes equal to zero 𝐼𝐷𝑆 = 0 at 𝑉𝐷𝑆 = 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁

Why the discrepancy ?

𝑉𝐷𝑆,𝑠𝑎𝑡 𝑉𝐷𝑆
𝑄𝐼′ = −𝐶𝑜𝑥
′ (𝑉 − 𝑉
𝐺𝑆 𝑇𝑁 − 𝑉𝐶𝑆 (𝑥))

𝑄𝐼′ = −𝐶𝑜𝑥
′ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉𝐷𝑆 𝑎𝑡 𝑥 = 𝐿 𝑉𝐷𝑆,𝑠𝑎𝑡 = (𝑉𝐺𝑆 − 𝑉𝑇𝑁 ) More closer to the
actual curve
𝑄𝐼′ at the drain = 0 at 𝑉𝐷𝑆 = (𝑉𝐺𝑆 − 𝑉𝑇𝑁 )

Phenomenon referred to as Pinch Off

 𝑄𝐼′
However, the inversion charge is not zero at this point.

At low values of inversion charge, the device is NOT in

strong inversion.

Hence, the strong inversion equation is not valid.

Exact expression for inversion charge should be used.

A small amount of charge will be present at the surface.

It can be in the weak inversion region.

𝑉𝐶𝐵
𝑉𝑃
S.I.
 𝑉𝐺𝑆 Linear 𝑉𝐶𝑆 𝑥

𝑉𝐷𝑆 𝑟 𝑟 𝑟 𝑟 𝑟
0 ∆𝑉𝐷1

𝑛+ 𝑛+
𝑝 𝑟 𝑟 𝑟 10000 𝑟
0 ∆𝑉𝐷2

High field region

Most of the field drops here
Any increase in 𝑉𝐷𝑆 does not
affect inversion layer field and
the current saturates
To make physical sense:

Let there be a small non-zero 𝑄𝐼′ at the drain end of the channel

Assume this length to be much lesser compared to channel length

Any change in 𝑉𝐷𝑆 above the pinchoff voltage will drop across the w.i./depletion region
𝐼 = 𝑊𝑄𝐼′ . 𝑣𝑑

Thus, there can be non-zero current if drift velocity is high

Because of high field, carriers travel at saturation drift velocity through the pinchoff region

High field region

𝑣𝑑
+ D
𝒏

𝑁𝐴
Water Analogy
 Level – 0 Model

𝐼𝐷𝑆 = 0 for 𝑉𝐺𝑆 < 𝑉𝑇𝑁 Cutoff

1 2
𝐼𝐷𝑆 = 𝑘𝑁 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉 ] for 𝑉𝐺𝑆 > 𝑉𝑇𝑁 and 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇𝑁 Non-Saturation
2 𝐷𝑆

1 2
𝐼𝐷𝑆 = 𝐼𝐷𝑆,𝑚𝑎𝑥 = 𝑘 𝑉 − 𝑉𝑇𝑁 for 𝑉𝐺𝑆 > 𝑉𝑇𝑁 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 Saturation
2 𝑁 𝐺𝑆 and

′ 𝑊
𝑘 𝑁 = 𝑘𝑁 (device transconductance parameter)
𝐿

′ ′ (process transconductance parameter)

𝑘𝑁 = 𝜇𝑛 𝐶𝑜𝑥
 Example

An N-channel MOSFET is operated with its source and body terminals grounded and 1V applied to its gate
′
terminal. It has the following parameters: 𝑉𝑇𝑁0 = 0.7 V, 𝑘𝑁 = 40 μAV −2 , 𝛾 = 0.4 V1/2 , 2𝜙𝐹 = 0.6 V, 𝑊 =
10 μm, and 𝐿 = 1 μm. (a) Determine the drain current for applied drain potential equal to 0.2 V and 5 V. (b)
What body bias will make the drain current to be zero?

𝑉𝑇𝑁 = 𝑉𝑇𝑁0 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 = 𝑉𝑇𝑁0 = 0.7 V

∴ 𝑉𝐺𝑆 > 𝑉𝑇𝑁 ⇒ MOSFET is not in cut-off region

𝑉𝐷𝑆,𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 1 − 0.7 = 0.3 V

𝑉𝐷𝑆 = 0.2 V ⇒ 𝑉𝐷𝑆 < 𝑉𝐷𝑆,𝑆𝑎𝑡 ⇒ MOSFET is in non-saturation region

𝑉𝐷𝑆 = 5 V ⇒ 𝑉𝐷𝑆 > 𝑉𝐷𝑆,𝑆𝑎𝑡 ⇒ MOSFET is in saturation region

 Example

An N-channel MOSFET is operated with its source and body terminals grounded and 1V applied to its gate
′
terminal. It has the following parameters: 𝑉𝑇𝑁0 = 0.7 V, 𝑘𝑁 = 40 μAV −2 , 𝛾 = 0.4 V1/2 , 2𝜙𝐹 = 0.6 V, 𝑊 =
10 μm, and 𝐿 = 1 μm. (a) Determine the drain current for applied drain potential equal to 0.2 V and 5 V. (b)
What body bias will make the drain current to be zero?
1 2
𝑉𝐷𝑆 = 0.2 V ⇒ 𝑉𝐷𝑆 < 𝑉𝐷𝑆,𝑆𝑎𝑡 ⇒ non-saturation ⇒ 𝐼𝐷𝑆 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 = 16 μA
2

1 2
𝑉𝐷𝑆 = 5 V ⇒ 𝑉𝐷𝑆 > 𝑉𝐷𝑆,𝑆𝑎𝑡 ⇒ saturation ⇒ 𝐼𝐷𝑆 = 𝐼𝐷𝑆,𝑆𝑎𝑡 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 18 μA
2

′
𝑊
𝑘𝑁 = 𝑘𝑁 = 400 μAV −2
𝐿
 Example

An N-channel MOSFET is operated with its source and body terminals grounded and 1V applied to its gate
′
terminal. It has the following parameters: 𝑉𝑇𝑁0 = 0.7 V, 𝑘𝑁 = 40 μAV −2 , 𝛾 = 0.4 V1/2 , 2𝜙𝐹 = 0.6 V, 𝑊 =
10 μm, and 𝐿 = 1 μm. (a) Determine the drain current for applied drain potential equal to 0.2 V and 5 V. (b)
What body bias will make the drain current to be zero?

Drain current will be zero when 𝑉𝐺𝑆 ≤ 𝑉𝑇𝑁 in level-0 model i.e., when 𝑉𝑇𝑁 = 1 V, 𝐼𝐷𝑆 = 0

𝑉𝑇𝑁 = 𝑉𝑇𝑁0 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 = 1 V

0.7 + 0.4 0.6 + 𝑉𝑆𝐵 − 0.6 = 1 V

⇒ 𝑉𝑆𝐵 = 1.72 V i.e., with source grounded, apply −1.72 V to body terminal.
EE203 Semiconductor Devices

MOSFET - 3

Level – 1 Model
MOSFET G
S D
𝐿𝐷𝑟𝑎𝑤𝑛

𝑛+ 𝑊 𝑛+ 𝑛+
𝑛+ 𝐿𝐸𝑓𝑓
𝐿

P-Type

• Basic idea: Connect the majority carriers of S and D by a channel of carriers of same type
(opposite to those of the substrate)
• If a 𝑉𝐺𝐵 larger than the threshold voltage is applied, inversion layer will form in the channel
• If a potential difference is applied between S and D, there will be a current flow
• Key: Gate terminal voltage can control the conductivity of the channel
• Enhancement-mode (or Normally-OFF) devices and Depletion-mode (or Normally-ON) devices
 Transfer Characteristics

1 2 𝐼𝐷𝑆
𝐼𝐷𝑆 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 Mobility degradation
2 Source/Drain resistance
1
= 𝑘𝑁 [𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉𝐷𝑆 ]𝑉𝐷𝑆
2 for a small 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇𝑁

Small 𝑉𝐷𝑆

Intercept gives threshold voltage

1 1
𝐼𝐷𝑆 = 0 ⇒ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉𝐷𝑆 = 0 ⇒ 𝑉𝑇𝑁 = 𝑉𝐺𝑆 − 𝑉𝐷𝑆
2 2

𝑉𝐺𝑆
Slope gives electron mobility
Weak Inversion Region
′
𝑊
𝑘𝑁 = 𝜇𝑛 𝐶𝑜𝑥
𝐿
 Transconductance

𝜕𝐼𝐷𝑆
𝐼𝐷𝑆 𝑔𝑚 𝑔𝑚 =
Mobility degradation 𝜕𝑉𝐺𝑆
Source/Drain resistance

𝑔𝑚,𝑚𝑎𝑥

𝑉𝐺𝑆 𝑉𝑇𝑁 𝑉𝐺𝑆

𝑉𝑇𝑁
 Transconductance

MOSFET transconductance is defined as the change in drain current with respect to the change in gate voltage

𝜕𝐼𝐷𝑆
𝑔𝑚 =
𝜕𝑉𝐺𝑆

′
𝑊 1 2 ′
𝑊
Linear region: 𝐼𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉 ⇒ 𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 𝑉 ⇒ Independent of 𝑉𝐺𝑆
𝐿 2 𝐷𝑆 𝐿 𝐷𝑆

1 2 𝑊
Saturation region: 𝐼𝐷𝑆 = 𝐼𝐷𝑆,𝑆𝑎𝑡 = 𝑘 𝑉 − 𝑉𝑇𝑁 ⇒ ′
𝑔𝑚 = 𝜇𝑛 𝐶𝑜𝑥 (𝑉 − 𝑉𝑇𝑁 ) ⇒ Independent of 𝑉𝐷𝑆
2 𝑁 𝐺𝑆 𝐿 𝐺𝑆
 Beyond Pinch-off: Channel Length Modulation

𝑉𝐺𝑆 𝑉𝐷𝑆,𝑆𝑎𝑡 𝐼𝐷𝑆

Does not saturate

𝑛+ 𝑛+
𝐿
𝐼𝐷𝑆,𝑆𝑎𝑡
𝑝-sub

𝑉𝐺𝑆 𝑉𝐷𝑆 > 𝑉𝐷𝑆,𝑆𝑎𝑡

𝑉𝐷𝑆
𝑉𝐷𝑆,𝑠𝑎𝑡
𝑛+ 𝑛+
𝐿′
1 ′
𝑊 2
𝑝-sub 𝐼𝐷𝑆,𝑆𝑎𝑡 = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝑁
2 𝐿 𝐺𝑆
 ~(𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡 )
𝑄𝐼′ = 0, 𝑉𝐷𝑆,𝑠𝑎𝑡 𝑄𝐼′ = 0, 𝑉𝐷𝑆,𝑠𝑎𝑡 𝑉𝐷𝑆
𝑉𝐷𝑆

n+ D n+ D

𝑙
𝐿 𝐿
′
NA- 𝐿 NA-
𝑟 𝑟 𝑟 … 𝑟 𝑟 𝑟 … 𝑅
… ∆𝑉𝐷 … ∆𝑉𝐷

𝑄𝐼′ 𝑄𝐼′

𝑥
𝑥

Effective channel length, 𝐿′ = (𝐿 − 𝑙)

𝑙 increases with increase in 𝑉𝐷𝑆
𝐿′ decreases with increase in 𝑉𝐷𝑆
 Channel length ↓ ⇒ 𝐼𝐷, 𝑠𝑎𝑡 ↑

𝑉𝐷𝑆 = 𝑉𝐷𝑆,𝑠𝑎𝑡 𝑉𝐷𝑆 > 𝑉𝐷𝑆,𝑠𝑎𝑡

1 ′ 𝑊 1 ′ 𝑊 2
2 → 𝐼𝐷𝑆,𝑠𝑎𝑡 = 𝑘𝑁 𝑉 − 𝑉𝑇𝑁
𝐼𝐷𝑆,𝑠𝑎𝑡 = 𝑘𝑁 𝑉 − 𝑉𝑇𝑁
2 𝐿 𝐺𝑆 2 (𝐿 − 𝑙) 𝐺𝑆

𝐿′ = (𝐿 − 𝑙)

1 1 𝑙
For small 𝑙, (𝐿−𝑙) ≅ 1+𝐿
𝐿

1 ′ 𝑊 2
𝑙
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘 𝑉 − 𝑉𝑇𝑁 1+
2 𝑁 𝐿 𝐺𝑆 𝐿

(form better for convergence while using numerical methods)

 𝑙 =?
1 ′ 𝑊 2
𝑙
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘 𝑉 − 𝑉𝑇𝑁 1+
2 𝑁 𝐿 𝐺𝑆 𝐿

Simple approximation of average field gives:

1 ′ 𝑊 2
(𝑉𝐷𝑆 −𝑉𝐷𝑆,𝑆𝑎𝑡 )
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘𝑁 𝑉 − 𝑉𝑇𝑁 1+
2 𝐿 𝐺𝑆 𝐸𝑎𝑣𝑔 𝐿

1 ′ 𝑊 2
1 1
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘𝑁 𝑉 − 𝑉𝑇𝑁 1 + 𝜆′(𝑉𝐷𝑆 −𝑉𝐷𝑆,𝑆𝑎𝑡 ) 𝜆′ = 𝜆′ ∝
2 𝐿 𝐺𝑆 𝐸𝑎𝑣𝑔 𝐿 𝐿

Smaller channel lengths ⇒ Effect of 𝜆′ will be higher

 𝑙 =?
Solving 1D Poisson’s equation gives:

ℰ𝑥
2𝜖𝑠 𝜖𝑠 ℰ12
𝑙1𝐷 ≈ 𝜙𝐷 + 𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡 − 𝜙𝐷 𝜙𝐷 =
𝑞𝑁𝐴 2𝑞𝑁𝐴 ℰ𝑚
ℰ1
~ℰ𝑐
Pseudo-2D analysis gives:
𝐿−𝑙 𝐿
𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡
+ ℰ𝑚 𝜖𝑠
𝑙𝑎 𝑙𝑎 = 𝑡 𝑑
𝑙2𝐷 = 𝑙𝑎 𝑙𝑛
ℰ1 𝜖𝑜𝑥 𝑜𝑥 𝑗

𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡 𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡

ℰ𝑚 = ℰ1 + 𝑐𝑜𝑛𝑠𝑡. 𝑙2𝐷 = 𝑙𝑎 𝑙𝑛 1 +
𝑙𝑎 𝑉𝐸

𝜙𝐷 , 𝑉𝐸 ∶ Mostly treated as fitting parameters

 𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡
𝑙2𝐷 = 𝑙𝑎 𝑙𝑛 1 + 1 + 𝜖 ≈ 𝜖 for small 𝜖
𝑉𝐸

𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡
𝑙2𝐷 ≈ 𝑙𝑎
𝑉𝐸

1 ′ 𝑊 2
𝑙
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘 𝑉 − 𝑉𝑇𝑁 1+
2 𝑁 𝐿 𝐺𝑆 𝐿

1 ′ 𝑊 2
𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘 𝑉 − 𝑉𝑇𝑁 1+
2 𝑁 𝐿 𝐺𝑆 𝑉𝐸 𝐿/𝑙𝑎

1 ′ 𝑊 2
𝑉𝐷𝑆 − 𝑉𝐷𝑆,𝑠𝑎𝑡
𝐼𝐷𝑆,𝑠𝑎𝑡 ≅ 𝑘 𝑉 − 𝑉𝑇𝑁 1+ 𝑉𝐴 = 𝑉𝐸 𝐿/𝑙𝑎
2 𝑁 𝐿 𝐺𝑆 𝑉𝐴
 𝐼𝐷
Slope - Discontinuity

1 2
𝐼𝐷𝑆,𝑠𝑎𝑡 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 Level 0
2
1
𝐼𝐷𝑆,𝑠𝑎𝑡 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 2 (1 + 𝜆𝑉𝐷𝑆 ) Level 1
2

Corrective multiplication term

𝑉𝐷𝑆

Numerical convergence of non-saturation and saturation equations:

Include this term in non-saturation 𝐼 − 𝑉 as well
Note: This has no physical justification
Level – 1 Model

𝐼𝐷𝑆 = 0 𝑉𝐺𝑆 ≤ 𝑉𝑇𝑁 Cutoff

1 2
𝐼𝐷𝑆 = 𝑘𝑁 [ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ](1 + 𝜆𝑉𝐷𝑆 ) 𝑉𝐺𝑆 > 𝑉𝑇𝑁 𝑉𝐷𝑆 < 𝑉𝐺𝑆 − 𝑉𝑇𝑁 Non-Saturation
2

1
𝐼𝐷𝑆 = 𝑘𝑁 𝑉𝐺𝑆 − 𝑉𝑇𝑁 2 (1 + 𝜆𝑉𝐷𝑆 ) 𝑉𝐺𝑆 > 𝑉𝑇𝑁 𝑉𝐷𝑆 ≥ 𝑉𝐺𝑆 − 𝑉𝑇𝑁 Saturation
2

Schichman-Hodges Model

Note: Unlike with level 0 model, it is clear here that

the gate does not have exclusive control of the channel
 EE203 Semiconductor Devices

MOSFET - 4

Non-Idealities and Small Channel Effects

Effective Mobility

One of the assumptions – Mobility is constant in the channel.

• Lattice/Phonon scattering (vibrating lattice atoms)
• Coulomb scattering (ionized impurity atoms) Mobilities due to various
scattering events add
• Electron-electron scattering (other electrons) inversely
• Surface scattering (surface roughness/surface defects/oxide charges) 1 1 1 1
= + + …
• Additional mechanism for surface 𝑒 − s ⇒ Surface mobility < Bulk mobility 𝜇 𝜇1 𝜇2 𝜇3

• At very low fields, typically, surface mobility ~ half of bulk mobility

• Apply 𝑉𝐺𝑆 , 𝑉𝐷𝑆 , and 𝑉𝑆𝐵 ⇒ Varying 2D electric fields that deflect carrier paths
• Complex analysis !
 ▪ Coulomb scattering also due to
✓ Interface trapped charges
✓ Charges trapped inside the oxide
▪ Surface Roughness

Different mechanisms dominate in

different ranges of field values

[Link]
• Significant 𝑄𝐼′ → inversion layer charge screens itself from Coulomb
scattering (both ionized impurity as well as oxide charges)

• ℰ𝑦 → accelerates inversion layer 𝑒 − s towards surface ⇒ additional

scattering from surface ⇒ 𝜇𝑛 reduces as a function of vertical field
ℰ𝑦,0 +ℰ𝑦,𝑦𝑐
• Assume ℰ𝑦,𝑎𝑣𝑔 = (top & bottom of the inversion layer) 𝜇𝑛 (log)
2

• Low ℰ𝑦,𝑎𝑣𝑔 → Coulomb scattering due to impurity atoms and oxide 𝑁𝐴2 > 𝑁𝐴1
charges dominate

• Increase ℰ𝑦,𝑎𝑣𝑔 → 𝑄𝐼′ becomes large, screens Coulomb scattering ⇒ 𝜇𝑛 𝑁𝐴1

increases initially 𝑁𝐴2

• Phonon scattering limits 𝜇𝑛

• Higher ℰ𝑦,𝑎𝑣𝑔 → strongly pulls 𝑒 − s to surface and surface scattering

ℰ𝑦,𝑎𝑣𝑔 (log)
dominates ⇒ 𝜇𝑛 reduces further

• Higher doping ⇒ 1. Higher impurity scattering 2. Significant 𝑄𝐼′ will form

only at a higher field ⇒ Right shift of the curve
 With 𝑉𝐺𝑆 above 𝑉𝑇𝑁 , i.e., with significant inversion charge,

𝑉𝐺𝑇0 ↑ ⇒ ℰ𝑦 ↑ ⇒ 𝜇 ↓ Level-0
𝐼𝐷𝑆
𝑉𝑆𝐵 ↑ ⇒ ℰ𝑦 ↑ ⇒ 𝜇 ↓

Consequently, 𝐼𝐷𝑆 increases at lower rate w.r.t. 𝑉𝐺𝑆

𝑉𝐺𝑇0 ≜ 𝑉𝐺𝑆 − 𝑉𝑇𝑁|𝑉𝑆𝐵 =0 = 𝑉𝐺𝑆 − 𝑉𝑇𝑁0

𝑉𝑇𝑁0 = 𝑉𝐹𝐵 + 2𝜙𝐹 + 𝛾 2𝜙𝐹 At a small 𝑉𝐷𝑆

and a fixed 𝑉𝑆𝐵

One of the suggested models

𝑉𝐺𝑆
𝜇0
𝜇𝑒𝑓𝑓 =
1 + 𝜃𝑉𝐺𝑇0 + 𝜃𝐵 𝑉𝑆𝐵

𝛽𝜃 Neglecting the dependence on 𝑉𝐷𝑆

𝜃= 𝛽𝜃 : 0.5 𝑡𝑜 2 nm/V
𝑡𝑜𝑥
 Example

For an N-channel MOSFET, threshold voltage = 0.8 V for some back bias. Applied gate-to-source and drain-to-
source voltages are 2 V and 50 mV. If the low-field e- mobility is 600 cm2 V −1 s−1, determine effective mobility
for an oxide thickness of (a) 100 nm and (b) 10 nm. Given 𝛽𝜃 : 1 nm/V, Neglect the effect of 𝑉𝑆𝐵 , Assume
𝑉𝑇𝑁0 = 𝑉𝑇𝑁 .

𝜇0
𝜇𝑒𝑓𝑓 =
1 + 𝜃𝑉𝐺𝑇0 + 𝜃𝐵 𝑉𝑆𝐵
Reduction of oxide thickness while scaling down
𝛽𝜃 the MOSFET size significantly impacts its speed
𝜃= = 0.01 V −1 and = 0.1 V −1
𝑡𝑜𝑥

𝑉𝐺𝑇0 = 𝑉𝐺𝑆 − 𝑉𝑇𝑁0 = 1.2 V

𝜇𝑒𝑓𝑓 = 592.9 cm2 V −1 s−1 and 535.7 cm2 V −1 s−1

 Bulk-Charge Effect

One of the approximations we made: Ignore the variation of depletion charge along the channel

Ignoring the variation of depletion charge

𝑄𝐵′
𝑄𝐼′ = ′ (𝑉
−𝐶𝑜𝑥 𝐺𝐵 − 𝑉𝐹𝐵 − 𝜓𝑠 − 𝛾 𝜓𝑠 ) along the channel – Constant depletion charge

𝑄𝐼′ = −𝐶𝑜𝑥
′ (𝑉
𝐺𝐵 − 𝑉𝐹𝐵 − (2𝜙𝐹 +𝑉𝐶𝐵 (𝑥)) − 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 (𝑥))

𝑄𝐼′ = −𝐶𝑜𝑥
′ (𝑉
𝐺𝐵 − 𝑉𝑇𝑁 − 𝑉𝐶𝐵 (𝑥))

𝑄𝐼′ = −𝐶𝑜𝑥
′ (𝑉 − 𝑉
𝐺𝑆 𝑇𝑁 − 𝑉𝐶𝑆 (𝑥))

(With the source terminal as reference)

 Bulk-Charge Effect

• One of the approximations: Ignore the variation of depletion charge along the channel

• But the depletion charge varies from source to drain

• Accordingly, the inversion charge is lowered 𝑄𝐺′ = −𝑄𝐶′ 𝑄𝐶′ = 𝑄𝐼′ + 𝑄𝐵′
• Hence, the current will also be lower

𝑉𝐺
B S 𝑉𝐷

𝑛+ 𝑛+
𝑑𝐵𝑆 𝑑𝐵𝐷

𝑝
 Bulk-Charge Effect

𝑄𝐼′ = −𝐶𝑜𝑥
′
(𝑉𝐺𝐵 − 𝑉𝐹𝐵 − (2𝜙𝐹 +𝑉𝐶𝐵 (𝑥)) − 𝛾 (2𝜙𝐹 +𝑉𝐶𝐵 (𝑥))

′
𝑊 1 2 3/2 3/2
𝐼𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝐹𝐵 − 2𝜙𝐹 − 𝑉𝐷𝑆 𝑉𝐷𝑆 − 𝛾 2𝜙𝐹 + 𝑉𝐷𝐵 − 2𝜙𝐹 + 𝑉𝑆𝐵
𝐿 2 3

′
𝑊 1 2 3/2 3/2
𝐼𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝐹𝐵 − 2𝜙𝐹 − 𝑉𝐷𝑆 𝑉𝐷𝑆 − 𝛾 2𝜙𝐹 + 𝑉𝐷𝑆 − 2𝜙𝐹 when 𝑉𝑆 = 𝑉𝐵 = 0
𝐿 2 3

Complicated equations
Designers typically use a fitting parameter to avoid this type of equations
Bulk-Charge Effect

′
𝑊 𝛼 2
𝐼𝐷𝑆 = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉 𝛼: A fitting parameter ~ 1.5
𝐿 2 𝐷𝑆
Called as Bulk-charge factor
1
𝑉𝐷𝑆,𝑠𝑎𝑡 = (𝑉𝐺𝑆 − 𝑉𝑇𝑁 )
𝛼

1 ′
𝑊 2
1
𝐼𝐷 = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝑁
2 𝐿 𝐺𝑆 𝛼
 Velocity Saturation
ℰ𝑥 ≪ ℰ𝑐 → 𝑣𝑑 = 𝜇𝑛 ℰ𝑥 ℰ𝑥 ≫ ℰ𝑐 → 𝑣𝑑 = 𝑣𝑠𝑎𝑡

• Consider a MOSFET under S.I., in linear region 𝑣𝑑

• Drain current is primarily through drift (~107 cm/s) 𝑣𝑠𝑎𝑡

𝑣𝑠𝑎𝑡 = 𝜇𝑛 ℰ𝑐
• Two-piece model: (a) Insufficient for transition region (b)
Slope change issue.

• How do we incorporate this effect? One simple model is:

ℰ𝑥
ℰ𝑐
ℰ𝑥 /ℰ𝑐
𝑣𝑑 = 𝑣𝑠𝑎𝑡 (~104 V/cm)
1 + ℰ𝑥 /ℰ𝑐

For a MOSFET, 𝑑𝑉𝐶𝐵 𝑑𝑉𝐶𝐵

ൗℰ𝑐
𝑑𝑥 𝑑𝑥
𝜓𝑠 = 2𝜙𝐹 + 𝑉𝐶𝐵 (𝑥) 𝑣𝑑 𝑥 = 𝑣𝑠𝑎𝑡 = 𝜇𝑛
𝑑𝑉𝐶𝐵 𝑑𝑉𝐶𝐵
1+ ൗℰ𝑐 1+ ൗ ℰ𝑐
𝑑𝑥 𝑑𝑥
𝑑𝜓𝑠 𝑑𝑉𝐶𝐵
∴ ℰ𝑥 = =
𝑑𝑥 𝑑𝑥
𝐼𝐷𝑆 = 𝑊|𝑄𝐼′ |𝑣𝑑 𝐿 𝑉𝐷𝐵
1
𝑉𝐷𝐵

න 𝐼𝐷𝑆 𝑑𝑥 = 𝑊𝜇𝑛 න |𝑄𝐼′ |𝑑𝑉𝐶𝐵 − න 𝐼𝐷𝑆 𝑑𝑉𝐶𝐵

ℰ𝑐
𝑑𝑉𝐶𝐵 0 𝑉𝑆𝐵 𝑉𝑆𝐵
𝑑𝑥
𝐼𝐷𝑆 = 𝑊|𝑄𝐼′ |𝜇𝑛
𝑑𝑉𝐶𝐵 𝑉𝐷𝐵
1+ ൗℰ𝑐 𝑉𝐷𝐵 − 𝑉𝑆𝐵
𝑑𝑥
𝐼𝐷𝑆 𝐿 = 𝑊𝜇𝑛 න |𝑄𝐼′ |𝑑𝑉𝐶𝐵 − 𝐼𝐷𝑆
ℰ𝑐
𝑉𝑆𝐵
𝑑𝑉𝐶𝐵 𝑑𝑉𝐶𝐵
𝐼𝐷𝑆 1 + ൗℰ𝑐 = 𝑊|𝑄𝐼′ |𝜇𝑛
𝑑𝑥 𝑑𝑥 𝑉𝐷𝐵
𝑉𝐷𝑆
𝐼𝐷𝑆 𝐿+ = 𝑊𝜇𝑛 න |𝑄𝐼′ |𝑑𝑉𝐶𝐵
ℰ𝑐 𝑉𝑆𝐵
Integrate from source to drain
1 𝑊 𝑉𝐷𝐵 ′
𝐼𝐷𝑆 = 𝜇 න |𝑄 |𝑑𝑉
𝑥 = 0 → 𝑉𝐶𝐵 0 = 𝑉𝑆𝐵 1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 ) 𝑛 𝐿 𝑉𝑆𝐵 𝐼 𝐶𝐵
𝑥 = 𝐿 → 𝑉𝐶𝐵 𝐿 = 𝑉𝐷𝐵
𝐼𝐷𝑆|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡.
 𝐼𝐷𝑆|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡. ′
𝑊 1 2
𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡. = 𝐼𝐷𝑆|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡. = 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉
1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 ) 𝐿 2 𝐷𝑆

For 𝑉𝐷𝑆 < 𝑉𝐷𝑆,𝑠𝑎𝑡

⇒ Magnitude of drain current reduces with velocity saturation

Long channel → 𝐿ℰ𝑐 ≫ 𝑉𝐷𝑆 ⇒ Negligible effect of velocity saturation

Short channel devices → Effect of velocity saturation will be significant

 𝐼𝐷𝑆|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡.
𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡. = 𝑉𝐷𝑆 < 𝑉𝐷𝑆,𝑠𝑎𝑡
1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 )

For severe velocity saturation, say with very small channel length,

→ 𝐿ℰ𝑐 ≪ 𝑉𝐷𝑆 ⇒ (1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 )) ≈ 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 )

𝐿ℰ𝑐 𝑊 1 2 𝐿ℰ𝑐 1
𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡. ≈ 𝐼𝐷𝑆,|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡. ′
= 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑉𝐷𝑆 − 𝑉𝐷𝑆 ′ 𝑊ℰ
= 𝜇𝑛 𝐶𝑜𝑥 𝑐 𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉
𝑉𝐷𝑆 𝐿 2 𝑉𝐷𝑆 2 𝐷𝑆

⇒ Current becomes independent of channel length for severe velocity saturation

 Velocity Saturation: Saturation Voltage

′ 𝑊 𝑉 −𝑉
𝜇𝑛 𝐶𝑜𝑥 𝑉 −
1 2
𝐿 𝐺𝑆 𝑇𝑁 𝐷𝑆 2 𝑉𝐷𝑆 Max. value at
𝑑𝐼𝐷𝑆
=0
𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡. = 𝑑𝑉𝐷𝑆
1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 )

2 𝑉𝐺𝑆 − 𝑉𝑇𝑁
𝑉𝐷𝑆,𝑠𝑎𝑡|𝑣𝑒𝑙. 𝑠𝑎𝑡. = < 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 𝑉𝐷𝑆,𝑠𝑎𝑡|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡.
2 𝑉𝐺𝑆 − 𝑉𝑇𝑁
1+ 1+ 𝐿ℰ𝑐

⇒ Saturation voltage reduces with velocity saturation

For very small channel lengths i.e., under severe velocity saturation, 𝑉𝐷𝑆,𝑠𝑎𝑡|𝑣𝑒𝑙. 𝑠𝑎𝑡. becomes a small value.
✓ Magnitude of drain current reduces with velocity saturation

✓ Saturation voltage reduces with velocity saturation

𝐼𝐷𝑆

𝐼𝐷𝑆|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡.

𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡.

𝑉𝐷𝑆
𝑉𝐷𝑆,𝑠𝑎𝑡
 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁
𝑉𝐷𝑆,𝑠𝑎𝑡|𝑣𝑒𝑙. 𝑠𝑎𝑡. =
2 𝑉𝐺𝑆 − 𝑉𝑇𝑁
1+ 1+ 𝐿ℰ𝑐

0.5 0.5
VGS-VT = 0.5 V
0.4 0.4
EC = 2X104 V/cm
VGS-VT = 0.5 V
VDS,Sat (V)

VDS,Sat (V)
0.3 0.3
EC = 2X104 V/cm
0.2 0.2

0.1 0.1
0.0 0.0
0 20 40 60 80 100 120 1E-3 0.01 0.1 1 10 100
L (m) L (m)

Log Scale
 Velocity Saturation: Saturation Current

′ 𝑊 1 2
𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉 𝑉 −
𝐿 𝐺𝑆 𝑇𝑁 𝐷𝑆 2 𝑉𝐷𝑆 ′
𝐼𝐷𝑆,𝑠𝑎𝑡|𝑣𝑒𝑙. 𝑠𝑎𝑡. ≈ 𝜇𝑛 ℰ𝑐 𝑊𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁
𝐼𝐷𝑆|𝑣𝑒𝑙. 𝑠𝑎𝑡. =
1 + 𝑉𝐷𝑆 Τ(𝐿ℰ𝑐 )

1 = 𝑊(−𝑄𝐼′ ) 𝑣𝑑,𝑠𝑎𝑡
′ 𝑊ℰ
≈ 𝜇𝑛 𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 − 𝑉
𝑐 Linear
2 𝐷𝑆
relation

250
Constant velocity Max. current
VGS-VT = 0.5 V
200 ⇒ Constant charge when velocity
EC = 2X104 V/cm
∵ Current is constant is maximum all
150
everywhere along the channel
VDS/LEC

100

50

0 Independent of channel length

1E-3 0.01 0.1 1 10 100
L (m)
𝑥-axis: log scale
 1 ′
𝑊 2
𝐼𝐷𝑆,𝑠𝑎𝑡|𝑛𝑜 𝑣𝑒𝑙. 𝑠𝑎𝑡. = 𝜇𝑛 𝐶𝑜𝑥 𝑉 − 𝑉𝑇𝑁 ⇒ Quadratic dependence on gate voltage
2 𝐿 𝐺𝑆

Independent of 𝑉𝐷𝑆 Not entirely true

′
𝐼𝐷𝑆,𝑠𝑎𝑡|𝑣𝑒𝑙.𝑠𝑎𝑡. ≈ 𝑊𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝜇𝑛 ℰ𝑐 ‘Channel length modulation’

quadratic
increments
𝐼𝐷𝑆,𝑠𝑎𝑡 Without V.S. 𝐼𝐷𝑆, 𝑛𝑜 𝑣𝑒𝑙.𝑠𝑎𝑡. 𝐼𝐷𝑆, 𝑣𝑒𝑙.𝑠𝑎𝑡.
𝑉𝐺𝑆 = 5𝑉 proportional
increments
With V.S. 4𝑉
𝑉𝐺𝑆 = 5𝑉

3𝑉 4𝑉
3𝑉
2𝑉 2𝑉
𝑉𝐺𝑆 𝑉𝐷𝑆 𝑉𝐷𝑆
 EE203 Semiconductor Devices

MOSFET - 5

Non-Idealities and Small Channel Effects - 2

Sub-Threshold Characteristics

𝐼𝐷𝑆 Level 0 Model

𝐼𝐷𝑆 Sub-threshold
Log Scale

W.I.

𝑉𝐺𝑆 𝑉𝑇𝑁 𝑉𝐺𝑆

𝑉𝑇𝑁

MOSFET below threshold voltage: Off-state current

⇒ Power dissipation, Discharge of capacitances in memories etc.

 𝜙𝐹 < 𝜓𝑠 < 2𝜙𝐹 𝑛𝑠 > 𝑛𝑖

• W.I. → Inversion charge is not significant – Very few e-s

• Potential gradient across the channel will be negligible ℰ𝑥 ≈ 0
• Any applied drain voltage drops only in the depletion region at the channel-drain junction
• Surface potential can be assumed to be almost constant over the channel region
• No drift current
• Charge gradient between source and drain
• Thus, any small number of inversion charges will mainly flow by diffusion

∝ 𝑒 −𝑉𝑆𝐵/𝑉𝑇 Major: Diffusion ∝ 𝑒 − 𝑉𝐷𝐵)/𝑉𝑇

 𝑑𝑛
𝐽𝑥(𝑑𝑖𝑓𝑓) = 𝑞𝐷𝑛 𝐷𝑛 = 𝜇𝑛 𝑉𝑇 𝐼𝐷𝑆 = 𝐴. 𝐽𝑥 𝐴 = 𝑊𝑡𝐼𝑎𝑣𝑔
𝑑𝑥

𝑑𝑛 1 𝑑𝑄𝐼′ 1 𝑑𝑄𝐼′ 𝑑𝑄𝐼′

|𝑄𝐼′ | = 𝑞𝑛𝑡𝐼𝑎𝑣𝑔 ⇒ = 𝐼𝐷𝑆 = 𝑊𝑡𝐼𝑎𝑣𝑔 𝑞𝜇𝑛 𝑉𝑇 = 𝑊𝜇𝑛 𝑉𝑇
𝑑𝑥 𝑞𝑡𝐼𝑎𝑣𝑔 𝑑𝑥 𝑞𝑡𝐼𝑎𝑣𝑔 𝑑𝑥 𝑑𝑥

𝑑𝑄𝐼′ ′
𝑄𝐼0 ′
− 𝑄𝐼𝐿 1 ′ ′
𝑄𝐼𝐿 ′
𝑄𝐼𝐿 𝑒 −𝑉𝐷𝐵/𝑉𝑇
= = 𝑄 1− ′ −𝑉𝐷𝑆 /𝑉𝑇
𝑑𝑥 𝐿 𝐿 𝐼0 𝑄𝐼0 ′ = −𝑉𝑆𝐵 /𝑉𝑇 = 𝑒
𝑄𝐼0 𝑒
𝑄𝐼′

0 𝐿
′
𝑄𝐼𝐿
′
𝑄𝐼0
 2𝜖𝑠 𝑞𝑁𝐴 𝜓𝑠
𝑉𝐺𝐵 = 𝑉𝐹𝐵 + 𝜓𝑠 + ′
𝑉𝐺𝑆 → 𝜓𝑠 , 𝜓𝑠 near-linear variation 𝐶𝑜𝑥

(Take into account 𝑉𝐶𝐵 )

𝑄𝐼′ → 𝑛𝑠 → 𝑒 𝑞𝜓𝑠 /𝑘𝑇 exponential variation
Similar form, when written with
source reference
𝑄𝐼′ → 𝑉𝐺𝑆 ? ✓ exponential variation,
(with some multiplication factor)
Variation of drain current with gate voltage above threshold:
• Non-Saturation: Linear
• Saturation: Quadratic

𝑊 (𝑉𝐺𝑆 −𝑉𝑇𝑁 )
ൗ𝑛𝑉 −𝑉𝐷𝑆
ൗ𝑉
𝐼𝐷𝑆 = 𝐼0 𝑒 𝑇 1− 𝑒 𝑇 𝑉𝐺𝑆 ≤ 𝑉𝑇𝑁
𝐿

Exponential variation with 𝑉𝐺𝑆 in W.I. Practically independent of 𝑉𝐷𝑆 for 𝑉𝐷𝑆 > (3 𝑡𝑜 4)𝑉𝑇
In log scale, slope will be given by 1Τ𝑛𝑉𝑇 [for ex. 𝑒 −4 = 0.018]

𝑛: Subthreshold slope factor; 1 ≤ 𝑛 ≤ 1.5

𝛾 ′
𝛾𝐶𝑜𝑥
𝑛=1+ 𝐼0 ≜ 𝜇𝑛 𝑉𝑇2
2 2𝜙𝐹 + 𝑉𝑆𝐵 2 2𝜙𝐹 + 𝑉𝑆𝐵

Functions of back bias

Subthreshold Slope / Swing

Subthreshold Swing (also called Subthreshold Slope) is defined as:

Change in gate-to-source voltage needed to create a decade change in drain current (in W.I. region)

∆𝑉𝐺𝑆 𝑊 (𝑉𝐺𝑆 −𝑉𝑇𝑁 )

ൗ𝑛𝑉
−𝑉𝐷𝑆
ൗ𝑉
𝑆 ≜ ቤ 𝐼𝐷𝑆 = 𝐼0 𝑒 𝑇 1− 𝑒 𝑇
∆𝐼𝐷𝑆 𝑓𝑜𝑟 𝑎 𝑑𝑒𝑐𝑎𝑑𝑒 𝑐ℎ𝑎𝑛𝑔𝑒 𝑖𝑛 𝐼 𝐿
𝐷

Exercise: Show that 𝑆 = 2.3𝑛𝑉𝑇 . Note: ∆𝐼𝐷𝑆 is in log scale i.e., 𝑆 = 𝑑𝑉𝐺𝑆 Τ𝑑(log 𝐼𝐷 )

Smaller value of 𝑆 is desirable: 𝑛 ↓

With small change in 𝑉𝐺𝑆 , 𝐼𝐷𝑆 can be drastically reduced → Turn-off

Typical values: 60-100 mV/decade

𝛾 2𝑞𝜖𝑠 𝑁𝐴
𝑛=1+ 𝛾= ′ 𝛾 ↓ 𝑜𝑟 𝑉𝑆𝐵 ↑⇒ 𝑛 ↓
2 2𝜙𝐹 + 𝑉𝑆𝐵 𝐶𝑜𝑥
 𝐼𝐷𝑆 Recall that ON current depends on 𝑉𝐺𝑆 − 𝑉𝑇𝑁

Log Scale As the supply voltages are scaled down, threshold

voltage should also be lowered to obtain same ON/OFF
ratio.

Low-voltage operations, as in many mobile applications

will be seriously affected

For any given 𝑉𝑇𝑁 , a higher steepness is desired

0.8V 1.0V 𝑉𝐺𝑆

Drain Induced Barrier Lowering (DIBL)

Gate voltage – for flat band

𝑛+ 𝑛+
Negligible drain & source voltages

Long Channel
✓ No channel depletion charge 𝐸𝐶 (𝑥) 1
✓ No channel inversion layer 𝑞𝑉𝑏𝑖 2

✓ Built-in potential at 𝑛+ 𝑝 jns. 3 𝑞𝑉𝐷𝑆

✓ Barriers for 𝑒 − s from 𝑛+ to 𝑝
𝑆 𝐶 𝐷
𝑥
 2

𝑛+ 𝑛+
Gate voltage ↑– for inversion

Negligible drain & source voltages

Long Channel

𝐸𝐶 (𝑥) 1
✓ Surface potential ↑ 𝑞𝑉𝑏𝑖 2
✓ Conduction band edge ↓
3 𝑞𝑉𝐷𝑆
✓ Barriers for 𝑒 −s from 𝑛+ to 𝑝 ↓

𝑆 𝐶 𝐷
𝑥
 3

𝑛+ 𝑛+
Gate voltage ↑– for inversion

Drain voltage ↑ Long Channel

✓ CB edge at the drain ↓ by 𝑉𝐷𝑆 𝐸𝐶 (𝑥) 1

✓ Any 𝑒 − s from S to CB can now 𝑞𝑉𝑏𝑖 2
drift towards drain
3 𝑞𝑉𝐷𝑆

𝑆 𝐶 𝐷
𝑥
𝐸𝐶 (𝑥) 𝐸𝐶 (𝑥)
1 1
𝑞𝑉𝑏𝑖 2 𝑞𝑉𝑏𝑖 2
3 𝑞𝑉𝐷𝑆 3 𝑞𝑉𝐷𝑆

𝑆 𝐶 𝐷 𝑆 𝐶 𝐷
𝑥 𝑥
Same gate voltage as in long-channel (LC) case

✓ Drain and source fields also contribute

✓ Higher surface potential than in LC case

✓ Conduction band edge will be lower in curve 1

✓ Barriers for e-s from n+ to p is smaller

𝐸𝐶 (𝑥)
✓ Easier to invert the channel – 𝑉𝑇𝑁 lowered
1
✓ Curve 2 will also be lower (than LC case) 𝑞𝑉𝑏𝑖 2
✓ Apply drain voltage – CB will be lowered
3 𝑞𝑉𝐷𝑆
✓ Drain field lines reach up to source

✓ Surface potential at source increases 𝑆 𝐶 𝐷

𝑥
✓ Reduced barrier at source

✓ Curve 3 will also be lower (than LC case)

 Effective reduction of the Higher current
onsets of all inversion regions
DIBL
𝐸𝐶 (𝑥) 𝐸𝐶 (𝑥)

1
1

𝑞𝑉𝑏𝑖 2
2

3
𝑞𝑉𝐷𝑆 3 𝑞𝑉𝐷𝑆

𝑆 𝐶 𝐷 𝑆 𝐶 𝐷

𝑥 𝑥

Increase 𝑉𝐷𝑆 ⇒ DIBL increases ⇒ Current increases in saturation as well

Model ?
Simplest way: Add multiplication term to the previous W.I. equation !

Δ𝑉𝑇𝑁|𝐷𝐼𝐵𝐿
−
𝐼𝐷|𝐷𝐼𝐵𝐿 = 𝐼𝐷|𝑁𝑜 𝐷𝐼𝐵𝐿 . 𝑒 𝑛𝑉𝑇

Example 1: Δ𝑉𝑇𝐿,𝐷𝐼𝐵𝐿 = −𝜎(Δ𝑉𝐷𝑆 ) 𝜎 ≜ DIBL Parameter Typical value: 0.01 − 0.1 𝑉 −1

𝑑𝐵𝑆 𝛽4 = 1/2 ; Fitting parameter

2𝛽4 𝑑𝐵 sinh
𝜆
𝜎= .
𝜆 𝐿 − 𝑑𝐵𝐷 𝑑 𝜆 : Characteristic length associated with DIBL
cosh − cosh 𝐵𝑆
𝜆 𝜆

−1/2
𝜖𝑜𝑥 𝑑𝐵
𝜆 = 𝑑𝐵 1+ cosh and sinh : Exponential dependence of Δ𝑉𝑇𝐿,𝐷𝐼𝐵𝐿 on 𝐿
𝜖𝑠 𝑡𝑜𝑥
Model ?
Simplest way: Add multiplication term to the previous W.I. equation !

Δ𝑉𝑇𝑁|𝐷𝐼𝐵𝐿
−
𝐼𝐷|𝐷𝐼𝐵𝐿 = 𝐼𝐷|𝑁𝑜 𝐷𝐼𝐵𝐿 . 𝑒 𝑛𝑉𝑇

1/2
𝜖𝑠 𝑡𝑜𝑥 𝑑𝐵
Example 2: Δ𝑉𝑇𝐿,𝐷𝐼𝐵𝐿 = −[3 𝑉𝑏𝑖 − 2𝜙𝐹 + 𝑉𝐷𝑆 ]𝑒 −𝐿/𝜆 𝜆= 𝑓𝑜𝑟 𝐿 ≥ 4𝑑𝐵
𝜖𝑜𝑥 𝛽5

𝛽5 = 1 ; Fitting parameter

Exponential dependence of Δ𝑉𝑇𝐿,𝐷𝐼𝐵𝐿 on 𝐿

Two-Dimensional Charge Sharing

Assume 𝑉𝐷𝑆 is very small

→ 𝑉𝑆𝐵 ≈ 𝑉𝐷𝐵
𝑄𝐵
• Channel charge is uniformly
distributed
Long Channel • Neglect contribution to depletion
charge from S & D
• Vertical field dominates

𝑄𝐵′
𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 − ′ 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 )
𝐶𝑜𝑥
~𝑄𝐵
𝑄𝐵
= 𝑉𝐹𝐵 + 2𝜙𝐹 −
𝐿 ≫ 𝑑𝐵 𝐶𝑜𝑥
 𝑄𝐵

Long Channel Short Channel

• Significant contribution to channel area

charges from S and D
• 2D field – Especially at S and D ends
• Field lines from G, S, D – All help to
~𝑄𝐵
deplete the channel and invert the
surface
𝐿 ≫ 𝑑𝐵 • Two-dimensional charge sharing
 𝑄෠𝐵′
𝑉𝑇𝑁1 = 𝑉𝐹𝐵 + 2𝜙𝐹 − ′
𝐶𝑜𝑥

𝑄𝐵 𝑄෠𝐵

Long Channel Short Channel

Highly erroneous
~𝑄𝐵 ~𝑄𝐵 approximation

𝑄෠𝐵
𝐿 ≫ 𝑑𝐵 <1
𝑄𝐵
𝐼𝐷𝑆 Surface gets inverted at lower gate voltages
Small 𝑉𝐷𝑆 due to the contributions from S/D

Thus, threshold voltage gets reduced

If 𝑉𝐷𝑆 is increased, this effect becomes more

prominent

𝑄෠𝐵′
𝑉𝑇𝑁1 = 𝑉𝐹𝐵 + 2𝜙𝐹 − ′ Arbitrary assumption,
𝐶𝑜𝑥 since charge is not
uniformly distributed
𝑄෠𝐵 under gate area
𝑉𝑇𝑁1 = 𝑉𝐹𝐵 + 2𝜙𝐹 −
𝑉𝐺𝑆 𝐶𝑜𝑥
𝑉𝑇,𝑆𝐶 𝑉𝑇,𝐿𝐶
Task: Calculate depletion charge due
to gate alone to obtain threshold voltage
 𝑄𝐵
𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 )
𝐶𝑜𝑥

𝑄෠𝐵 𝑄෠𝐵 𝑄෠𝐵 𝑄𝐵 𝑄෠𝐵

𝑉𝑇𝑁1 = 𝑉𝐹𝐵 + 2𝜙𝐹 − = × = × 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 )
𝐶𝑜𝑥 𝐶𝑜𝑥 𝑄𝐵 𝐶𝑜𝑥 𝑄𝐵

= 𝛾ො1 (2𝜙𝐹 +𝑉𝑆𝐵 )

𝛾ො1 < 𝛾
𝑄෠𝐵
Effective body effect coefficient

Short Channel 𝑄෠𝐵

Task: Calculate
𝑄𝐵
 A D
𝒅𝑩,𝒎𝒂𝒙
𝒅𝒋 n+ n+ 𝒅𝒋 𝑉𝑆 = 𝑉𝐷 = 0
B E F C
𝑉𝐺 𝑛𝑒𝑎𝑟 𝑉𝑇𝑁
𝐿 is of the order of depletion widths
𝒅𝑩𝑺 𝒅𝑩𝑫

• Total depletion ‘under the gate’ ∝ Area of the rectangle ABCD

• Approximate the charge contributions to the rectangle:

• Depletion charges in triangular areas ABE and CDF are from source and
drain respectively and the rest - from gate alone
 𝐿
A D
𝒅𝑩
𝒅𝒋
B E F C 𝒅𝒋
For 𝑑𝐵 < 𝐿/2
𝒅𝑩 𝒅𝑩

Assume

• Cylindrical n+ regions with radius 𝑑𝑗 2𝜖𝑠 (2𝜙𝐹 +𝑉𝑆𝐵 )

𝑑𝐵 =
• Depletion regions exist without interaction 𝑞𝑁𝐴

• All depletion region widths are same → 𝑑𝐵

𝑄෠𝐵 𝐴𝑟𝑒𝑎 𝐴𝐸𝐹𝐷
Task: Calculate
𝑄𝐵 = 𝐴𝑟𝑒𝑎 𝐴𝐵𝐶𝐷
 𝐴𝑟𝑒𝑎 𝐴𝐵𝐶𝐷 = 𝐴𝐷. 𝐴𝐵 = 𝐿𝑑𝐵
𝐿 𝐴𝐷 + 𝐸𝐹
Q A H G D 𝐴𝑟𝑒𝑎 𝐴𝐸𝐹𝐷 = 𝐻𝐸
2
𝒅𝑩 𝐻𝐸 = 𝑑𝐵 𝐴𝐷 = 𝐿
𝒅𝒋
B E F C 𝒅𝒋
𝐸𝐹 = 𝐵𝐶 − 𝐵𝐸 + 𝐹𝐶 = 𝐿 − 2𝐵𝐸 = 𝐿 − 2𝐴𝐻
𝒅𝑩 𝒅𝑩

2 2
𝑇𝑟𝑖𝑎𝑛𝑔𝑙𝑒 𝑄𝐸𝐻: 𝑄𝐸 2 = 𝑄𝐻2 + 𝐻𝐸 2 = (𝑄𝐴 + 𝐴𝐻)2 +𝐻𝐸 2 ⇒ 𝑑𝑗 + 𝑑𝐵 = 𝑑𝑗 + 𝐴𝐻 + 𝑑𝐵 2

𝑑𝑗 + 𝐴𝐻 = 𝑑𝑗 + 𝑑𝐵
2
− 𝑑𝐵 2 = 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 ⇒ 𝐴𝐻 = 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 − 𝑑𝑗 ⇒ 𝐸𝐹 = 𝐿 − 2 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 − 𝑑𝑗

𝐿+ 𝐿−2 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 − 𝑑𝑗
𝑑𝐵 2𝐿 − 2 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 − 𝑑𝑗
𝐴𝑟𝑒𝑎 𝐴𝐸𝐹𝐷 2 1
= = =1− 𝑑𝑗 2 + 2𝑑𝑗 𝑑𝐵 − 𝑑𝑗
𝐴𝑟𝑒𝑎 𝐴𝐵𝐶𝐷 𝐿𝑑𝐵 2𝐿 𝐿

𝑑𝑗 2𝑑𝐵
=1− 1+ −1
𝐿 𝑑𝑗
EE203 Semiconductor Devices

MOSFET - 6

Small Signal Model

 Small-Signal Model

• Assume that level-1 model is applicable

• Assume that the device is biased in saturation region i.e., it has a very high output resistance.

𝐼𝐷𝑆 𝑉𝐷𝐷
𝐼𝐷 + 𝑖𝑑
𝑉𝐺𝑆4 very small slopes
high o/p resistance 𝑉𝐵
+
𝑉𝐺𝑆3 as if it is an almost
constant current source 𝑣𝑔𝑠 = 𝑣𝑖
𝑉𝐺𝑆2
−
𝑉𝐺𝑆1 +
𝑉𝐷𝑆 𝑉𝐺𝑆
−
Instantaneous values: 𝑉𝑔𝑠 = 𝑉𝐺𝑆 + 𝑣𝑔𝑠 𝐼𝑑 = 𝐼𝐷 + 𝑖𝑑
𝑉𝐷𝐷
Assume, for now, that channel length modulation is negligible. 𝐼𝐷 + 𝑖𝑑

𝑘𝑁 2 𝑉𝐵
𝐼𝑑 = 𝑉 − 𝑉𝑇𝑁 +
2 𝑔𝑠
𝑣𝑔𝑠 = 𝑣𝑖
𝑘𝑁
𝐼𝐷 + 𝑖𝑑 = 𝑉𝐺𝑆 + 𝑣𝑖 − 𝑉𝑇𝑁 2 −
2
+
𝑘𝑁 𝑉𝐺𝑆
= 𝑉𝐺𝑆 − 𝑉𝑇𝑁 2 +2 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝑖 − 𝑣𝑖2 −
2
𝑘𝑁
= 𝐼𝐷 + 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝑖 − 𝑣𝑖2
2

𝑘𝑁 𝑣𝑖
𝑖𝑑 = 2 𝑉𝐺𝑆 − 𝑉𝑇𝑁 𝑣𝑖 − 𝑣𝑖2 = 𝑘𝑁 𝑉𝐺𝑇 𝑣𝑖 1 +
2 2𝑉𝐺𝑇

where 𝑉𝐺𝑇 = (𝑉𝐺𝑆 − 𝑉𝑇𝑁 ) is called the ‘gate overdrive’ voltage

 𝑣𝑖
𝑖𝑑 = 𝑘𝑁 𝑉𝐺𝑇 𝑣𝑖 1+
2𝑉𝐺𝑇

The small signal drain current, thus, contains linear and quadratic input voltage terms.

The true essence of a small signal model is to:

‘make the incremental change in current to be linearly proportional to the incremental change in the
applied voltage so that the circuit analysis becomes easy’.

𝑣𝑖
This can happen when ≪ 1 i.e., 𝑣𝑖 must be at least an order smaller than 2𝑉𝐺𝑇
2𝑉𝐺𝑇

MOSFETs, typically, are made to operate at a few hundred mV of gate overdrive ⇒ input voltage
should not be more than a few tens of mV.
 Model Parameters

1. Transconductance, 𝑔𝑚 : Incremental change in 𝐼𝐷 𝑖𝑑 caused by 𝜕𝐼𝐷

𝑔𝑚 ≜ ቤ
an incremental change in 𝑉𝐺𝑆 𝑣𝑔𝑠 = 𝑣𝑖 , with constant 𝑉𝐷𝑆 and 𝑉𝐵𝑆 . 𝜕𝑉𝐺𝑆 𝑉 𝑎𝑛𝑑 𝑉𝐵𝑆 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝐷𝑆

𝑘𝑁 2
𝐼𝐷 = 𝑉 − 𝑉𝑇𝑁 1 + 𝜆𝑉𝐷𝑆 ⇒ 𝑔𝑚 = 𝑘𝑁 𝑉𝐺𝑇 1 + 𝜆𝑉𝐷𝑆 = 2𝑘𝑁 𝐼𝐷 (1 + 𝜆𝑉𝐷𝑆 )
2 𝐺𝑆

A high value of 𝑔𝑚 is desirable since it determines 𝐴𝑣 𝐺 𝐷

+
Trade-offs!
𝑣𝑔𝑠
Increasing overdrive increases power dissipation 𝑔𝑚 𝑣𝑔𝑠

Increasing device area reduces packing density and increases

−
device capacitance which degrades the frequency response

𝑆
2. Body Transconductance, 𝑔𝑚𝑏 : Incremental change in 𝐼𝐷 𝑖𝑑 𝜕𝐼𝐷
𝑔𝑚𝑏 ≜ ቤ
for an incremental change in 𝑉𝐵𝑆 𝑣𝑏𝑠 with constant 𝑉𝐷𝑆 and 𝑉𝐺𝑆 . 𝜕𝑉𝐵𝑆 𝑉 𝑎𝑛𝑑 𝑉𝐺𝑆 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝐷𝑆

Change in 𝑉𝐵𝑆 ⇒ Change in 𝑉𝑇𝑁 ⇒ Change in 𝐼𝐷

𝛾 𝛾
𝑔𝑚𝑏 = 𝑔𝑚 = 𝜒𝑔𝑚 where 𝜒 =
2 2𝜙𝐹 + 𝑉𝑆𝐵 2 2𝜙𝐹 +𝑉𝑆𝐵
𝐺 𝐷

A low value of 𝑔𝑚𝑏 is desirable since a higher value reduces 𝐴𝑣 𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠
𝑣𝑔𝑠

Trade-off:

Increasing 𝑉𝑆𝐵 increases 𝑉𝑇𝑁

Consequently, higher supply voltages will be necessary 𝑣𝑏𝑠

𝑆 𝐵
3. Drain Conductance, 𝑔𝑑

𝜕𝐼𝐷 𝐺 𝐷
𝑔𝑑 ≜ ቤ
𝜕𝑉𝐷𝑆 𝑉 𝑎𝑛𝑑 𝑉𝐵𝑆 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝐺𝑆
𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠
𝑣𝑔𝑠 𝑟𝑜
𝜆𝐼𝐷
𝑔𝑑 = 𝑟𝑜−1 =
1 + 𝜆𝑉𝐷𝑆

𝑣𝑏𝑠
Output Resistance, 𝑟𝑜 = 𝑔𝑑−1
𝑆 𝐵
 4. Gate-to-Drain Capacitance 𝐶𝑔𝑑 and Gate-to-Source Capacitance 𝐶𝑔𝑠

Intrinsic capacitance:

The gate to channel capacitance is divided into two parts:

𝑊
one part to be included in gate-to-drain capacitance and
another in gate-to-source capacitance.

The division depends on the region of device operation.

One famous model is by Meyer, which gives values as: 𝐿𝐷 𝐿𝐷

Non-Saturation Region Saturation Region 𝑊

′ 𝑊𝐿 2 ′
𝐶𝑜𝑥
𝐶𝑔𝑠𝑖 = 𝐶𝑔𝑑𝑖 = 𝐶𝑔𝑠𝑖 = 𝐶 𝑊𝐿 𝐶𝑔𝑑𝑖 ≈ 0
2 3 𝑜𝑥

′ 𝑊𝐿
𝐶𝑔𝑠𝑜 = 𝐶𝑔𝑑𝑜 = 𝐶𝑜𝑥
Overlap capacitance: The gate overlaps with source and 𝐷
drain regions because of lateral diffusion of dopants
𝐶𝑔𝑑 = 𝐶𝑔𝑑𝑖 + 𝐶𝑔𝑑𝑜 𝐶𝑔𝑠 = 𝐶𝑔𝑠𝑖 + 𝐶𝑔𝑠𝑜
during fabrication process.
 𝐶𝑔𝑑

𝐺 𝐷

𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠

𝑣𝑔𝑠 𝐶𝑔𝑠 𝑟𝑜

𝑣𝑏𝑠
𝑆 𝐵
5. Source-to-Body Capacitance 𝐶𝑠𝑏 and Drain-to-body Capacitance 𝐶𝑑𝑏

𝐶𝑠𝑏0 𝐶𝑑𝑏0
𝐶𝑠𝑏 = 𝑚 𝐶𝑑𝑏 = 𝑚
𝑉 𝑉
1 + 𝑉𝑆𝐵 1 + 𝑉𝐷𝐵 𝑊
𝑏𝑖 𝑏𝑖
𝑛+ 𝑛+

Reverse biased 𝑛+ − 𝑝 junctions

𝑝 − 𝑠𝑢𝑏
𝑚: grading coefficient 𝑋𝐿 𝐿

𝐶𝑠𝑏0 and 𝐶𝑑𝑏0 : Zero-bias capacitances

(assume to be equal) 𝐶𝑠𝑏0 = 𝐶𝑑𝑏0 = 𝐶𝑗𝑠𝑤 𝑊 + 2𝑋𝐿 + 𝐶𝑗 𝑋𝐿 𝑊

Assume rectangular diffusion for ease of calculation

𝐶𝑗𝑠𝑤 : Sidewall capacitance per unit perimeter (pF/m)
𝐶𝑗 : Bottom plate capacitance per unit area (µF/m2)
One side of each diffusion is facing the channel → Not considered
 Depletion
6. Gate-to-Body Capacitance 𝐶𝑔𝑏 charges

Fringe fields between gate and depletion region outside S 𝑊 G D

channel
Capacitive effect between gate and body – Another overlap 𝐿
capacitance
Relatively, a much smaller value than other capacitances

′
𝐶𝑔𝑏 = 2𝐶𝑔𝑏𝑜 𝐿

′ 𝑾
𝐶𝑔𝑏𝑜 – gate-body overlap capacitance per unit channel length
 𝐶𝑔𝑑

𝐺 𝐷

𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠

𝑣𝑔𝑠 𝐶𝑔𝑠 𝑟𝑜

𝐶𝑔𝑏 𝐶𝑑𝑏

𝑆
𝑣𝑏𝑠
𝐶𝑠𝑏

𝐵
 7. Source and Drain Resistances

𝐺
…
G 𝑅 𝑆′ 𝑅
𝐷′
… 𝑅1 𝑆 𝐷
𝑅3
𝑅2 𝑉෨𝐷𝑆
𝑉𝐷𝑆

𝑅 = 𝑅1 + 𝑅2 + 𝑅3 𝑉෨𝐷𝑆 = 𝑉𝐷𝑆 − 2𝑅𝐼𝐷𝑆

 𝐶𝑔𝑑
𝑅𝐷
𝐷′ 𝐷
𝐺

𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠

𝐶𝑔𝑠 +
𝐶𝑔𝑏 𝑣𝑔𝑠 𝑟𝑜 𝐶𝑑𝑏
−

10 Components:
𝑆′
2 Current Sources
𝑅𝑆
𝑣𝑏𝑠 − 𝐶𝑠𝑏 5 Capacitors
+ 3 Resistors
𝑆

𝐵
Low-Frequency Model

𝐶𝑔𝑑
𝐷′
𝐺 𝐷
𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠
𝐶𝑔𝑏 𝐶𝑔𝑠 𝑟𝑜 𝐶𝑑𝑏

𝑆′

Neglecting S/D series resistances 𝐶𝑠𝑏

𝐵
 Simplified Low-Frequency Model

𝐺 𝐷
+
𝑔𝑚 𝑣𝑔𝑠 𝑔𝑚𝑏 𝑣𝑏𝑠
𝐺 𝐷
𝑣𝑔𝑠 𝑟𝑜 +
𝑔𝑚 𝑣𝑔𝑠 𝐺 𝐷
+
𝑣𝑔𝑠 𝑟𝑜 𝑔𝑚 𝑣𝑔𝑠
−
𝑆 𝑣𝑔𝑠
− −
𝑣𝑏𝑠
+ −
𝑆

𝐵 Neglecting body effect or when source and body

𝑆
are at fixed DC without AC connections
For very high
• No current flow path between gate (and body) and any other terminal output resistance
• Infinite resistance looking from gate (and body)
 Frequency Response
Task: To calculate the Unity Gain Frequency or Unity Gain Bandwidth, 𝑓𝑇 ,
defined as the frequency at which ac small-signal current gain = 1

• Gate current will flow at frequencies where the capacitive impedances

cannot be treated as open circuits 𝑖𝑖𝑛 = 𝑗𝜔(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )𝑣𝑔𝑠

• 𝐶𝑠𝑏 , 𝐶𝑔𝑏 , and 𝑟𝑜 – shorted; Neglect 𝐶𝑔𝑏

𝑖𝑜 ≈ 𝑔𝑚 𝑣𝑔𝑠
• Neglect reverse transmission of signal through 𝐶𝑔𝑑
𝑖𝑜 𝑔𝑚
≈
𝑖𝑖𝑛 𝑗𝜔(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )
𝐶𝑔𝑑
𝑖
𝑖𝑖𝑛 At 𝑓 = 𝑓𝑇 𝑖. 𝑒. , 𝜔 = 2𝜋𝑓𝑇 , 𝑖 𝑜 = 1
𝑖𝑛
𝑖𝑖𝑛 𝐶𝑔𝑠
+
𝑖𝑜 𝑣𝑔𝑠 𝑖𝑜 𝑔𝑚
+ 𝑓𝑇 =
− 𝑔𝑚 𝑣𝑔𝑠 2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑 )
𝑣𝑔𝑠
−
Maximum Frequency of Operation

𝑊
Maximum Frequency of Operation, 𝑓𝑚𝑎𝑥 ′
𝑔𝑚 ≈ 𝜇𝑛 𝐶𝑜𝑥 (𝑉 − 𝑉𝑇𝐻 )
𝐿 𝐺𝑆
• Assume channel length modulation is negligible
2
• Under saturation, 𝐶𝑔𝑑 is much smaller than 𝐶𝑔𝑠 ′ 𝑊
𝐶𝑔𝑠 = 𝐶𝑔𝑠𝑖 + 𝐶𝑔𝑠𝑜 = 𝐶𝑜𝑥 𝐿 + 𝐿𝐷
3 𝑒𝑓𝑓
• Assume overlap component is negligible
2
′ 𝑊 𝐿
𝐶𝑔𝑠 ≈ 𝐶𝑜𝑥
3
′ 𝑊 (𝑉 − 𝑉 )
𝑔𝑚 𝜇 𝐶
𝑛 𝑜𝑥 𝐿 𝐺𝑆 𝑇𝐻
𝑓𝑇 = = 3 𝜇𝑛
2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) 2 𝑓𝑚𝑎𝑥 ≈ 𝑉
′
2𝜋𝐶𝑜𝑥 𝑊3𝐿 4𝜋 𝐿2 𝐺𝑇

To obtain high frequency of operation: Reduce 𝐿, Increase 𝑉𝐺𝑇

Consequences: Short-channel effects, High power dissipation

 Example

′
An 𝑛 −channel MOSFET, having 𝑊 = 10μm, 𝐿𝑑𝑟𝑎𝑤𝑛 = 1μm, 𝑡𝑜𝑥 = 20nm, 𝑘𝑁 = 40μA/V 2 , 𝑉𝑇𝑁0 = 0.7V, 𝛾 =
′
0.4V1/2 , 2𝜙𝐹 = 0.6V, 𝐿𝐷 = 0.1μm, 𝐶𝑔𝑏𝑜 = 0.1fF/μm, 𝜆 = 0.07V −1 , 𝑉𝑏𝑖 = 0.9V, 𝑚 = 0.5, 𝐶𝑠𝑏𝑜 = 𝐶𝑑𝑏𝑜 = 2fF, is
biased with 𝑉𝐷 = 1V, 𝑉𝑆 = 0V, 𝑉𝐺 = 1.5V, and 𝑉𝐵 = −1V, with all these voltages being measured w.r.t.
ground. Determine all the ac small-signal model parameters of the device at this bias point, the unity gain
frequency, and maximum operating frequency of this device.

′ =
𝜖𝑜𝑥
𝐶𝑜𝑥 = 1.73 × 10−7 F/cm2 𝐿𝑒𝑓𝑓 = 1 − 2 × 0.1 = 0.8μm
𝑡𝑜𝑥

𝑉𝑇𝑁 = 𝑉𝑇𝑁0 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 = 0.9V

𝑉𝐷𝑆 = 1V > 𝑉𝐺𝑆 − 𝑉𝑇𝑁 = 1.5 − 0.9 = 0.6V ⇒ device in saturation

𝑘𝑁 2
𝐼𝐷 = 𝑉 − 𝑉𝑇𝑁 1 + 𝜆𝑉𝐷𝑆 = 96.3μA
2 𝐺𝑆
 Example

′
An 𝑛 −channel MOSFET, having 𝑊 = 10μm, 𝐿𝑑𝑟𝑎𝑤𝑛 = 1μm, 𝑡𝑜𝑥 = 20nm, 𝑘𝑁 = 40μA/V 2 , 𝑉𝑇𝑁0 = 0.7V, 𝛾 =
′
0.4V1/2 , 2𝜙𝐹 = 0.6V, 𝐿𝐷 = 0.1μm, 𝐶𝑔𝑏𝑜 = 0.1fF/μm, 𝜆 = 0.07V −1 , 𝑉𝑏𝑖 = 0.9V, 𝑚 = 0.5, 𝐶𝑠𝑏𝑜 = 𝐶𝑑𝑏𝑜 = 2fF, is
biased with 𝑉𝐷 = 1V, 𝑉𝑆 = 0V, 𝑉𝐺 = 1.5V, and 𝑉𝐵 = −1V, with all these voltages being measured w.r.t.
ground. Determine all the ac small-signal model parameters of the device at this bias point, the unity gain
frequency, and maximum operating frequency of this device.

′
𝑔𝑚 = 2𝑘𝑁 𝐼𝐷 (1 + 𝜆𝑉𝐷𝑆 ) = 0.32 mA/V 𝐶𝑔𝑏 = 2𝐶𝑔𝑏𝑜 𝐿𝑒𝑓𝑓 = 0.16 fF

2
𝛾 ′ 𝑊
𝐶𝑔𝑠 = 𝐶𝑔𝑠𝑖 + 𝐶𝑔𝑠𝑜 = 𝐶𝑜𝑥 𝐿 + 𝐿𝐷 = 10.96 fF
𝜒= = 0.16 3 𝑒𝑓𝑓
2 2𝜙𝐹 + 𝑉𝑆𝐵
′ 𝑊𝐿 = 1.73 fF
𝐶𝑔𝑑 = 𝐶𝑜𝑥 𝐷
𝑔𝑚𝑏 = 𝜒𝑔𝑚 = 51.4 μA/V
𝐶𝑠𝑏0
1 + 𝜆𝑉𝐷𝑆 𝐶𝑠𝑏 = 𝑚 = 1.38 fF 𝐶𝑑𝑏 = 1.11 fF
𝑟𝑜 = = 158.7 kΩ 𝑉
𝜆𝐼𝐷 1 + 𝑉𝑆𝐵
𝑏𝑖
 Example

′
An 𝑛 −channel MOSFET, having 𝑊 = 10μm, 𝐿𝑑𝑟𝑎𝑤𝑛 = 1μm, 𝑡𝑜𝑥 = 20nm, 𝑘𝑁 = 40μA/V 2 , 𝑉𝑇𝑁0 = 0.7V, 𝛾 =
′
0.4V1/2 , 2𝜙𝐹 = 0.6V, 𝐿𝐷 = 0.1μm, 𝐶𝑔𝑏𝑜 = 0.1fF/μm, 𝜆 = 0.07V −1 , 𝑉𝑏𝑖 = 0.9V, 𝑚 = 0.5, 𝐶𝑠𝑏𝑜 = 𝐶𝑑𝑏𝑜 = 2fF, is
biased with 𝑉𝐷 = 1V, 𝑉𝑆 = 0V, 𝑉𝐺 = 1.5V, and 𝑉𝐵 = −1V, with all these voltages being measured w.r.t.
ground. Determine all the ac small-signal model parameters of the device at this bias point, the unity gain
frequency, and maximum operating frequency of this device.

𝑔𝑚 ′
𝑘𝑁
𝑓𝑇 = = 4 GHz 𝜇𝑛 = ′ = 231.2 cm2 /Vs
2𝜋(𝐶𝑔𝑠 + 𝐶𝑔𝑑 ) 𝐶𝑜𝑥

3 𝜇𝑛
𝑓𝑚𝑎𝑥 ≈ 𝑉 = 7.8 GHz
4𝜋 𝐿2𝑒𝑓𝑓 𝐺𝑇
 𝑄𝐵 𝑉𝑇𝑁1
𝑉𝑇𝑁 = 𝑉𝐹𝐵 + 2𝜙𝐹 − 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 )
𝐶𝑜𝑥
𝐿1
𝑄෠𝐵
𝑉𝑇𝑁1 = 𝑉𝐹𝐵 + 2𝜙𝐹 −
𝐶𝑜𝑥

1 𝑄𝐵 𝑄෠𝐵 Δ𝑉𝑇𝑁1
𝑉𝑇𝑁1 − 𝑉𝑇𝑁 = − ෠
𝑄 − 𝑄𝐵 = − −1 𝐿2 < 𝐿1
𝐶𝑜𝑥 𝐵 𝐶𝑜𝑥 𝑄𝐵
𝑄෠𝐵
=− 1− 𝛾 (2𝜙𝐹 +𝑉𝑆𝐵 )
𝑄𝐵

𝑄෠𝐵
Δ𝑉𝑇𝑁1 =− 1− 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 𝑉𝑆𝐵
𝑄𝐵