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Up-Down Counter Testbench Code

The document contains a testbench code for an up-down counter in Verilog, which includes clock generation, reset functionality, and a sequence for counting up and down. The testbench initializes signals, toggles the clock, and monitors the count value during the simulation. Additionally, it defines the up-down counter module with asynchronous reset and counting logic based on the control signal.

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4mt22ec004
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9 views2 pages

Up-Down Counter Testbench Code

The document contains a testbench code for an up-down counter in Verilog, which includes clock generation, reset functionality, and a sequence for counting up and down. The testbench initializes signals, toggles the clock, and monitors the count value during the simulation. Additionally, it defines the up-down counter module with asynchronous reset and counting logic based on the control signal.

Uploaded by

4mt22ec004
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

test bench code

`timescale 1ns / 1ps // Time unit is 1 nanosecond, time precision is 1 picosecond

module tb_up_down_counter;

// Testbench signals
reg clk;
reg reset;
reg up_down;
wire [1:0] count;

// Instantiate the up-down counter


up_down_counter uut (
.clk(clk),
.reset(reset),
.up_down(up_down),
.count(count)
);

// Clock generation
initial begin
clk = 0;
forever #5 clk = ~clk; // Toggle clock every 5 nanoseconds
end

// Test sequence
initial begin
// Initialize signals
reset = 1; // Assert reset
up_down = 1; // Set to count up
#10; // Wait for 10 nanoseconds

reset = 0; // Deassert reset


#10; // Wait for 10 nanoseconds

// Count up
up_down = 1; // Count up
#20; // Wait for 20 nanoseconds

// Count down
up_down = 0; // Count down
#20; // Wait for 20 nanoseconds

// Reset the counter


reset = 1; // Assert reset
#10; // Wait for 10 nanoseconds
reset = 0; // Deassert reset
#10; // Wait for 10 nanoseconds

// Count down from 0


up_down = 0; // Count down
#20; // Wait for 20 nanoseconds

// Finish simulation
$finish;
end
// Monitor the count value
initial begin
$monitor("Time: %0t | Reset: %b | Up/Down: %b | Count: %b", $time, reset, up_down, count);
end

endmodule

code

`timescale 1ns / 1ps

module up_down_counter (
input wire clk, // Clock input
input wire reset, // Asynchronous reset
input wire up_down, // Up/Down control signal
output reg [1:0] count // 2-bit counter output
);
// Asynchronous reset and counter logic
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 2'b00; // Reset counter to 0
end else begin
if (up_down) begin
count <= count + 1; // Count up
end else begin
count <= count - 1; // Count down
end
end
end
endmodule

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