Digital VLSI Design Lab Lab File 3

Digital VLSI Design Lab 3:

Implementation of Multiplexers, Demultiplexers,
Encoders and Decoders
Harsh Sunil Suryawanshi
Roll No: 241060909
Branch: Electronics TY
August 2025

1 Aim
To design and simulate multiplexers, de-multiplexers, encoders and decoders using HDL
code.

2 Background / Theory

2.1 16:1 Multiplexer Using 4:1 Multiplexer

A 16:1 multiplexer is a combinational circuit that selects one input from 16 different input
lines and passes it to the output based on the combination of 4 selection lines. It has 16
inputs (D0–D15), 4 select lines (S3–S0), and one output (Y).

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Figure 1: 16:1 Multiplexer Block Diagram

Since a 4:1 multiplexer has 4 data inputs, 2 select lines, and 1 output, a larger multi-
plexer such as a 16:1 can be realized by combining multiple 4:1 multiplexers in a hierar-
chical structure.
The implementation is done in two levels:
1. First Level (Lower MUXes):

• The 16 inputs (D0–D15) are divided into 4 groups, each containing 4 inputs.

• Each group is connected to one 4:1 MUX, giving 4 outputs (Y0–Y3).

• The selection lines S1 and S0 are applied to all these 4:1 MUXes, so that each MUX
selects one input from its group.

2. Second Level (Final MUX):

• The outputs (Y0–Y3) of the first stage are applied as inputs to a fifth 4:1 MUX.

• The higher-order selection lines S3 and S2 are given to this final MUX to select one
of the four outputs (Y0–Y3).

• The output of this stage becomes the final output of the 16:1 multiplexer.

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Thus, the 16:1 multiplexer output is: Y = D(S3S2S1S0)

This means the output corresponds directly to one of the 16 inputs, depending on the
binary value of the 4 select lines. To construct a 16:1 MUX using 4:1 MUXes, a total of
5 multiplexers are required – 4 for the first stage and 1 for the final stage.
Truth Table:

Figure 2: 16:1 Multiplexer Truth Table

2.2 1:16 Demultiplexer Using 1:4 Demultiplexer

A 1:16 demultiplexer is a combinational circuit that routes a single input to one of sixteen
outputs, depending on the values of four selection lines. To implement it using 1:4
demultiplexers, we use the concept of cascading.

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Figure 3: 1:16 Demultiplexer Block Diagram

The design requires five 1:4 DEMUXs in two stages. In the first stage, one 1:4 DEMUX
is used with the two most significant select lines. This DEMUX divides the single input
into four intermediate outputs, each of which acts as an enable signal for the next stage.
In the second stage, four 1:4 DEMUXs are connected to these intermediate outputs. Each
of them is controlled by the remaining two select lines. In this way, each sub-DEMUX
produces four outputs, resulting in a total of 16 outputs.
The upper two selection lines (S3 and S2) decide which one of the four DEMUXs in
the second stage will be activated. The lower two selection lines (S1 and S0) determine
which output line within the selected DEMUX becomes active. Thus, for any given
combination of the four selection inputs, only one output among the sixteen lines carries
the input data, while all others remain at logic zero.
Hence, by combining one 1:4 DEMUX in the first stage and four 1:4 DEMUXs in the
second stage, we can construct a 1:16 DEMUX efficiently.
Truth Table:

Figure 4: 1:16 Demultiplexer Truth Table

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2.3 8:3 Encoder

An encoder is a combinational logic circuit that converts multiple input signals into a
smaller number of outputs, which represent the binary code of the active input line.

Figure 5: 8:3 Encoder Block Diagram

The 8:3 encoder has 8 input lines (Y0–Y7) and 3 output lines (A2, A1, A0). At any
time, only one input is assumed HIGH, and the encoder produces the 3-bit binary code
corresponding to that active input.
For instance:

• If Y0 = 1, output is 000

• If Y3 = 1, output is 011

• If Y7 = 1, output is 111

This reduces the 8 inputs into just 3 output bits. The 8:3 encoder has 8 inputs
(Y0–Y7) and 3 outputs (A2, A1, A0). Only one input is HIGH (1) at a time; the encoder
converts this active input into its binary equivalent at the outputs. Thus, the encoder
reduces 8 inputs into 3 output lines, providing a compact binary code.
Truth Table:

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Figure 6: 8:3 Encoder Truth Table

2.4 3:8 Decoder

A decoder is a combinational circuit that performs the reverse operation of an encoder.
It converts n input binary lines into 2n unique output lines.

Figure 7: 3:8 Decoder Block Diagram

A 3-to-8 decoder has 3 inputs (Ip0, Ip1, Ip2) and 8 outputs (Op0–Op7). Depending
on the binary combination of inputs, exactly one output becomes HIGH (1) while all
others remain LOW (0).
For example:

• If inputs = 000 → Op0 = 1

• If inputs = 011 → Op3 = 1

• If inputs = 111 → Op7 = 1

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Thus, the decoder decodes the 3-bit binary input into one of 8 active outputs.
Truth Table:

Figure 8: 3:8 Decoder Truth Table

2.5 8:3 Priority Encoder

An encoder converts multiple inputs into a binary output code. However, in a normal
encoder, if more than one input is HIGH at the same time, the output becomes undefined.

Figure 9: 8:3 Priority Encoder Block Diagram

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To solve this, a priority encoder is used. It assigns a priority order to inputs. In an

8-to-3 priority encoder, there are 8 inputs (D0–D7) and 3 outputs (Q2, Q1, Q0). The
highest-numbered input has the highest priority (D7 is highest, D0 is lowest). If multiple
inputs are active simultaneously, the output corresponds to the highest-priority active
input.

3 Materials and Methods

• Hardware Description Language: Verilog HDL • Simulation Tool: Xilinx Vivado
v2025.1 • Schematic/Layout and Output Tool: Xilinx Vivado

4 Experimental Procedure
1. Design the circuit architectures for multiplexers, demultiplexers, encoders and de-
coders 2. Develop Verilog HDL modules for each circuit 3. Create testbenches with
comprehensive test scenarios 4. Execute simulations and analyze waveform outputs for
correctness 5. Verify functionality through all input combinations 6. Document results
and compare with expected outputs

5 Results

5.1 Verilog Code Implementation

5.1.1 16:1 Multiplexer Module

1 module Mux_16to1 ( in , set , out ) ;

2 input wire [15:0] in ;
3 input wire [3:0] set ;
4 output wire out ;
5 wire [3:0] mux4x1_out ;
6 Mux_4to1 m1 (. in ( in [3:0]) , . set ( set [1:0]) , . out ( mux4x1_out [0]) ) ;
7 Mux_4to1 m2 (. in ( in [7:4]) , . set ( set [1:0]) , . out ( mux4x1_out [1]) ) ;
8 Mux_4to1 m3 (. in ( in [11:8]) , . set ( set [1:0]) , . out ( mux4x1_out [2]) ) ;
9 Mux_4to1 m4 (. in ( in [15:12]) , . set ( set [1:0]) , . out ( mux4x1_out [3]) ) ;
10 Mux_4to1 m5 (. in ( mux4x1_out ) , . set ( set [3:2]) , . out ( out ) ) ;
11 endmodule

Listing 1: 16:1 Multiplexer using 4:1 Multiplexers

5.1.2 16:1 Multiplexer Testbench

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1 module Mux_16to1_tb () ;
2 reg [15:0] in ;
3 reg [3:0] set ;
4 wire out ;
5 Mux_16to1 mux16x1 ( in , set , out ) ;
6 initial begin
7 in = 16 ’ b1 111000 011110 000 ;
8 set = 4 ’ b0000 ; #10;
9 set = 4 ’ b0001 ; #10;
10 set = 4 ’ b0010 ; #10;
11 set = 4 ’ b0011 ; #10;
12 set = 4 ’ b0100 ; #10;
13 set = 4 ’ b1111 ; #10;
14 $finish ;
15 end
16 endmodule

Listing 2: 16:1 Multiplexer Testbench

5.1.3 1:16 Demultiplexer Module

1 module demux16x1 ( in , set , out ) ;

2 input in ;
3 input [3:0] set ;
4 output [15:0] out ;
5

6 wire [3:0] demux1x4_out ;

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8 demux1x4 DM0 (. in ( in ) , . set ( set [3:2]) , . out ( demux1x4_out ) ) ;

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10 demux1x4 DM1 (. in ( demux1x4_out [0]) , . set ( set [1:0]) , . out ( out [3:0]) ) ;
11 demux1x4 DM2 (. in ( demux1x4_out [1]) , . set ( set [1:0]) , . out ( out [7:4]) ) ;
12 demux1x4 DM3 (. in ( demux1x4_out [2]) , . set ( set [1:0]) , . out ( out [11:8]) ) ;
13 demux1x4 DM4 (. in ( demux1x4_out [3]) , . set ( set [1:0]) , . out ( out [15:12]) ) ;
14

15 endmodule

Listing 3: 1:16 Demultiplexer using 1:4 Demultiplexers

5.1.4 1:16 Demultiplexer Testbench

1 module demux1x16_tb () ;
2 reg in ;
3 reg [3:0] set ;
4 wire [15:0] out ;
5 demux16x1 DMX ( in , set , out ) ;

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6 initial begin
7

8 in = 1 ’ b1 ;
9 set = 4 ’ b1100 ; #10;
10 set = 4 ’ b1101 ; #10;
11 set = 4 ’ b1110 ; #10;
12 set = 4 ’ b1111 ; #10;
13 $finish ;
14 end
15 endmodule

Listing 4: 1:16 Demultiplexer Testbench

5.1.5 8:3 Encoder Module

1 module encoder8to3 ( in , out ) ;

2 input [7:0] in ;
3 output reg [2:0] out ;
4 always @ (*)
5 begin
6

7 case ( in )
8 8 ’ b00000001 : out = 3 ’ b000 ;
9 8 ’ b00000010 : out = 3 ’ b001 ;
10 8 ’ b00000100 : out = 3 ’ b010 ;
11 8 ’ b00001000 : out = 3 ’ b011 ;
12 8 ’ b00010000 : out = 3 ’ b100 ;
13 8 ’ b00100000 : out = 3 ’ b101 ;
14 8 ’ b01000000 : out = 3 ’ b110 ;
15 8 ’ b10000000 : out = 3 ’ b111 ;
16 endcase
17 end
18 endmodule

Listing 5: 8:3 Encoder

5.1.6 8:3 Encoder Testbench

1 module encoder8to3_tb () ;
2 reg [7:0] in ;
3 wire [2:0] out ;
4 encoder8to3 E ( in , out ) ;
5 initial
6 begin
7 in = 8 ’ b00000001 ;#10;
8 in = 8 ’ b00000010 ;#10;

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9 in = 8 ’ b00000100 ;#10;
10 in = 8 ’ b00001000 ;#10;
11 in = 8 ’ b00010000 ;#10;
12 in = 8 ’ b00100000 ;#10;
13 in = 8 ’ b01000000 ;#10;
14 in = 8 ’ b10000000 ;#10;
15 $finish ;
16 end
17 endmodule

Listing 6: 8:3 Encoder Testbench

5.1.7 3:8 Decoder Module

1 module decoder3to8 ( in , out ) ;

2 input [2:0] in ;
3 output reg [7:0] out ;
4 always @ (*)
5 begin
6

7 case ( in )
8 3 ’ b000 : out = 8 ’ b00000001 ;
9 3 ’ b001 : out = 8 ’ b00000010 ;
10 3 ’ b010 : out = 8 ’ b00000100 ;
11 3 ’ b011 : out = 8 ’ b00001000 ;
12 3 ’ b100 : out = 8 ’ b00010000 ;
13 3 ’ b101 : out = 8 ’ b00100000 ;
14 3 ’ b110 : out = 8 ’ b01000000 ;
15 3 ’ b111 : out = 8 ’ b10000000 ;
16 endcase
17 end
18 endmodule

Listing 7: 3:8 Decoder

5.1.8 3:8 Decoder Testbench

1 module decoder3to8_tb () ;
2 reg [2:0] in ;
3 wire [7:0] out ;
4 decoder3to8 D3 ( in , out ) ;
5 initial
6 begin
7 in = 3 ’ b000 ;#10;
8 in = 3 ’ b001 ;#10;
9 in = 3 ’ b010 ;#10;

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10 in = 3 ’ b011 ;#10;
11 in = 3 ’ b100 ;#10;
12 in = 3 ’ b101 ;#10;
13 in = 3 ’ b110 ;#10;
14 in = 3 ’ b111 ;#10;
15 end
16 endmodule

Listing 8: 3:8 Decoder Testbench

5.1.9 8:3 Priority Encoder Module

1 module p ri or it ye nc od er 8x 3 ( in , out ) ;
2 input [7:0] in ;
3 output reg [2:0] out ;
4 always @ (*)
5 begin
6

7 case ( in )
8 8 ’ b00000001 : out = 3 ’ b000 ;
9 8 ’ b0000001x : out = 3 ’ b001 ;
10 8 ’ b000001xx : out = 3 ’ b010 ;
11 8 ’ b00001xxx : out = 3 ’ b011 ;
12 8 ’ b0001xxxx : out = 3 ’ b100 ;
13 8 ’ b001xxxxx : out = 3 ’ b101 ;
14 8 ’ b01xxxxxx : out = 3 ’ b110 ;
15 8 ’ b1xxxxxxx : out = 3 ’ b111 ;
16 endcase
17 end
18 endmodule

Listing 9: 8:3 Priority Encoder

5.1.10 8:3 Priority Encoder Testbench

1 module p r i o r i t y e n c o d e r 8 x 3 _ t b () ;
2 reg [7:0] in ;
3 wire [2:0] out ;
4 pr io ri ty en co de r8 x3 En ( in , out ) ;
5 initial
6 begin
7 in = 8 ’ b00000001 ;#10;
8 in = 8 ’ b0000001x ;#10;
9 in = 8 ’ b000001xx ;#10;
10 in = 8 ’ b00001xxx ;#10;
11 in = 8 ’ b0001xxxx ;#10;

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12 in = 8 ’ b001xxxxx ;#10;
13 in = 8 ’ b01xxxxxx ;#10;
14 in = 8 ’ b1xxxxxxx ;#10;
15 $finish ;
16 end
17 endmodule

Listing 10: 8:3 Priority Encoder Testbench

6 Circuit Diagrams and Simulation Results

6.1 16:1 Mux using 4:1 Mux

Figure 10: 16:1 Multiplexer RTL Schematic

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Figure 11: 16:1 Multiplexer Simulation Waveform

6.2 1:16 De-mux using 1:4 De-Mux

Figure 12: 1:16 Demultiplexer RTL Schematic

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Figure 13: 1:16 Demultiplexer Simulation Waveform

6.3 8:3 Encoder

Figure 14: 8:3 Encoder RTL Schematic

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Figure 15: 8:3 Encoder Simulation Waveform

6.4 3:8 Decoder

Figure 16: 3:8 Decoder RTL Schematic

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Figure 17: 3:8 Decoder Simulation Waveform

6.5 8:3 Priority Encoder

Figure 18: 8:3 Priority Encoder RTL Schematic

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Figure 19: 8:3 Priority Encoder Simulation Waveform

The simulation results demonstrate successful implementation of all designed circuits.

The outputs match the expected results for all test cases, confirming correct logical op-
eration and proper functionality of multiplexers, demultiplexers, encoders, and decoders.
The waveform analysis shows the characteristic behavior of each circuit type with proper
signal routing and code conversion.

7 Analysis and Discussion

The simulation results demonstrate successful implementation of the multiplexer, demul-
tiplexer, encoder, and decoder circuits. The outputs match the expected results for all test
cases, confirming correct logical operation and proper signal routing through all stages.
The hierarchical design approach using smaller building blocks provides a clear and sys-
tematic method for implementing larger circuits, making them suitable for educational
purposes and practical digital system applications.
The 16:1 multiplexer successfully demonstrated data selection from 16 inputs based
on 4-bit select signals. The 1:16 demultiplexer correctly distributed input data to the
appropriate output line. Both encoder implementations (standard and priority) showed
accurate binary code generation, with the priority encoder properly handling multiple
simultaneous inputs.

8 Observations
Based on the simulation results and analysis of the implemented circuits, the following
observations were made:

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1. 16:1 Multiplexer Performance: The hierarchical implementation using 4:1 multi-

plexers successfully demonstrated correct data selection functionality. All 16 input
combinations were properly routed to the output based on the 4-bit select signal.

2. 1:16 Demultiplexer Functionality: The cascaded 1:4 demultiplexer structure effec-

tively distributed the input data to the correct output line. Only one output was
active at any given time, confirming proper demultiplexing operation.

3. 8:3 Encoder Behavior : The encoder correctly converted one-hot encoded inputs to
their corresponding 3-bit binary outputs. Each input line produced its expected
binary representation at the output.

4. 3:8 Decoder Operation: The decoder successfully converted 3-bit binary inputs to
activate the corresponding output lines. The one-hot output pattern was correctly
generated for all input combinations.

5. 8:3 Priority Encoder : The priority encoder demonstrated proper priority handling
when multiple inputs were simultaneously active. The highest priority input always
dominated the output, confirming the priority mechanism.

6. Timing Analysis: All circuits exhibited acceptable propagation delays suitable for
digital system applications. The critical path timing met design requirements.

7. Resource Utilization: The HDL synthesis results showed efficient use of FPGA
resources with optimal logic implementation for each circuit.

9 Conclusion
The multiplexers, demultiplexers, encoders, and decoders have been successfully designed,
implemented in Verilog HDL, and verified through simulation. The results demonstrate
accurate data routing, selection, and code conversion mechanisms. The hierarchical ap-
proach using smaller building blocks provides a fundamental understanding of complex
digital circuit design and serves as essential components for larger digital systems in VLSI
design.
The design and simulation of multiplexers, demultiplexers, encoders, and decoders
using Verilog HDL were successfully performed. The results verified that each circuit
produced correct outputs for all given input conditions. Through this experiment, the
fundamental concepts of data selection, distribution, and code conversion were reinforced.
Additionally, it provided hands-on experience with HDL-based modeling and simulation,
which is essential for digital logic design and VLSI applications.

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